KR100202979B1 - Apparatus for automatically changing maintenance-bus for inter-processor communication in a switching system - Google Patents

Abstract

The present invention relates to an MBS switching device for controlling inter-processor communication in an all-electronic exchanger, and more particularly, to an MBS switching device for inter-processor communication control in which a MAINTENANCE-BUS (hereinafter referred to as M-BUS) The present invention relates to an M-BUS switching device for controlling inter-processor communication in an all-electronic exchanger so that the M-BUS can be automatically switched and used. BUS status check, and performs switching of M-BUS when there is no response from one or more of the interface units 62-69, and each interface unit 62-69 transmits M- - It can monitor the BUS clock and perform the M-BUS transfer more quickly than when the M-BUS is abnormal.

Description

An inter-processor inter-processor for controlling inter-processor communication in all electronic exchanges

FIG. 1 is a schematic block diagram of an IPC for inter-processor communication in a full-duplexer; FIG.

FIG. 2 is a detailed block diagram of the IPC of FIG. 1; FIG.

3 is a block diagram of an M-BUS switching device according to the present invention;

DESCRIPTION OF THE REFERENCE NUMERALS

10, 20, 30, 40, 50: first, second, third, fourth, N processors 60: IPC

61: IPC control unit 62-69: 1-8 interface unit

1: clock generating unit 2, a: first and second microcomputers

3,5, c, e: first, second, third, fourth, transceiver 4,6, b, d: first,

f: clock monitoring unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MBA switching device for controlling inter-processor communication in an all-electronic exchange, and more particularly, to an MBA (MAINTENANCE-BUS: hereinafter referred to as M-BUS) To an inter-processor communication in an all-electronic exchanger that can be automatically switched and used.

In general, a plurality of inter-processor communication in an electronic exchanger is performed based on an Inter-Processor Communication (IPC) scheme as shown in FIG. 1, and this IPC block 60 includes all the processors 10, 20, 30, 40, and 50), and monitors and controls various states of all nodes connected to the processors in the IPC block.

In more detail, the IPC block 60 is a block for transmitting control messages and data for communication between functional processors dispersed in all electronic exchanges adopting a distributed processing structure. And a plurality of interface units 62-69 that include an IPC control unit 61 that performs a management role and interfaces with a processor connected to each node (NODE).

In the present invention, the TDX-100 currently being developed will be described as an example. In the TDX-100, there are eight interface units, and each interface has a node capable of connecting eight processors again.

In order to stabilize the system, the IPC control unit 61 controls each node to which each processor is connected through a duplicated M-BUS. D-BUS is used for data transmission and reception between the processors, and the IPC control unit 61 to each of the interface units 62-69 using a clock line.

On the other hand, if the A-BUS is selected as the default, A-BUS is selected for redundant M-BUS (A-BUS, B-BUS)

The IPC control unit 61 transmits the same M-BUS clock to the A-BUS and B-BUS with the redundant M-BUS (A-BUS, B-BUS) Processor communicates control messages for maintenance and repair through the M-BUS data line based on the M-BUS clock of the selected M-BUS (A-BUS, B-BUS).

However, as a method of switching the duplicated M-BUS, the IPC control unit 61 may transmit a message for bus switching to each of the interface units 62-69 so that each of the interface units 62-69 sends a duplicated M- BUS or A-BUS. However, when the interface unit 62-69 can not receive the bus solicitation message due to an abnormality of the M-BUS, it takes a lot of time to transfer the bus there was.

Accordingly, an object of the present invention is to provide a method and apparatus for transmitting a message for checking an M-BUS state at a predetermined cycle in the IPC control unit 61 to the above-mentioned M-BUS switch for controlling inter- 69, the interface unit 62-69 monitors the M-BUS clock to perform an M-BUS transfer more quickly than when the M-BUS is abnormal. The present invention is to provide an MBS switching device for controlling communication between processors in a whole electronic switching system.

The MBS switching device for controlling the inter-processor communication in the exchange according to the present invention is a channel for maintenance of IPC communication between the IPC control part 61 and a plurality of interface parts 62 connected to a plurality of processors, An apparatus for switching a dual-used M-Bus to be used, the apparatus comprising: a clock generating unit (1) for generating a predetermined M-BUS clock; A first transmission / reception and matching unit (3, 4) enabled based on a first enable signal and transmitting / receiving a control message based on an M-BUS clock from the clock generation unit (1); Receiving and matching sections (5, 6) for enabling the first transmission / reception and matching sections (3, 4) to be enabled based on a second enable signal; A control message for checking the state of the bus is generated at a predetermined cycle by the first transmission / reception unit 3 and the second transmission / reception unit 4 and the second transmission / reception unit 5, 6, and a control message for the received bus state response And a first microcomputer 2 for selectively applying the first and second enable signals to the first and second matching sections 4 and 6 in accordance with a control signal from the IPC control section 61 ; Receiving and matching units c and d that are enabled based on the third enable signal and are connected to the data transmission line MDATA and the clock line MCLK for transmission / reception with the first transmission / reception and matching units 3 and 4, b); Receiving and matching sections e and d that are enabled based on the fourth enable signal and connected to the data transmission line MDATA and the clock line MCLK for transmission / reception with the second transmission / reception and matching sections 5 and 6, d); A clock monitoring unit (f) for checking each of the M-BUS clocks output from the third and fourth matching units (4,6) and outputting a predetermined bus monitoring signal; And a second microcomputer (a) for interfacing with a plurality of processors connected to the node and selectively outputting the third and fourth enable signals based on a bus supervisory signal from the clock supervising section (f) And at least one interface unit 62.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an M-BUS switching apparatus according to the present invention. The IPC control unit 61 includes a clock generation unit 1, a first microcomputer 2, a first transmission / reception unit 3, The interface unit 62 includes a second microcomputer (a), a third matching unit (b), a third matching unit (b), and a third matching unit A transmission / reception unit c, a fourth matching unit d, a fourth transmission / reception unit e, and a clock monitoring unit f.

In the figure, the clock generator 1 generates an M-BUS clock for M-BUS. The first microcomputer 2 generates and outputs a control message for checking the bus state at predetermined intervals, And selectively outputs the first and second enable signals for M-BUS switching based on the status response message.

The first transmission / reception unit 30 transmits a control message from the first microcomputer 2 based on the M-BUS clock signal from the clock generation unit 1 or transmits a control message to the first microcomputer 2 And the second transmission / reception unit 5 is duplicated with the first transmission / reception unit 3 and performs the same function.

The first matching unit 4 is enabled by the first enable signal of the first microcomputer 2 as an interface means for serial communication in accordance with the RS-485 standard, and receives control data from the first transmitting and receiving unit 3 And the M-BUS clock and outputs the control data from the interface unit 62 to the first transceiver 3. The second matching unit 6 receives the control data from the first matching unit 4 Receiving unit 5 and is enabled based on the second enable signal of the first microcomputer 2. In this case,

The second microcomputer (a) of the interface unit 62 generates and outputs a control message for the bus status response in response to the control message for checking the bus status from the third and fourth transmission / reception units (c, e) , And detects the M-BUS change based on the bus monitor signal from the clock monitoring unit (f) to be described later, and selectively outputs the third and fourth enable signals to perform the M-BUS switch.

On the other hand, the third matching unit b and the fourth matching unit d are duplexed and used as means for performing serial communication in accordance with the RS-485 standard, respectively, on the basis of the third and fourth enable signals from the second microcomputer (a) And performs matching between the second matching unit 6 and the fourth transmitting and receiving unit e between the first matching unit 4 and the third transmitting and receiving unit c.

The third transmission / reception unit (c) receives the control message from the third matching unit (b) based on the M-BUS clock from the third matching unit (b) and transfers it to the second microcomputer (a) The fourth transmitting and receiving unit e receives the control message from the second microcomputer a to the third matching unit b and the fourth transmitting and receiving unit e is duplicated with the third transmitting and receiving unit c to perform the same function as the fourth matching unit d. .

On the other hand, the clock monitoring unit (f) checks the M-BUS clocks output from the third and fourth matching units (b, d) and transfers the predetermined bus monitoring signal to the second microcomputer (a).

The operation procedure of the present invention including the above-described components, that is, the switching process of the duplicated M-BUS will be described in detail.

First, the first microcomputer 2 of the IPC control unit 61 generates and outputs a predetermined control message for checking the state of the bus at predetermined intervals in order to monitor an abnormal state of the M-BUS from time to time.

When the currently used M-BUS channel is A-BUS, a predetermined control message for checking the status of the bus is transmitted to the first transmission / reception unit 3 through the first transmission / reception unit 3 and the first matching unit 4, Is applied to the second microcomputer (a) through the third matching section (b) of the interface section (62-69) and the third transmitting / receiving section (c).

Then, the second microcomputer (a) generates a predetermined control message for the bus status response in response to the predetermined control message for the bus status check and transmits the predetermined control message to the third transmission / reception unit (c) Is transmitted to the first microcomputer 2 through the first matching section 4 and the first transceiver section 3 of the IPC control section 61 via the third matching section b.

At this time, when all the predetermined control messages for the bus status response are received from the respective interface units 62-69, the first microcomputer 2 recognizes the A-BUS of the currently used M-BUS as a normal state, And does not perform switching.

However, if a message for a bus status response is not transmitted from any one of the interface units 62-69, the first microcomputer 2 of the IPC control unit 61 transfers the M-BUS to the B-BUS The first enable signal is stopped to be applied to the first matching portion 4 and the second enable signal is applied to the second matching portion 6. [

Then, the driving of the first matching unit 4 connected to the A-BUS is stopped, and the second matching unit 6 is driven to activate the B-BUS.

Therefore, the output of the M-BUS clock output from the first matching unit 4 is stopped and the M-BUS clock is output from the second matching unit 6.

At this time, the clock monitoring unit (f) of each of the interfaces (62-69) does not detect the M-BUS clock output from the third matching unit (b).

Accordingly, the clock monitoring unit f applies a bus monitor signal indicating that the M-BUS clock is not detected from the third matching unit (b) connected to the activated A-BUS to the second microcomputer (a) .

Then, the second microcomputer (a) stops applying the third enable signal to the third matching section (b) based on the bus supervisory signal from the clock monitoring section (f), and stops the fourth enable signal to the fourth B-BUS to which the fourth matching portion (d) is connected is activated by applying it to the matching portion (d) to switch the M-BUS.

As described above, according to the present invention, it is possible to perform the M-BUS switching more quickly than when the M-BUS is abnormal by monitoring the M-BUS clock for switching the M-BUS, It is effective.

Claims (1)

An apparatus for switching a redundant M-BUS used as a channel for IPC communication maintenance between an IPC control unit 61 and a plurality of interface units 62 connected to a plurality of processors, A clock generating unit (1) generating the clock; A first transmission / reception and matching unit (3, 4) which is enabled based on a first enable signal and transmits / receives a control message based on the M-BUS clock from the clock generation unit (1); A second transmission / reception and matching unit (5, 6) enabled based on a second enable signal to duplicate the first transmission / reception and matching unit (3, 4); A control message for checking the state of the bus is generated at a predetermined cycle by the first transmitting / receiving unit 3, 4 and the second transmitting / receiving unit 5, 6, and a control message for the received bus state response And a first microcomputer (2) selectively applying the first and second enable signals to the first and second matching sections (4, 6) to switch the M-BUS, ; Receiving and matching units c and d that are enabled based on the third enable signal and are connected to the data transmission line MDATA and the clock line MCLK for transmission / reception with the first transmission / reception and matching units 3 and 4, d); Receiving and matching sections e and d that are enabled based on the fourth enable signal and connected to the data transmission line MDATA and the clock line MCLK for transmission / reception with the second transmission / reception and matching sections 5 and 6, d); A clock monitoring unit (f) for checking each of the M-BUS clocks output from the third and fourth matching units (4,6) and outputting a predetermined bus monitoring signal; And a second microcomputer (a) for interfacing with a plurality of processors connected to the node and selectively outputting the third and fourth enable signals based on a bus supervisory signal from the clock supervising section (f) And an inter-processor communication in an electronic exchanger including at least one interface unit (62).