GB1573329A - Method and apparatu for detecting errors in parity encoded data - Google Patents

Description

(54) METHOD AND APPARATUS FOR DETECTING ERRORS IN PARI1 ENCODED DATA (71) We, HONEYWELL INFORMA TION SYSTEMS INC., a corporation organised and existing under the laws of the State of Delaware, United States of America, of 200 Smith Street, Waltham, Massachusetts 02154, United States of America, do hereby declare the invention for which we pray that a Patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement: This invention relates generally to data processing systems and more particularly to methods of error detection and correction and to apparatus therefor included within the memory of a data processing system.

It is well known to utilize metal oxide semiconductor field effect transistor (MOS FET) memory elements in main memory systems. Since such memories are volatile in nature and require continual restoration of the stored information, error detection and correction apparatus are normally included within such memory systems for ensuring the integrity of the stored information.

Generally, main storage systems utilize a modified Hamming code for single error detection/double error detection. Normally, such codes increase significantly the number of memory circuits.

In order to increase memory reliability notwithstanding attendant increases in error detection and correction circuits, at least one system utilizes codes which improve upon the modified Hamming SEC/DED codes and simplify the memory circuit implementation as well as provide faster and better error detection capability. This arrangement is described in a paper "A Class of Optimal Minimum Odd-Weight Column SEC/DED Codes" by M. Y. Hsiao which appears in the publication "IBM Journal of Research and Development", July, 1970. The construction of such codes is described in terms of a parity check matrix H. The selection of the columns of the H matrix for a given (n, k) code is based upon the following constraints: 1. Every column should have an odd number one's; 2. The total number of one's in the H matrix should be a minimum; and, 3. The number of one's in each row of the H matrix should be made equal or as close as possible to the average number.

Errors are indicated by analyzing the syndromes formed from the data and check code bits. An odd number of syndrome bits indicates a single error while an even number of syndrome bits indicates a double or uncorrectable error.

In the above mentioned arrangement as well as other prior art systems, while reducing the amount of circuits by observing the constraints mentioned above, such systems still require large numbers of multiinput AND error locator circuits as well as circuits for generating parity bit signals for the data read out of memory. Thus, the disadvantages of such arrangements are their higher cost, complexity in implementation and lower reliability. That is, if the implementation requires fewer circuits and connections, its chance of failure is decreased. Also, such systems may require construction of special circuits which would also result in higher cost.

In general, operations for decoding or encoding data and check bits in prior art memory systems proceed as follows. Normally, during a read operation, a word is read from a main memory location and the data bits together with check code bits are stored in a data storage register. Byte parity bits are generated from the data bits. The syndromes formed from the data and code check bits are analyzed. If no error is indicated, the byte parity encoded data is transmitted onto the data bus. If a double code error is indicated, a program interrupt signal is generated and the error data are made available for program analysis. In the case where a single error is signalled, the correction circuits correct the data.

In the case of a write operation, the byte encoded parity word is received from the data bus and the check code bits are generated for the SEC/DED code. The received byte parity bits are examined for validity. When no error is detected, the coded word is stored into a memory location. In the event of a double error, the write operation is aborted and the data processing system is notified of the error.

Additionally, such prior art memory systems are required to perform "partial write" operations. The partial write operation occurs when a portion of data word (i.e., a byte) stored in memory is read out and altered by new data and thereafter written into memory. Prior art memory systems handle partial write operations similar to that described above. That is, the data to be written into memory is checked. When a double error is indicated, the operation is aborted and the data processing system is notified.

The above arrangements have been found to be unsuitable for use in systems where data is transferred along a common data bus at a rapid rate. In such instances, by the time the parity encoded data word can be checked, the data source applying the data will have relinquished its control of the bus.

Accordingly, the arrangement requires that the sending source be connected to the bus until the parity encoded data can be checked. This results in reducing the overall throughput of the data processing system.

Also, at least one of the above mentioned prior art systems has employed an arrangement which utilizes address parity bits as data bits and includes such bits in the generation of check code bits. While the arrangement is able to signal when an incorrect location is being accessed, the address parity bits provide no indication regarding the integrity of the data being written into memory.

Accordingly, it is a primary object of the present invention to provide an improved method and apparatus for detecting errors in parity encoded data applied from any one of a plurality of input/output sources for storage in a memory system.

Thus in accordance with the invention there is provided a method of detecting errors in groups of signals received from a bus network for storage in a memory pertaining to which is a data processor subsystem containing encoder and decoder circuits respectively at the input and output of the memory, each of said groups of signals including a plurality of data bit signals and at least one parity bit signal for indicating the validity of said plurality of data bit signals, said method comprising applying to said encoder circuits during a memory cycle of operation a group of signals received from said bus for writing in said memory, generating a group of check code bit signals by said encoder circuits from said plurality of data bit signals and said one parity bit signal of said group and forcing a number of said check code bit signals to a predetermined state when said one parity bit signal indicates that said data bit signals received from said bus are in error, storing in said memory only said data bit signals and said check bit signals of said group during said memory cycle of operation, reading said stored data and check code bit signals from said memory, generating a plurality of syndrome signals by said decoder circuits from the said signals read from the memory and forcing said plurality of syndrome signals to have a first predetermined characteristic for signalling when said group of data bit signals had incorrect parity when written into said memory enabling detection of incorrect signals without decreasing the operating speed of said data handling devices.

The invention also provides a memory subsystem for detecting errors in recorded data provided on a bus of an associated data processing system comprising an addressable memory for storing groups of signals, input means coupled to said bus for receiving said groups of signals occurring thereon, each said group of signals including a plurality of unchecked data bit signals and at least one parity bit signal for indicating the validity of said data bit signals, an encoder, coupled to said input means and to said memory, which generates a group of check code bits derived from a group of said unchecked data bit signals and said one parity bit signal, said encoder forcing a number of said check code bit signals to predetermined states when said one parity bit signal designates that said unchecked data bit signals are in error, transfer means connected to said encoder and to said input means which applies said unchecked data bit signals and group of check code bit siganls to said memory for said storage during a memory cycle of operation, and a decoder coupled to said memory which generates a plurality of syndrome signals characterised for locating an error in said data bit signals, the location of said error being established by said unchecked data bit signals and said check code bit signals, both sets of signals being read out from said memory during a subsequent cycle of operation.

In a preferred embodiment, there are encoder circuits which couple to the input circuits of a memory system and decoder circuits which couple to the output circuits of the memory system. The decoder circuits connect to error correction circuits which transmit to the bus and the encoder circuits are connected to receive from the bus data bit signals and parity bit signals by and one of a number of input/output devices. During a write memory cycle of operation, the encoder circuits generate a predetermined number of coded check bits from the unchecked data signals and associated parity bits received from any one of the devices.

Thereafter, the data signals and generated check code bits are written into memory.

The encoder circuits are operative to force selectively the check code bits to predetermined states when the parity bits of the unchecked data indicate that such data is an error. During a subsequent read cycle of operation, the decoder circuits are conditioned by the check code bits to generate selectively syndrome bits having a first predetermined characteristic for signalling that the data was in error when it was initially written into memory.

The characteristic is that the syndrome bits contain an even number of binary ONES indicative of an uncorrectable error condition. In the case where the input data has correct parity, the decoder circuits generate syndrome bits having the first predetermined characteristic only when a double error occurs as a consequence of a failure or fault within the memory system or its associated circuits. In all other instances, the decoder circuits generate syndrome bits having a second predetermined characteristic which corresponds to the syndrome bits having an odd number of binary ONES indicative of a single error condition. In response to such single bit error coniditions, the correction circuits correct the condition automatically and produce parity bits from the data and check code bits which are thereafter applied to the bus together with the data bits.

In the case of a "partial write" operation, when the double error condition is detected by the decoder circuits during the read portion of the operation, the error conditions the encoder circuits to force the check code bits to a predetermined state. That is, the check code bits are forced to a predetermined state which condition the decoding circuits during a subsequent read cycle to generate syndrome bits having the first predetermined characteristic.

From the above, it is seen that the arrangement is able to automatically signal the occurrence of errors related to the correctness of unchecked data written into memory. Since it is essential that such errors not be corrected, they produce uncorrectable error indications. By eliminating the need to provide circuits for checking data before it is written into memory, the present invention reduces the amount of additional circuits. It also eliminates the need to include parity bits in memory.

More importantly, the present invention enables data transfers to take place at a maximum rate in that the invention eliminates the necessity for requiring checking of the parity encoded data words before being written into memory.

Additionally, the arrangement of the present invention facilitates the detection of catastrophic failures (i.e., inoperative memory) by ensuring that an uncorrectable error condition is signalled in such instances. That is, by selecting a particular group of outputs from the encoder, this causes the data signals written into memory containing all ONES or all ZEROS not to have check bits containing all ONES or all ZEROS notwithstanding same being inverted or complemented when subsequently read from memory.

The preferred embodiment also has error locator circuits. These circuits connect to receive syndrome signals which indicate the presence of single bit and multiple bit errors formed by decoder circuits which connect to the output circuits of a memory system. The error locator circuits comprise a small number of decoder circuits which connect to a plurality of correction circuits and parity circuits. In response to the syndrome signals, the decoder circuits generate signals for locating any data bit signal in error and concurrently provide for correct parity for the read out data.

A minimum number of standard decoder circuits are utilized to locate single bit errors within a parity check matrix constructed in accordance with the constraints discussed above. In the preferred embodiment, a 3 to 8 decoder circuit is employed. This circuit may take the form of the circuits discussed at pages 274-275 of the text "TIL Data Book for Design Engineers - First Edition" dated 1973.

The syndrome signals are divided into first and second groups. The first group is coded to specify which one of the decoder circuits is to be enabled in response to a single bit or double bit error condition. The second group of signals is coded to designate one of a plurality of outputs indicative of which one of a smaller number of data bits is to be corrected. The first and second groups are applied to a set of three enable inputs and three binary select inputs respectively of each decoder circuit.

A predetermined number of output terminals of each decoder circuit representative of valid single bit errors to be corrected are applied as inputs to a number of data correction circuits and to circuits for providing correct parity signals for the data signals associated therewith. Since the remaining output terminals of the decoder circuits designate noncorrectable conditions (e.g.

multiple error conditions), they are not used.

It will be appreciated that the error locator circuits as described reduce the overall complexity of the memory system.

This results in decreased cost and increased reliability.

Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a system which incorporates the principles of the present invention, Figure 2 illustrates in block diagram form one of the memory subsystems of the main memory system of Figure 1, Figures 3a to 3c illustrate in greater detail portions of Figure 2, Figures 4a to 4f are matrix diagrams useful in explaining the system, and Figure 5 is a memory timing diagram used in explaining the operation of the present system.

Figure 1 illustrates in block diagram form a data processing system which incorporates the teachings of the present invention. It is seen that the system includes a main memory which comprises a plurality of memory subsystems 10-1 through 10-n, a disk controller 12, a communication controller 14, a multidevice controller 16 and central processor 18 all of which connect to a common bus 20.

The bus arrangement enables any two units to communicate with each other at a given time interval over a common signal path provided by bus 20. Briefly, any unit wishing to communicate, requests a bus cycle. When the cycle is granted to the particular requesting unit, it is accorded the role of "master" amd can address any other unit in the system as a slave unit. In those instances in which a response is required (i.e., read operations), the requesting unit signals the slave unit that a response (i.e., acknowledge) is required and identifies itself to the slave unit. The master unit applies the information to the bus and the slave unit (i.e., memory) sends an acknowledge signal and initiates a memory cycle of operation. At the time of acknowledgement, the master unit releases itself from the bus.

The bus 20 includes 24 address lines, 18 data lines, 6 control lines and 5 integrity lines. Certain ones of these lines will be discussed in greater detail in connection with Figure 2. However, for detailed information regarding the operation of the system of Figure 1 and bus 20, reference may be made to the U.S. patent 3,997,896.

Referring now to Figure 2, it is seen that each memory subsystem in accordance with the present invention includes a MOS memory 10-40 which for the purposes of the present invention can be considered conventional in design. For example, the memory 10-40 can be constructed with the memory circuits disclosed in U.S. Patent 3,786,437.

The memory subsystem 10-1 further includes a plurality of input flip-flops 10-10 through 10-34, a plurality of selector circuits 10-20 through 10-26, an EDAC encoder circuit 10-30, an EDAC decoder circuit 10-50 and error correction, inverter and parity circuits. The plurality of input flipflops of blocks 10-10 through 10-34 are connected to receive corresponding ones of the signals from bus 20. That is, flip-flops 1 through 9 of block 10-10 receive signals BSDT00-BSDT07, BSDTOA of a first or left hand byte which correspond to data bits 0-7 and A of the bus 20. Flip-flop 10 of block 10-12 receives a parity signal BSDP00 which contains odd parity for bits 0-7 and A.

Flip-flop 11 of block 10-14 receives a parity signal BSDP01 which contains odd parity for data bits 8-15, B of a second or right hand byte.

The flip-flops 12-20 of block 10-16 receive the data bits 8-15, B of the second byte from bus 20. Further, flip-flops 21 and 22 receive byte and write control signals BSBYTE and BSWRIT during a write operation. The byte signal BSBYTE indicates whether the transfer is a byte or word transfer. When a binary ONE, it indicates that the current transfer is a byte transfer. The signal BSWRIT indicates the direction of transfer. When a binary ONE, it indicates that the transfer is from the master unit to the slave unit. The binary ONE outputs of flip-flops-21 and 22 representative of stored states of the byte and write control signals are combined in an AND gate 10-36 to produce a BYTE WRITE signal. When the BYTE WRITE signal is forced to a binary ONE, this signals the memory subsystem that it is to perform a partial write operation as explained herein.

The signals BSAD00 through BSAD23 are memory address signals which are applied to the input address circuits (not shown) of memory 10-40. (Each 24 bit address includes 8 memory module select bits, 15 internal address bits and a byte designator bit and designates a word storage location in memory 10-40.

As seen from Figure 2, it is seen that the output signals of flip-flops 1-20 are applied as one input of corresponding ones of the plurality of one of two data selector circuits 10-20, 10-22, 10-24 and 10-26. The second input to each of the data selector circuits is from the output of the error correction, inverter and parity circuits of block 10-60.

The signals CRD0-CRD7, CRDA, CRD8 CRD15, CRDB, CRP0 and CRP1 are selected from the second input for application to memory 10-40 and EDAC encoder circuit 10-30 during the read portion of a partial write cycle as explained herein.

The output signals WD0-WD7, WDA selected from either flip-flops 1-9 or inverter circuits of block 10-60 by data selector circuit 10-20 are applied to the EDAC encoder circuit 10-30 and to the write circuits (not shown) of memory 10-40 as shown. In accordance with the embodiment the parity signals WBP0 and WBP1, selected from either flip-flops 10 and 11 or the circuits of block 10-60, are applied as inputs to EDAC encoder 10-30. Further, the byte signals WD8-WD15, WDB from either flip-flops 12-20 or circuits 10-60 are applied as inputs to EDAC encoder 10-30 and memory 10-40.

As explained herein, the EDAC encoder 10-30 generates from the byte data signals WD0-WD15, WDA, WDB and parity signals WBP0, WBP1, check code bit signals WC0-WC5. The check code signals together with the byte data signals associated therewith are stored in memory 10-40. It will be appreciated that the data and check bit signals RD0-RD15, RDA, RDB, RC0 RC5, when read out from MOS memory 10-40 into a data out register (not shown), are inverted or complemented. As seen from Figure 2, the inverted bit signals are applied to EDAC decoder 10-50 and the circuits 10-60.

The EDAC decoder 10-50 produces six pairs of complementary syndrome bit signals S00, S0E through S50, S5E in addition to two error indicator signals YELL and REDD. The signal YELL when a binary ONE indicates the detection of a single error and that correction of the error was made. The signal REDD indicates the detection of a double bit error, a bus parity error or a byte write error as explained herein.

The EDAC decoder circuit 10-50 applies the pairs of syndrome signals and pairs of check bit and data bit signals RC0, RC1, and RDX and RDY to the circuits 10-60. As explained herein, the circuits 10-60 provide corrected signals CRD0-CRD7, CRDA, CRD8-CRD15, CRDB to bus 20 and to data selector circuits 10-20 and 10-26 as mentioned previously. Also, the circuits 10-60 produce the parity signals CBP0 and CBP1 which are also applied to bus 20 and data selector circuits 10-22 and 10-24.

The data selector circuits discussed above can for the purpose of the present invention be considered conventional in design. The EDAC encoder circuit 10-30, the EDAC decoder circuit 10-50, and the circuits 10-60 are shown in greater detail in Figures 3a through 3c respectively.

Referring first to Figure 3a, it is seen that the EDAC encoder circuit 10-30 comprises a plurality of exclusive OR circuits 10-300 through 10-314 and a NAND gate 10-316 connected as shown. The six exclusive OR circuits 10-304 through 10-314 combine different ones of the data signals and parity signals to generate the check code signals WC0-WC5. The exclusive OR circuit 10-300 sums the expansion data bits while the circuit 10-302 sums the parity byte write error signal and data bit 12.

The combinations of signals to be summed are selected in accordance with the matrix of Figure 4a. The matrix illustrates the generation of each of the check code bit signals WC0 through WC5. It will be noted that the matrix includes columns representing states of the data bits 0-7, A and 8-15, B.

Data bits A and B are additional bit positions to be used for expansion. A column labeled PDE is used to represent the occurrence of a partial write double error condition which is signaled by the state of signal REDD as explained herein. The column labeled BPS represents the sum of the bus parity bit signals WBP0 and WBP1.

In each instance, a check code bit is generated by the exclusive OR or all of the columns which contain binary ONES (odd and even). For examPle, check code bit WC0= 10 (9 3 12 03 13 3 14 3 15 3 B Q3 BPS where BPS = WBP0 0 WBP1.

To provide the summing operation indicated for generating each check code bit, each of the circuits 10-304 through 10-314 employs a parity generator/checker circuit which can be considered conventional in design. For example, such circuits may be constructed utilizing a 9 bit parity generator/ checker circuit designated 82S62 manufactured by Signetics Corporation. The even output terminal designated E and odd output terminal are in turn applied as inputs to memory 10-40.

Normally, the inputs to each of the exclusive OR circuits are binary ZEROS which corresponds to ZERO volts. When the inputs are switched on or forced to a binary ONE, they assume a positive voltage value. By contrast, the signal BWDE from NAND gate 10-316 is normally a binary ONE (positive voltage value). The reason is that both signals BYTE WRITE and REDD are normally binary ZEROS (i.e., no error and not a partial write operation).

It will be noted that the matrix of Figure 4a is a simplified version of the matrix of Figure 4b. The matrix of Figure 4b represents a modified version of the so-called H matrix for generating the check code bits for the two byte, 18 bit, data word. The basic matrix is expanded to include a PDE column for designating a partial write double error condition and a BPE column for designating a bus parity error.

It will also be noted that the occurrence of either a bus parity error or a partial write double error results in causing the decoder circuit 10-50 to generate syndrome bits having an even number of binary ONES as explained herein. This results from including an even number of binary ONES in the PDE and PBS columns which relate to an even number of check code bits.

The matrix of Figure 4b has been simplified so as to reduce the number of circuits required for generating the check code bits.

That is, the rows CO and C1 in the basic H matrix have been modified so that they require fewer number of binary ONES.

It is seen that in Figure 4b, CO = 0 Q 1 0 2 ....... 03 7 t3 8 e 9 0 A O BPE.

Substituting into the previous expression, the appropriate value for BPE (i.e., 0 Q3 1 m ... 15 O B O P1), CO = 10 0 11 PO j) 15 0 B O PO O~ P1. B~y having BPS = PO CO P1; C0 = 10 Q 11 -- 15 03 B O BPS. Similarly, it can be shown that C1 = 0 0 1 0 2 --... 0 6 0 BPS.

By appropriate selection of encoder signals, certain check code patterns are not produced for the all ZEROS and all ONES data signals. As seen from Figure 4d, that all ZERO and all ONES data signals produce check code bits which do not have all ONES or all ZEROS. This ensures that when there is a catastrophic memory failure rendering the memory inoperative that the check bit signals enable the detection of the failure.

That is, such failures could give rise to an all ZEROS or all ONES pattern of data and check bit signals. Therefore, the failure could go undetected.

The decoder circuit 10-50 is shown in detail in Figure 3b. The circuit 10-50 is constructed in accordance with the parity check matrix of Figure 4c. It should be noted that this matrix does not include PDE or PBE columns. The reason is that the errors designated by these columns have been incorporated into the generation of check code bits by encoder circuit 10-30 and produce syndrome bits which include an even number of binary ONES upon the occurrence of such errors as mentioned previously.

Referring to Figure 3b, it is seen that the decoder circuit 10-50 includes a plurality of exclusive OR circuits 10-500 through 10-520 arranged as shown. Similar to encoder circuit 10-30, the summing of the different binary ONE columns of the matrix of Figure 4c required for the generation of syndrome bits SO through S5 is also accomplished by means of parity generator/checker circuits.

As indicated by Figure 4c, S0 and S1 require summation of 12 column signals, and S3, S4 and S5 require summation of 11 column signals. Certain data bits (i.e., RDO, RD6 through RD11, RD12) are summed by exclusive OR circuits 10-500 through 10508.

Since syndrome bits SO and S1 are produced from an even number of column signals and syndrome bits S2-S5 are produced from an odd number of column signals, both the even and odd output terminals of circuits 10-510 through 10-520 are utilized as explained herein. As mentioned previously, the signals read out of memory 10-40 are complemented. Accordingly, the input signals to each of the exclusive OR circuits are normally in a binary ONE state (i.e., positive voltage level). This means that the output signals RDV, RDW, RDY and RDZ are also in a binary ZERO state. Also, the even output terminal, designated E of each of the circuits 10-510 and 10-512 are normally binary ONES while the same terminal of each of the circuits 10-514, 10-516, 10-518 and 10-520 are normally binary ZEROS.

The odd output terminals, designated 0, of each of the circuits 10-510 through 10-520 are in a state which is complementary to the even output terminal associated therewith.

Figure 3c illustrates the circuits of block 10-60 which locate and correct single bit errors in addition to producing byte parity signals and error signals. As seen from the Figure, the block 10-60 includes a plurality of error location circuits 10-62, a plurality of correction cicuit 10-64, a parity circuit 10-66 and a plurality of error generation circuits 10-68 arranged as shown.

The circuits 10-62 designate the particular bit which requires correction in the case of a single bit error. The circuits 10-62 include a plurality of decoder circuits 10-620 through 10-628 each of which receive different combinations of syndrome bit signals. The decoder circuits may be considered conventional in design. For example, they may employ circuits such as an SN74S138 manufactured by Texas Instrument Inc. both corrects and inverts the state of the data bit signal applied as a second input thereto. More specifically, normally the signals applied to each exclusive OR circuit is a binary ONE placing the output terminal of each circuit at a binary ZERO. When no correction is designated, the decoder signal (e.g., signal ED4) remains a binary ONE.

Therefore, the signal present at the output terminal of the exclusive OR circuit is the complement or inverse of the input data signal (e.g., signal CRD4 = RD44. When correction is required, the decoder signal is forced to a binary ZERO state. Therefore, the signal present at the output terminal of the exclusive OR circuit is the same as the input data signal (e.g., signal CRD4 = RD4).

As seen from Figure 3c, the parity circuit 10-66 includes exclusive OR circuits 10-660 through 10-666 and a pair of AND gates 10-668 and 10-669 arranged as shown. Parity bit CBPO represents odd parity for bits 0-7 and A while parity bit CBP1 represents odd parity for bits 8-15 and B.

The above can be seen from Figures 4a and 4b. CO (encoder) = 10 0 11 10 0@ 12 Q3120+ Q3120+ 13 t3 14 Q315B Q315B B Q BPS where BPS = 0 01 032 037(3At38039 7 A A 0 0 8 8 0 0 9 9 ........ 015 0031563 015 0031563 B. Substituting the value for BPS into the expression for CO results in the following C0 = o 0102.... 0 AO 8 0 9. By applying signal RDX to exclusive OR circuit 10-660, this effectively cancels out bits 8 and 9 (i.e., RDX = RD8 e RD9). Thus, signal CBP0 = 0 Q 101 101 2 .... 7 (3 A and represents odd parity for bits 0-7 and A. The same is true for C1.

In Figure 3c, normally RCO is a binary ONE and signal RBPO is also a binary ONE.

When data bit signals RD8 and RD9 are equal, RDX is a binary ZERO. Signal RBPO assumes the same state as signal RCO.

When signals RD8 and RD9 are unequal, RDX is a binary ONE. Signal RBPO is the complement of the state of signal RCO.

In the case of no correction, signal EBPO is normally a binary ONE which means that signals ECO, ED8 and ED9 are normally binary ONES. Therefore, signal CBPO corresponds to the complement of signal RBPO. In the case of a correction when signal EBPO is forced to a binary ZERO, signal CBPO assumes the same state as signal RBPO. The circuits 10-662 through 10-666 operate in a similar fashion to produce signal CBP1.

The last group of circuits in Figure 3c generates error signals REDD and YELL.

The circuits include a NAND gate 10-680, and AND gate 10-682 and an exclusive OR circuit 10-684 arranged as shown. The signal YELL signals the system of Figure 1 when the memory subsystem 10-1 detected a single bit error in a data word which it corrected. The signal REDD signals the system when the memory subsystem 10-1 detected an uncorrectable error which includes a double bit error, a bus parity error or a partial write error.

When there is no error, syndrome signals S00 through S5E are normally all binary ONES. This causes signal RE to be a binary ZERO which causes signal REDD to be a binary ZERO. The circuit 10-684 in this case forces its odd output terminal to a binary ZERO and its even output terminal to a binary ONE.

In the case of a correctable error where there is an odd number of syndrome bits, circuit 10-684 forces its odd terminal to a binary ONE and its even terminal to a binary ZERO. Hence, signal REDD remains a binary ZERO. Thus, the state of signal RE does not matter in this case.

When there is uncorrectable error where there is an even number of syndrome bits, two or more of the syndrome signals SOO S5E are binary ZEROS. This forces signal RE to a binary ONE. The circuit 10-684 forces its even output terminal to a binary ONE and its odd output terminal to a binary ZERO. This causes AND gate 10-682 to force signal REDD to a binary one.

Description of operation With reference to Figure 1-3c and Figures 4a-4e and 5, the operation of the apparatus of the preferred embodiment will now be described. Referring first to Figure 5, it is seen that the bus cycle is 300 nanoseconds in duration. Data is available from a device for an interval of 60 nanoseconds starting at 100 nanoseconds from the start of the cycle as shown in Figure 5.

When the memory subsystem 10-1 is addressed and it is not busy, a memory cycle of operation is begun. At this time, the bus has completed 150 nanoseconds of its cycle.

After 30 nanoseconds from the start of the memory cycle, valid memory address signals BSADOO-BSAD23 appear at the address circuits of memory 10-40. During a write cycle, the data signals are available at encoder circuit 10-30, 50 nanoseconds from the start of the memory cycle. At 90 nanoseconds, valid data with check code bits are available for writing into memory 10-40.

As seen from Figure 5, data signals appear at the output of memory 10-40, 400 nanoseconds from the start of the memory cycle. After an interval of 100 nanoseconds, the corrected data is applied to the data selector circuits and bus 20. During a write cycle of operation, data is written into memory 10-40 within 470 nanoseconds and the memory subsystem 10-1 is again available after 620 nanoseconds.

In the case of a byte write operation, the new data bit signals together with check bits are present at the input circuits of memory 10-40, 570 nanoseconds from the start of the memory cycle. A write cycle is begun, at 570 nanoseconds and the new data will have been written into memory 10-40 by 970 nanoseconds from the start of a memory cycle. The memory is available for operation, 1360 nanoseconds from the start of the cycle. The additional delay ensures proper operation of the MOS memory.

It should be noted that if it was necessary to check the parity of the data signals applied to the memory subsystem 10-1, it would require increasing the bus cycle by 50 nanoseconds. The reason is that the memory subsystem would have to make the check and acknowledge this via bus 20. The increase in the bus cycle is illustrated by dotted lines in Figure 5.

An example illustrating the operation of memory subsystem 10-1 in accordance with the present invention will now be discussed with reference to Figures 4d and 4e. It is assumed that one of the devices of Figure 1 applies words A, B, C and D in succession to memory subsystem 10-1 for writing into four successive memory locations during four successive bus cycles. In the first case, the words A through D are shown with no errors.

In accordance with the matrix of Figure 4a, the encoder circuit 10-30 of Figure 3a generates values for check code bits CO through C5 by summing the data and parity bits in each word as designated by the binary ONE bits in the matrix of Figure 4a. The values of the check code bits produced by encoder circuit 10-30 are as indicated.

As illustrated by Figure 5, the data and check code bits of each word are written into memory subsystem 10-1 within the time interval indicated. It will be appreciated that from the point of view of memory subsystem operation, there is no recognition of any error present in the stored data until it is read out during a read cycle of operation.

Assuming that a device requests read out of the same four data words, it is seen from Figure 4e that the four words A through D read out from memory 10-40 appear inverted. When they are applied to decoder 10-50, this results in the generation of syndrome bit signal SO through S5 which are all binary ZEROS indicating the presence of no errors (see Figure 4e).

Referring to Figure 3c, it will be noted that when the syndrome bits SO through S5 are all ZEROS, signals SOE and S1E are binary ZEROS while signals S2E through S5E are binary ONES. This causes the output signals ECO through EDB to remain binary ONES which simply results in the complementing of each of the signals RDO through RDB by the exclusive OR circuits of block 10-64. The signals SOO through S5E condition the error generation circuits 10-68 which cause signals REDD and YELL to be binary ZEROS (i.e., signal RE is forced to a binary ZERO while the E terminal of circuit 10-684 is forced to a binary ONE).

It can be seen from the above how the arrangement of the present invention generates the appropriate check code and syndrome signals for several different coded words containing no errors.

Now, it will be assumed that bit 0 of one of the bytes of word A when presented to memory subsystem 10-1 by a device was in error and therefore contained bad parity.

Accordingly, this results in a binary ONE being included in column BPS of Figure 4d.

As seen from Figure 4d, this causes check code bits CO and C1 to be binary ZEROS while check code bits C2-C5 remain binary ONES.

When a device requests for read out of word A during a subsequent read memory cycle of operation, this results in decoder circuit 12-50 forcing syndrome bits SO and S1 to binary ONES. Syndrome bits S2-S5 remain binary ZEROS. This causes decoder circuits 10-510 and 10-512 of Figure 3b to force signals SOE and S1E to binary ONES.

The signals S20 through S50 remain binary ZEROS. Accordingly, the even number of ONES in the syndrome bits cause circuit 10-684 of Figure 3c to force its even output terminal to a binary ONE and circuit 10-680 to force signal RE to a binary ONE which results in AND gate 10-682 forcing signal REDD to a binary ONE. This signals an uncorrectable error condition to the system.

It will be appreciated that where there is a single bit error condition, this causes one of the columns of syndrome bits in Figure 4f to contain an odd number of binary ONES.

For example, it is assumed that when word A is read out from memory subsystem 10-1, it contains an error in bit 0. The bit values appear complemented when read out and hence these values are designated by fr in Figure 4f.

The decoder circuit 10-50 forces syndrome bits SO, S3 and S4 to binary ONES when bit 0 is a binary ZERO. Syndrome bits S1, S2 and S5 remain binary ZEROS. As seen from Figure 4f, word A without errors cause all of the syndrome bits to be binary ZEROS.

More specifically, with reference to Figure 3b, signal SOE is forced to a binary ONE and signals S30 and S40 are forced to binary ONES. Signal S10 remains a binary ONE while signals S20 and S50 remain binary ZEROS. This results in a code of 001 being applied to the enable input terminals of each decoder circuit and a code of 011 being applied to the select input terminals of each decoder circuit. This enables the de coder circuit 10-620 and causes it to force signal EDO to a binary ZERO. This in turn causes the exclusive OR circuit 10-640 to force signal CRDO to a binary ZERO. The odd number of binary ONES causes the circuit 10-684 to force signal YELL to a binary ONE indicating the occurrence of a corrected single error condition.

It will be appreciated that the decoder circuits 10-620 and 10-626 apply signals ECO, EC1, ED7, EDA, ED8 and ED9 to parity circuit 10-66. Since there are no errors associated with any of these bits, both AND gates 10-668 and 10-669 force their outputs to binary ONES. The pairs of signals RCO, RDX and RC1, RDW cause exclusive OR circuits 10-660 and 10-662 to force their outputs to binary ZEROS. The result is that circuits 10-664 and 10-666 force signals CBPO and CBP1 respectively to binary ONES.

Where there is a single bit error associated with any one of the signals RCO, RDX, RC1 or RDW, this causes corresponding ones of the decoder circuits 10-620 through 10-626 to force an appropriate one of signals ECO, ED8, ED9, EC1, ED7 or EDA to a binary ZERO. As mentioned above in signal RBPO assumes the state of signal RCO when signal RDX is a binary ZERO. When RDX is a binary ONE, signal RBPO is the complement of signal RCO.

When there is a correction, signals EBPO and EP1 are forced to binary ZEROS.

Signals CBPO and CBP1 assume the states of signals RBPO and RBP1 respectively.

By having the data error locator circuits 10-62 provide signals from which the correct parity bits can be produced, reduces substantially the amount of circuits normally required for generating parity signals.

It will be noted that the error locator circuits in response to multiple error conditions produced by double data bit error, a bus parity error or byte write error are not enabled by the syndrome bits SO through S5.

That is, the syndrome bits SO through S5 in such instances contain an even number of binary ONES in those column(s) of the matrix associated with the error condition(s). The combinations of syndrome signals applied to the decoder circuits 10-620 through 10-628 produce signals only at the unused output terminals of these circuits.

Hence, no correction takes place.

The occurrence of a partial write error also will be detected as an uncorrectable error condition. For example, it is assumed that during the read portion of a byte write operation (see Figure 5), the error generation circuits 10-68 detect the presence of a double error in word A. This results in signal REDD being forced to a binary ONE. During the write cycle of the byte write operation (see Figure 5), the encoder circuit 10-30 causes check code bits C4 and C5 to be forced to binary ZEROS and the new and odd data bytes selected by circuits 10-20 and 10-26 are written into memory 10-40.

When word A is read out during a subsequent read cycle of operation, the decoder circuit 10-50 forces syndrome bits S4 and S5 to binary ONES. The error generation circuits 10-68 are conditioned by the even number of binary ONES to force its even output terminal to a binary ONE.

This results in signal REDD in being forced to a binary ONE signalling the uncorrectable error condition to the system of Figure 1.

It will be appreciated that a double error in a word also causes the circuits 10-68 to force signal REDD to a binary ONE indicating an uncorrectable error condition.

For example, it is assumed that bits 0 and 1 of word A are both binary ZEROS when read out during a read cycle of operation.

This causes the decoder circuit 10-50 to force syndrome bits S4 and S5 to binary ONES. This in turn causes the circuit 10-684 to force its even output terminal to a binary ONE which results in signal REDD being forced to a binary ONE.

From the foregoing, it is seen how the arrangement of the present invention is able to detect and signal the presence of a variety of uncorrectable error conditions to a system while enabling the system to operate at maximum speed and efficiency. Moreover, the present invention provides the foregoing without having to increase the number of check code bits required to be stored. Also, the arrangement of the present invention minimizes the amount of error detector and correction circuits thereby resulting in increased system reliability.

It will be appreciated by those skilled in the art that many changes may be made to the preferred embodiment of the present invention. For example, this could include changes in the number of bits included in a word, the type of bus system and type of circuits.

WHAT WE CLAIM IS: 1. A method of detecting errors in groups of signals received from a bus network for storage in a memory pertaining to which is a data processor subsystem containing encoder and decoder circuits respectively at the input and output of the memory, each of said groups of signals including a plurality of data bit signals and at least one parity bit signal for indicating the validity of said plurality of data bit signals, said method comprising applying to said encoder circuits during a memory cycle of operation a group of signals received from said bus for writing in said memory, generating a group of check code bit signals by said encoder circuits from

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (42)

**WARNING** start of CLMS field may overlap end of DESC **. coder circuit 10-620 and causes it to force signal EDO to a binary ZERO. This in turn causes the exclusive OR circuit 10-640 to force signal CRDO to a binary ZERO. The odd number of binary ONES causes the circuit 10-684 to force signal YELL to a binary ONE indicating the occurrence of a corrected single error condition. It will be appreciated that the decoder circuits 10-620 and 10-626 apply signals ECO, EC1, ED7, EDA, ED8 and ED9 to parity circuit 10-66. Since there are no errors associated with any of these bits, both AND gates 10-668 and 10-669 force their outputs to binary ONES. The pairs of signals RCO, RDX and RC1, RDW cause exclusive OR circuits 10-660 and 10-662 to force their outputs to binary ZEROS. The result is that circuits 10-664 and 10-666 force signals CBPO and CBP1 respectively to binary ONES. Where there is a single bit error associated with any one of the signals RCO, RDX, RC1 or RDW, this causes corresponding ones of the decoder circuits 10-620 through 10-626 to force an appropriate one of signals ECO, ED8, ED9, EC1, ED7 or EDA to a binary ZERO. As mentioned above in signal RBPO assumes the state of signal RCO when signal RDX is a binary ZERO. When RDX is a binary ONE, signal RBPO is the complement of signal RCO. When there is a correction, signals EBPO and EP1 are forced to binary ZEROS. Signals CBPO and CBP1 assume the states of signals RBPO and RBP1 respectively. By having the data error locator circuits 10-62 provide signals from which the correct parity bits can be produced, reduces substantially the amount of circuits normally required for generating parity signals. It will be noted that the error locator circuits in response to multiple error conditions produced by double data bit error, a bus parity error or byte write error are not enabled by the syndrome bits SO through S5. That is, the syndrome bits SO through S5 in such instances contain an even number of binary ONES in those column(s) of the matrix associated with the error condition(s). The combinations of syndrome signals applied to the decoder circuits 10-620 through 10-628 produce signals only at the unused output terminals of these circuits. Hence, no correction takes place. The occurrence of a partial write error also will be detected as an uncorrectable error condition. For example, it is assumed that during the read portion of a byte write operation (see Figure 5), the error generation circuits 10-68 detect the presence of a double error in word A. This results in signal REDD being forced to a binary ONE. During the write cycle of the byte write operation (see Figure 5), the encoder circuit 10-30 causes check code bits C4 and C5 to be forced to binary ZEROS and the new and odd data bytes selected by circuits 10-20 and 10-26 are written into memory 10-40. When word A is read out during a subsequent read cycle of operation, the decoder circuit 10-50 forces syndrome bits S4 and S5 to binary ONES. The error generation circuits 10-68 are conditioned by the even number of binary ONES to force its even output terminal to a binary ONE. This results in signal REDD in being forced to a binary ONE signalling the uncorrectable error condition to the system of Figure 1. It will be appreciated that a double error in a word also causes the circuits 10-68 to force signal REDD to a binary ONE indicating an uncorrectable error condition. For example, it is assumed that bits 0 and 1 of word A are both binary ZEROS when read out during a read cycle of operation. This causes the decoder circuit 10-50 to force syndrome bits S4 and S5 to binary ONES. This in turn causes the circuit 10-684 to force its even output terminal to a binary ONE which results in signal REDD being forced to a binary ONE. From the foregoing, it is seen how the arrangement of the present invention is able to detect and signal the presence of a variety of uncorrectable error conditions to a system while enabling the system to operate at maximum speed and efficiency. Moreover, the present invention provides the foregoing without having to increase the number of check code bits required to be stored. Also, the arrangement of the present invention minimizes the amount of error detector and correction circuits thereby resulting in increased system reliability. It will be appreciated by those skilled in the art that many changes may be made to the preferred embodiment of the present invention. For example, this could include changes in the number of bits included in a word, the type of bus system and type of circuits. WHAT WE CLAIM IS:

1. A method of detecting errors in groups of signals received from a bus network for storage in a memory pertaining to which is a data processor subsystem containing encoder and decoder circuits respectively at the input and output of the memory, each of said groups of signals including a plurality of data bit signals and at least one parity bit signal for indicating the validity of said plurality of data bit signals, said method comprising applying to said encoder circuits during a memory cycle of operation a group of signals received from said bus for writing in said memory, generating a group of check code bit signals by said encoder circuits from

said plurality of data bit signals and said one parity bit signal of said group and forcing a number of said check code bit signals to a predetermined state when said one parity bit signal indicates that said data bit signals received from said bus are in error, storing in said memory only said data bit signals and said check bit signals of said group during said memory cycle of operation, reading said stored data and check code bit signals form said memory, generating a plurality of syndrome signals by said decoder circuits from the said signals read from the memory and forcing said plurality of syndrome signals to have a first predetermined characteristic for signalling when said group of data bit signals had incorrect parity when written into said memory enabling detection of incorrect signals without decreasing the operating speed of said data handling devices.

2. A method according to Claim 1 wherein said first predetermined characteristic is generated by said decoder circuits forcing said plurality of syndrome signals to contain an even number of binary ONES indicative of an uncorrectable error condition.

3. A method according to Claim 2 wherein said decoder circuits produce said even number of binary ONES by forcing an even number of syndrome signals to binary ONES.

4. A method according to any preceding claim wherein the plurality of syndrome signals has a second predetermined characteristic for signalling when said group of data bit signals contain a single bit error condition.

5. A method according to Claim 4 wherein said second predetermined characteristic is generated by said decoder circuits forcing said plurality of syndrome signals to contain an odd number of binary ONES indicative of a single error condition.

6. A method according to Claim 4 or Claim 5 wherein the data which is read from the memory and contains a single error condition and said syndrome signals are applied to an error correcting circuit from whence corrected data is obtained.

7. A method according to Claim 5 when appendant to Claim 3, further comprising applying signals representative of the states of said plurality of syndrome signals to error indicator circuits, generating a first output signal by said error indicator circuits indicating the presence of said uncorrectable error condition upon detecting said even number of binary ONES, and generating a second output signal by said error indicator circuits indicating the presence of said single error condition upon detecting said odd number of binary ONES.

8. A method according to Claim 7 further comprising applying a signal indicating when said memory is performing a partial write operation and said first output signal to said encoder circuits, forcing said number of said check code bit signals to said predetermined state by said encoder circuits when said first output signal is generated by said error indicator means during a read portion of said partial write operation, and writing said check code bit signals and said data bit signals including a number of new data bit signals received from said bus and a portion of the data bit signals read out during said read portion into said memory during a write portion of said partial write operation enabling detection of uncorrectable error conditions during a subsequent memory cycle of operation.

9 A method according to Claim 8 wherein said partial write operation involves replacement of one of a number of bytes of a word read out from one of said plurality of addressable locations of said memory with a byte applied to said bus network, each said byte including a corresponding parity bit, said method comprising applying a byte write signal from said bus network to said memory to indicate to the latter when it is to perform said partial write operation, generating an output error signal by said error indicator circuits in response to a plurality of syndrome signals from said decoder indicating the presence of an uncorrectable error in one of said words read out from one of said memory locations during a read portion of said partial write operation, applying said output error signal and said byte write signal to said encoder, generating by said encoder a group of check code bits derived from a first byte applied to said bus and a second byte read out from said one of said memory locations during said read portion, forcing by said encoder a number of said check code bit signals to a predetermined state in response to said output error signal, and writing said check code bit signals and said first and second bytes into one of said memory locations during a write portion of said partial write operation for enabling detection of uncorrectable error conditions during a subsequent memory cycle of operation by said decoder forcing said syndrome signals to have a first predetermined characteristic.

10. A memory subsystem for detecting errors in recorded data provided on a bus of an associated data processing system comprising an addressable memory for storing groups of signals, input means coupled to said bus for receiving said groups of signals occurring thereon, each said group of signals including a plurality of unchecked data bit signals and at least one parity bit signal for indicating the validity of said data bit signals, an encoder, coupled to said input means and to said memory, which generates a group of check code bits derived from a group of said unchecked data bit signals and said one parity bit signal, said encoder forcing a number of said check code bit signals to predetermined states when said one parity bit signal designates that said unchecked data bit signals are in error, transfer means connected to said encoder and to said input means which applies said unchecked data bit signals and group of check code bit signals to said memory for said storage during a memory cycle of operation, and a decoder coupled to said memory, which generates a plurality of syndrome signals characterised for locating an error in said data bit signals, the location of said error being established by said unchecked data bit signals and said check code bit signals, both sets of signals being read out from said memory during a subsequent cycle of operation.

11. Apparatus according to Claim 10 wherein said plurality of syndrome signals have a first predetermined characteristic for signalling when said group of unchecked data bit signals from any one of said data handling devices have incorrect parity when written into said memory enabling the storage of said signals from said bus to proceed without decreasing the operating speed of said system.

12. Apparatus according to Claim 10 or Claim 11 wherein each said group of signals include a plurality of bytes and a plurality of parity bit signals, each said parity bit signal being coded to specify odd parity for a different one of said plurality of bytes.

13. Apparatus according to Claim 11 or Claim 12 wherein said first predetermined characteristic corresponds to said plurality of syndrome signals containing an even number of binary ONES indicative of an uncorrectable error condition.

14. Apparatus according to any of Claims 11 to 13 further comprising an error indicator connected to said decoder for receiving selected states of said plurality of syndrome signals, said indicator detecting when said plurality of syndrome signals contains an even number and odd number of binary ONES whereby it generates a first output signal indicating the presence of said uncorrectable error condition and a second output signal indicating the presence of a single bit error condition.

15. Apparatus according to Claim 14 wherein said decoder includes a plurality of parity generator circuits corresponding in number to the number of said plurality of syndrome signals, each of said parity generator circuits having inputs connected to receive a different combination of said data bit signals and check code signals, each said parity generator circuit including a pair of output terminals for providing complementary states of a predetermined one of said plurality of syndrome signals, and wherein said error indicator is selectively connected to one of said pair of output terminals of each of said parity generator circuits for receiving signals corresponding to the normal states of said plurality of syndrome signals.

16. Apparatus according to Claim 15 wherein said number of said parity generator circuits is six.

17. Apparatus according to any of Claims 14 to 16 wherein the error indicator includes logic gating means having a plurality of input terminals and an output terminal, said plurality of input terminals being connected to the decoder to receive the syndrome signals therefrom, a parity generator circuit having a plurality of input terminals and an even and odd output terminal, said plurality of input terminals also being connected to the decoder to receive the said syndrome signals, and output gating means connected to said output terminal of said logic gating means and to said even output terminal of the last said parity generator circuit, said output gating means being conditioned by said logic gating means in response to an error condition to generate said first output signal when said parity circuit forces said even output terminal to a binary ONE for indicating that said syndrome signals contain an even number of binary ONES, and said error indicator generating said second output signal when said parity circuit forces its odd output terminal to a binary ONE indicating that said syndrome signals contain an odd number of binary ONES.

18. Apparatus according to any of Claims 10 to 17 wherein said encoder includes a plurality of parity generator circuits corresponding in number to the number of check code bits of said group, each of said parity generator circuits being connected to receive a different combination of said unchecked data bit signals, each said parity generator circuit including a pair of output terminals for indicating complementary states of a predetermined one of said plurality of check code bits, a predetermined one of the pair of output terminals of each said parity circuit being connected to the memory for applying a predetermined state of the respective check code bit to said memory.

19. Apparatus according to Claim 18 wherein each pair of output terminals of the encoder parity generator circuits include an even output terminal and an odd output terminal, said terminals being connected to the memory such that, in respect of predetermined patterns of data bit signals the generated check code bits do not contain all binary ONES or all binary ZEROS, thereby enabling detection of catastrophic failures in said memory.

20. Apparatus according to Claim 19 wherein said predetermined patterns of said data bit signals include all ZEROS and all ONES.

21. Apparatus according to any of Claims 18 to 20 when appendant to Claim 14 wherein said encoder further includes logic circuit means connected to receive the said first output signal of the error indicator and a signal indicating when said memory is performing a partial write operation, said logic circuit means including means conditioned by said output signal during a read portion of said partial write operation to force said number of said check code bit signals to predetermined states for designating the presence of an uncorrectable error in said data bit signals and check bit signals being written into said memory during a write portion of said partial write operation.

22. Apparatus according to Claim 21 wherein said decoder is conditioned by data bit signals and check code bit signals read out of said memory so as to generate syndrome signals having said first characteristic, where such signals have been inserted in said memory during a write portion of a partial write operation in a preceding cycle of operation.

23. Apparatus according to Claim 22 wherein said group of check code bit signals include an even number of bits and wherein said number of said check code bit signals forced to said predetermined states is an even number.

24. Apparatus according to Claim 23 wherein said even number of bits is six and wherein said even number of said check code bit signals is two.

25. Apparatus according to any of Claims 14 to 24 wherein said error indicator comprises a plurality of decoding circuits each having a number of input terminals and a number of output terminals, said number of input terminals of each decoding circuit being connected to receive a different combination of said group of syndrome signals from said syndrome decoder.

26. Apparatus according to Claim 25 comprising a plurality of data bit correction circuits connected to receive each such group of data bit signals read out from said memory, said plurality corresponding to said number of data bits, each one of said data bit correction circuits being connected to a different one of said plurality of decoding circuits and being connected to receive a different one of said data bits.

27. Apparatus according to Claim 26 wherein the outputs of each decoding circuit include first and second groups of outputs and the decoding circuits are conditioned by said group of syndrome signals to force a predetermined one of said first group of output terminals of one of said decoding circuits to a predetermined state for enabling correction of the check bit by one of said plurality of said correction circuits when said group of syndrome signals designate the presence of a correctable error condition and said decoding circuits are conditioned by said group of syndrome signals to force one of said second group of output terminals of one of said decoding circuits to said predetermined state for inhibiting correction of any of said data bit by said plurality of correction circuits when said group of syndrome signals designate the presence of an uncorrectable error condition.

28. Apparatus according to Claim 27 wherein said group of syndrome signals includes first and second groups of binary signals, said first group of binary signals being coded to designate which one of said decoding circuits is to be enabled for operation and said second group of binary signals being coded to designate which one of said number of output terminals is to be forced to said predetermined state, and said number of input terminals of said decoding circuits includes first and second groups of input terminals, said first group of each decoding circuit being connected to receive said first group of binary signals and said second group of each decoding circuit being connected to receive said second group of binary signals.

29. Apparatus according to Claim 28 wherein said first group of input terminals are enable inputs and said second group of input terminals are select inputs, said first group of input terminals of each decoding circuit being connected to receive a different combination of said first group of syndrome signals and said second group of input terminals of all said decoding circuits being connected to receive the same combination of said second group of syndrome signals.

30. Apparatus according to any of Claims 25 to 29 wherein said first group of output terminals of said decoding circuits includes no greater than one-half the total number of said output terminals.

31. Apparatus according to Claim 30 wherein said first group and second group of input terminals of said decoding circuits correspond to one-half the total number of said input terminals.

32. Apparatus according to Claim 27 or any claim appendant thereto wherein said predetermined state is a binary ZERO state and wherein each of said data bit correction circuits includes an exclusive OR circuit, said exclusive OR circuit being conditioned by said predetermined state from one of said second group of output terminals to complement the state of said data bit signal to correct the correctable error condition.

33. Apparatus according to Claim 32 wherein said correctable error condition corresponds to a single bit error and said uncorrectable error condition includes double bit and check code bit error conditions.

34. Apparatus according to Claim 27 or any claim appendant thereto wherein one of said plurality of decoding circuits forces a predetermined one of said second group of output terminals to said predetermined state for indicating that said derived state of said one parity bit signal is in error.

35. Apparatus according to Claim 27 or any claim appendant thereto further comprising logic circuit means connected to said predetermined one of said second group of output terminals of said decoding circuits and said one check bit signal for producing a signal corresponding to the correct state of said one parity bit derived from said one check bit in parallel with any correction of said data bit signals.

36. Apparatus according to Claim 35 wherein said logic circuit means includes first logic gating means connected to receive said one check code bit signal and predetermined ones of said data bit signals required for deriving the state of said one parity bit signal, second logic gating means connected to predetermined ones of said first group of output terminals which indicate the correctness of said one check code bit signal and predetermined ones of said data bit signals, and output logic gating means connected to said first and second logic gating means, said output logic gating means being conditioned by said first and second logic gating means to generate said signal corresponding to the correct state of said one parity bit.

37. Apparatus according to Claim 36 wherein said first logic gating means and output logic gating means each include an exclusive OR circuit.

38. Apparatus according to Claim 15 or any claim appendant thereto wherein said plurality of syndrome signals includes first and second groups of binary signals, said first group of binary signals being coded to designate which one of said plurality of decoder circuits is to be enabled for operation and said second group of binary signals being coded to designate which one of said number of output terminals is to produce said predetermined signal.

39. Apparatus according to Claim 38 wherein said number of input terminals of each decoding circuit includes a group of enable inputs and a group of select inputs, said enable inputs of each decoder circuit being connected to receive said first group of binary signals and said select inputs of each decoder circuit being connected to receive said second group of binary signals.

40. Apparatus according to Claim 26 or any claim appendant thereto wherein said transfer means comprise a plurality of one of two data selector circuits having a first set of inputs connected to sAid input means for receiving therefrom said unchecked data bit signals, a second set of inputs connected to said data bit correction circuits for receiving therefrom, in a later cycle of operation, corrected data bits corresponding to said unchecked data bits, and a set of outputs connected to the data write circuit of said memory.

41. A method of detecting and correcting errors in groups of signals received from a bus network according to Claim 1 and substantially as described herein.

42. A memory subsystem for detecting errors in recorded data provided on a bus of an associated data processing system substantially as described herein with reference to the accompanying drawings.