CA1106972A - Method and apparatus for storing parity encoded data from a plurality of input/output sources - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an ad-dressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrect-able error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.

Description

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This application is a division of our Canadian patent application Serial no. 285,459 filed August 25, 1977.
This invention relates generally to data processing systems and more particularly to error detection and correction apparatus included with-in the memory of a data processing system.
It is well known to utilize metal oxide semiconductor field effect tranSiStor (MOSFET) memory elements in main memory systems. Since such memories are volatile in nature and require continual restoration of the stored information, error detection and correction apparatus are normally included within such memory systems for ensuring the integrity of the stored information. Generally, main storage systems utilize a modified Hamming code for single error detection/double error detection. Normally, such codes increase significantly the number of memory circuits.
In order to increase memory reliability nothwithstanding attendant increases in error detection and correction circuits, at least one system utilizes codes which improve upon the modified Hamming SEC/DED codes and simplify the memory circuit implementation as well as provide faster and better error detection capability. This arrangement is described in a paper "A Class of Optimal Minimum Odd-Weight-Column SEC/DED Codes" by M. Y. Hsiao which appears in the publication "IBM Journal of Research and Development", July 1970. The construction of such codes is described in terms of a parity check matrix H. The selection of the columns of the H matrix for a given (n, k) code is based upon the following constraints:
1. Every column should have an odd number of one's;

2. The total number of one's in the H matrix should be a minimum; and,

3. The number of one's in each row of the H matrix should be made equal or as close as possible to the average number.
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`6972 Errors are indicated by analyzing the syndromes formed from the data and check code bits. An odd number of syndrome bits indicates a single error while an even number of syndrome bits indicates a double or uncorrectable error.
In the above mentioned arrangement as well as other prior art systems, while reducing the amount of circuits by observing the constraints mentioned above, such systems still require large numbers of multiinput AND
error locator circuits as well as circuits for generating parity bit signals for the data read out of memory. Thus, the disadvantages of such arrange-ments are their higher cost, complexity in implementation and lower reli-ability. That is, if the implementation requires fewer circuits and connec-tions, its chance of failure is decreased. Also, such systems may require construction of special circuits which would also result in higher cost.
In general, operations for decoding or encoding data and check bits in prior art memory systems proceed as follows. Normally, during a read operation, a word is read from a main memory location and the data bits together with check code bits are stored in a data storage register. Byte parity bits are generated from the data bits. The syndromes formed from the data and code check bits are analyzed. If no error is indicated, the byte parity encoded data is transmitted onto the data bus. If a double code error is indicated, a program interrupt signal is generated and the error data are made available for program analysis. In the case where a single error is signalled, the correction circuits correct the data.
In the case of a write operation, the byte encoded parity word is received from the data bus and the check code bits are generated for the SEC/DED code. The received byte parity bits are examined for validity.
When no error is detected, the coded word is stored into a memory location.

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In the event of a double error, the write operation is aborted and the data processing system is notified of the error.
Additionally, such prior art memory systems are required to perform "partial write" operations. The partial write operation occurs when a por-tion of data word (i.e., a byte) stored in memory is read out and altered by new data and thereafter written into memory. Prior art memory systems handle partial write operations similar to that described above. That is, the data to be written into memory is checked. When a double error is indi-cated, the operation is aborted and the data processing system is notified.
The above arrangements have been found to be unsuitable for use in systems where data is transferred along a common data bus at a rapid rate.
In such instances, by the time the parity encoded data word can be checked, the data source applying the data will have relinquished its control of the bus. Accordingly, the arrangement requires that the sending source be con-nected to the bus until the parity encoded data can be checked. This results in reducing the overall throughput of the data processing system.
Also, at least one of the above mentioned prior art systems has employed an arrangement which utilizes address parity bits as data bits and includes such bits in the generation of check code bits. While the arrange-ment is able to signal when an incorrect location is being accessed, the address parity bits provide no indication regarding the integrity of the data being written into memory.
Accordingly, it is a primary object of the present invention to provide an improved method and apparatus for detecting and correcting parity encoded data applied from any one of a plurality of input/output sources for storage in a memory system.
According to one aspect of the present invention there is provided in a data processing system including in a data processing system including a memory subsystem having a memory for storing groups of data signals, each group including a number of data bits and error detection and correction (EDAC) means including an encoder for generating a group of check code bit signals for each of said groups of data signals for storage in said memory together with the group of data signals associated therewith and a syndrome decoder for generating a group of syndrome bit signals in response to each group of data signals and group of check code bits read out from said memory, said group of syndrome signals for detecting correctable and uncorrectable error conditions within said group of data and check code bits signals, said EDAC means further including EDAC correction circuits comprising: a plura-lity of decoder circuit means, each having a number of input terminals and a number of output terminals including first and second groups, said number of input terminals of each decoder circuit being connected to receive a dif-ferent combination of said group of syndrome signals from said syndrome de-coder; a plurality of data bit correction circuit means connected to receive each said group of data signals read out from said memory, said plurality corresponding to said number of data bits, each of said data bit correction circuit means being connected to a different one of said first group of out-put terminals of one of said plurality of decoder circuit means and being connected to receive a different one of said number of data bits; and, said plurality of decoder circuit means being conditioned by said group of syn-drome signals to force a predetermined one of said first group of output terminals of one of said plurality of decoder circuit means to a predeter-mined state for enabling correction of the check bit by one of said plura-lity of said correction circuit means when said group of syndrome signals designate the presence of a correctable error condition and said plurality . , : .
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6~72 of decoder circuit means being conditioned by said group of syndrome signals to force one of said second group of output terminals of one of said plura-lity of decoder circuit means to said predetermined state for inhibiting correction of any of said data bit by said plurality of correction circuit means when said group of syndrome signals designate the presence of an uncor-rectable error condition.
According to another aspect of the invention there is provided a data processing system including a memory subsystem comprising a memory for storing data signals received from a plurality of devices, said data signals including a number of groups of data bits and a corresponding number of parity bits for indicating the validity of said groups of data bits, an en-coder for generating a group of check code bits derived from said data sig-nals for writing into said memory together with said number of data bits and a decoder for generating a plurality of syndrome signals from said number of data bits and check bit signals accessed from said memory for locating errors in said data signals, said memory subsystem further comprising: error loca-tion circuit means connected to said decoder for generating signals designat-ing locations of single bit and double bit errors, said circuit means includ-ing a plurality of decoder circuits, each decoder circuit having a number of input terminals for receiving said syndrome signals and a number of out-put terminals for generating said signals indicating said locations of said single bit and double bit errors; a plurality of data bit correction circuits, each being connected to receive a different one of said number of data bits;
and, conductor means for connecting each of said plurality of data bit cor-rection circuits to a different one of said output terminals of one of said decoder circuits which designates the presence of single bit error in said different one of said number of data bits, said plurality of decoder cir-cuits in response to said syndrome signals designating single and double bit errors being operative to produce a predetermined signal at a connected one of said output terminals to enable said plurality of correction circuits for correction of only single bit errors in said data bits.
According to a further aspect of the invention there is provided a data processing system including a memory subsystem having a memory for storing groups of data signals, each group including a number of data bits and at least one parity bit for indicating the validity of said data bits and error detection and correction (EDAC) means including a encoder for generating a group of check code bits from said number of data bits and said parity bit of each group for storage with said number of data bits of said each group and a decoder for generating pairs of complementary syndrome sig-nals in response to said data bits and said group of check code bits, said pairs of complementary syndrome signals for detecting double bit errors and single bit errors in said number of data bits, said group of check code bits and said parity bit, said memory system further comprising: error loca-tor circuit means connected to said decoder for receiving predetermined ones of said pairs of said complementary syndrome signals, said error locator circuit means including a number of decoder circuits, each decoder circuit having a number of input terminals connected for receiving a different com-bination of said predetermined ones of said pairs of complementary syndrome signals and a number of output terminals for generating predetermined out-put signals indicating the location of single bit errors in said data bits and check code bits and double bit errors; a plurality of data bit correction circuits, each being connected to receive a different one of said number of data bits and being connected to a predetermined one of said output terminals of one of said decoder circuits which designates the presence of a single i72 bit error in said different one of said number of data bits; and, logic circuit means for generating said parity bit, said circuit means being con-nected to receive at least one of said check code bits and predetermined ones of said data bits and said circuit means being connected to a number of said output terminals of predetermined ones of said decoder circuits which generate signals indicate the location of single bit errors in said one of said check code bits and said predetermined ones of said data bits, said plurality of decoder circuits in response to said predetermined ones of said pairs of complementary syndrome signals being operative to force dif-ferent ones of said output terminals to a predetermined state for condition-ing said plurality of data bit correction circuits and said logic circuit means for correction of only single bit errors enabling the correction of said number of data bits and the generation of said parity bit to proceed concurrently.
In preferred embodiment, there are encoder circuits which couple to the input circuits of a memory system and decoder circuits which couple to the output circuits of the memory system. The decoder circuits connect to error correction circuits which transmit to the bus and the encoder circuits are connected to receive from the bus data bit signals and parity bit signals by one of a number of input/output devices. During a write memory cycle of operation, the encoder circuits generate a predetermined number of coded check bits from the unchecked data signals and associated parity bits received from any one of the devices. Thereafter, the data signals and generated check code bits are written into memory. The encoder circuits are operative to force selectively the check code bits to predeter-mined states when the parity bits of the unchecked data indicate that such data is an error.

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During a subsequent read cycle of operation, the decoder circuits are conditioned by the check code bits to generate selectively syndrome bits having a first predetermined characteristic for signalling that the data was in error when it was initially written into memory. In the preferr-ed embodiment of the present invention, the characteristic is that the syndrome bits contain an even number of binary ONES indicative of an uncorrectable error condition. In the case where the input data has correct parity, the decoder circuits generate syndrome bits having the first predetermined characteristic only when a double error occurs as a consequence of a failure or fault within the memory system or its associated circuits. In all other instances, the decoder circuits generate syndrome bits having a second pre-determined characteristic. In the preferred embodiment, the second predeter-mined characteristic corresponds to the syndrome bits having an odd number of binary ONES indicative of a single error condition. In response to such single bit error conditions, the correction circuits correct the condition automatically and produce parity bits from the data and check code bits which are thereafter applied to the bus together with the data bits.
In the case of a "partial write" operation, when the double error condition is detected by the decoder circuits during the read portion of the operation, the error conditions the encoder circuits to force the check code bits to a predetermined state. That is, the check code bits are forced to a predetermined state which condition the decoding circuits during a sub-sequent read cycle to generate syndrome bits having the first predetermined characteristic.
From the above, it is seen that the arrangement is able to auto-matically signal the occurrence of errors related to the correctness of un-checked data written into memory. Since it is essential that such errors not be corrected, they produce uncorrectable error indications. By eliminat-ing the need to provide circuits for checking data before it is written into memory, the present invention reduces the amount of additional circuits. It also eliminates the need to include parity bits in memory.
More importantly, the present invention enables data transfers to take place at a maximum rate in that the invention eliminates the necessity for requiring checking of the parity encoded data words before being written into memory.
Additionally, the arrangement of the present invention facilitates the detection of catastrophic failures ~i.e., inoperative memory) by ensur-ing that an uncorrectable error condition is signalled in such instances.
That is, by selecting a particular group of outputs from the encoder, this causes the data signals written into memory containing all ONES or all ZEROS
not to have check bits containing all ONES or all ZEROS notwithstanding same being inverted or complemented when subsequently read from memory.
In the preferred embodiment, error detection and correction is implemented by means of error locator circuits. These circuits connect to receive syndrome signals which indicate the presence of single bit and mult-iple bit errors formed by decoder circuits which connect to the output cir-cuits of a memory system. The error locator circuits comprise a small num-ber of decoder circuits which connect to a plurality of correction circuits and parity circuits. In response to the syndrome signals, the decoder cir-cuits generate signals for locating any data bit signal in error and concur-rently provide for correct parity for the read out data.
A minimum number of standard decoder circuits are utilized to lo-cate single bit errors within a parity check matrix constructed in accordance with the constraints discussed above. In the preferred embodiment, a 3 to 8 _ g _ decoder circuit is employed. This circuit may take the form of the circuits discussed at pages 274-275 of the text "TTL Data Book for Design Engineers-First Edition" dated 1973.
In accordance with the preferred embodiment, the syndrome signals are divided into first and second groups. The first group is coded to specify which one of the decoder circuits is to be enabled in response to a single bit or double bit error condition. The second group of signals is coded to designate one of a plurality of outputs indicative of which one of a smaller number of data bits is to be corrected. The first and second groups are applied to a set of three enable inputs and three binary select inputs respectively of each decoder circuit.
A predetermined number of output terminals of each decoder circuit representative of valid single bit errors to be corrected are applied as inputS to a number of data correction circuits and to circuits for providing correct parity signals for the data signals associated therewith. Since the remaining output terminals of the decoder circuits designate noncorrect-able conditions (e.g. multiple error conditions), they are not used.
It will be appreciated that the error locator circuits as describ-ed reduce the overall complexity of the memory system. This results in decreased cost and increased reliability.
Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which:-Figure 1 is a block diagram of a system which incorporates the principles of the present invention, Figure 2 illustrates in block diagram form one of the memory sub-systems of the main memory system of Figure 1, Figures 3a to 3c illustrate in greater detail portionC of Figure 2, ~6972 Figures 4a to 4f are matrix diagrams useful in explaining the system, and Figure 5 is a memory timing diagram used in explaining the opera-tion of the present system.
Figure 1 illustrates in block diagram form a data processing system which incorporates the teachings of the present invention. It is seen that the system includes a main memory which comprises a plurality of memory sub-systems 10-1 through 10-n, a disk controller 12, a communication controller 14, a multidevice controller 16 and central processor 18 all of which connect to a common bus 20.
The bus arrangement enables any two units to communicate with each other at a given time interval over a common signal path provided by bus 20.
Briefly, any unit wishing to communicate, requests a bus cycle. When the cycle is granted to the particular requesting unit, it is accorded the role of "master" and can address any other unit in the system as a slave unit.
In those instances in which a response is required (i.e., read operations), the requesting unit signals the slave unit that a response (i.e., acknow-ledge) is required and identifies itself to the slave unit. The master unit applies the information to the bus and the slave unit (i.e., memory) sends an acknowledge signal and initiates a memory cycle of operation. At the time of acknowledgement, the master unit releases itself from the bus.
The bus 20 includes 24 address lines, 18 data lines, 6 control lines and 5 integrity lines. Certain ones of these lines will be discussed in greater detail in connection with Figure 2. However, for detailed infor-mation regarding the operation of the system of Figure 1 and bus 20, refer-ence may be made to the copending patent application "Data Processing System Providing Split Bus Cycle Operation" invented by Frank V. Cassarino, et al which issued as United States Patent No. 3,997,896 on December 14, 1976 and ~6972 assigned to the same assignee as named herein.
Referring now to Figure 2, it is seen that each memory subsystem in accordance with the present invention includes a MOS memory 10-40 which for the purposes of the present invention can be considered conventional in design. For example, the memory 10-40 can be constructed with the memory circuits disclosed in United States Patent 3,786,437 invented by Brian F.
Croxon, et al which issued January 15, 1974.
The memory subsystem 10-1 further includes a plurality of input flip-flops 10-10 through 10-34, a plurality of selector circuits 10-20 through 10-26, an EDAC encoder circuit 10-30, an EDAC decoder circuit 10-50 and error correction, inverter and parity circuits. The plurality of input flip-flops of blocks 10-10 through 10-34 are connected to receive correspond-ing ones of the signals from bus 20. That is, flip-flops 1 through 9 of block 10-10 receive signals BSDTOO-BSDTO7, BSDTOA of a first or left hand byte which correspond to data bits 0-7 and A of the bus 20. Flip-flop 10 of block 10-12 receives a parity signal BSDPOO which contains odd parity for bits 0-7 and A. Flip-flop 11 of block 10-14 receives a parity signal BSDPOl which contains odd parity for data bits 8-15, B of a second or right hand byte.
The flip-flops 12-20 of block 10-16 receive the data bits 8-15, B
of the second byte from bus 20. Further, flip-flops 21 and 22 receive byte and write control signals BSBYTE and BSWRIT during a write operation. The byte signal BSBYTE indicates whether the transfer is a byte or word transfer.
When a binary ONE, it indicates that the current transfer is a byte transfer.
The signal BSWRIT indicates the direction of transfer. When a binary ONE, it indicates that the transfer is from the master unit to the slave unit.
The binary ONE outputs of flip-flops 21 and 22 representative of stored states , of the byte and write control signals are combined in an AND gate 10-36 to produce a BYTE WRITE signal. When the BYTE WRITE signal is forced to a binary ONE, this signals the memory subsystem that it is to perform a par-tial write operation as explained herein.
The signals BSADOO through BSAD23 are memory address signals which are applied to the input address circuits ~not shown) of memory 10-40. (Each 24 bit address includes 8 memory module select bits, 15 internal address bits and a byte designator bit and designates a word storage location in memory 10-40). ~
As seen from Figure 2, it is seen that the output signals of flip-flops 1-20 are applied as one input of corresponding ones of the plurality of one of two data selector circuits 10-20, 10-22, 10-24 and 10-26. The second input to each of the data selector circuits is from the output of the error correction, inverter and parity circuits of block 10-60. The signals CRDO-CRD7, CRDA, CRD8-CRD15, CRDB, CRPO and CRPl are selected from the second input for application to memory 10-40 and EDAC encoder circuit 10-30 during the read portion of a partial write cycle as explained herein.
The output signals WDO-WD7, WDA selected from either flip-flops 1-9 or inverter circuits of block 1-60 by data selector circuit 10-20 are applied to the EDAC encoder circuit 10-30 and to the write circuits ~not shown) of memory 10-40 as shown. In accordance with the present invention, the parity signals WBPO and WBPl, selected from either flip-flops 10 and 11 or the circuits of block 10-60, are applied as inputs to EDAC encoder 10-30.
Further, the byte signals WD8-WD15, WDB from either flip-flops 12-20 or circuits 10-60 are applied as inputs to EDAC encoder 10-30 and memory 10-40.
As explained herein, the EDAC encoder 10-30 generates from the byte data signals WDO-WD15, WDA, WDB and parity signals WBPO, WBPl, check code bit 6~7Z

signals WCO-WC5. The check code signals together with the byte data signals associated therewith are stored in memory 10-40. It will be appreciated that the data and check bit signals RDO-RD15, RDA, RDB, RCO-RC5, when read out from MOS memory 10-40 into a data out register (not shown)" are inverted or complemented. As seen from Figure 2, the inverted bit signals are appli-ed to EDAC decoder 10-50 and the circuits 10-60.
The EDAC decoder 10-50 produces six pairs of complementary syndrome bit signals SOO, SOE through S50, S5E in addition to two error indicator sig-nals YELL and REDD. The sign YELL when a binary ONE indicates the detection of a single error and that correction of the error was made. The signal REDD indicates the detection of a double bit error, a bus parity error or a byte write error as explained herein.
The EDAC decoder circuit 10-50 applies the pairs of syndrome sig-nals and pairs of check bit and data bit signals RGO, RCl, and RDX and RDY
to the circuits 10-60. As explained herein, the circuits 10-60,provide cor-rected signals CRDO-CRD7, CRDA, CRD8-CRD15, CRDB to bus 20 and to data selec-tor circuits 10-20 and 10-26 as mentioned previously. Also, the circuits 10-60 produce the parity signals CBPO and CBPl which are also applied to bus 20 and data selector circuits 10-22 and 10-24.
The data selector circuits discussed above can for the purpose of the present invention be considered conventional in design. The EDAC encoder circuit 10-30, the EDAC decoder circuit 10-50, and the circuits 10-60 are shown in greater detail in Figures 3a through 3c respectively.
Referring first to Figure 3a, it is seen that the EDAC encoder circuit 10-30 comprises a plurality of exclusive OR circuits 10-300 through 10-314 and a NAND gate 10-316 connected as shown. The six exclusive OR cir-cuits 10-304 through 10-314 combine different ones of the data signals and parity signals to generate the check code signals WCO-WC5. The exclusive OR

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, 6~72 circuit 10-300 sums the expansion data bits while the circuit 10-302 sums the parity byte write error signal and data bit 12.
The combinations of signals to be summed are selected in accordance with the matrix of Figure 4a. The matrix illustrates the generation of each of the check code bit signals WCO through WC5. It will be noted that the matrix includes columns representing states of the data bits 0-7, A and 8-15, B. Data bits A and B are additional bit positions to be used for expansion.
A column labeled PDE is used to represent the occurrence of a partial write double error condition which is signaled by the state of signal REDD as ex-plained herein. The column labeled BPS represents the sum of the bus parity bit signals WBPO and WBPl.
In each instance, a check code bit is generated by the exclusive OR of all of the columns which contain binary ONES (odd and even). For ex-ample, check code bit WCO = 10 ~3 11 ~312 ~3 13 ~3 14 ~3 15 ~3 B ~3BPS where BPS = WBPO ~3WBPl.
To provide the summing operation indicated for generating each check code bit, each of the circuits 10-304 through 10-314 employs a parity generator/checker circuit which can be considered conventional in design.
For example, such circuits may be constructed utilizing a 9 bit parity gener-ator/checker circuit designated 82S62 manufactured by Signetics Corporation.
The even output terminal designated E and odd output terminal are in turn applied as inputs to memory 10-40.
Normally, the inputs to each of the exclusive OR circuits are binary ZEROS which corresponds to ZERO volts. When the inputs are switched on or forced to a binary ONE, they assume a positive voltage value. By con-trast, the signal BWDE from NAND gate 10-316 is normally a binary ONE ~posi-tive voltage value). The reason is that both signals BYTE WRITE and REDD
are normally binary ZEROS (i.e., no error and not a partial write operation).

~q36~72 It will be noted that the matrix of Figure 4a is a simplified ver-sion of the matrix of Figure 4b. The matrix of Figure 4b represents a modi-fied version of the so-called H matrix for generating the check code bits for the two byte, 18 bit, data word in accordance with the present invention.
The basic matrix is expanded to include a PDE column for designating a par-tial write double error condition and a BPE column for designating a bus parity error.
In accordance with the present invention, it will be noted that the occurrence of either a bus parity error or a partial write double error ; 10 results in causing the decoder circuit 10-50 to generate syndrome bits hav-ing an even number of binary ONES as explained herein. This results from including an even number of binary ONES in the PDE and PBS columns which relate to an even number of check code bits.
The matrix of Figure 4b has been simplified so as to reduce the number of circuits required for generating the check code bits. That is, the rows CO and Cl in the basic H matrix have been modified so that they require fewer number of binary ONES.
It is seen that in Figure 4b, CO = 0 ~ 1 ~ 2 .................................. ~ 7 ~ 8 ~ 9 ~ A ~ BPE. Substituting into the previous expression, the appropriate value for BPE ~i.e., O ~ 1 ~ ........ 15 ~ B ~ Pl), CO = 10 ~ 11 ~ ...... ...~ 15 ~ B
3 PO ~ Pl. By having BPS = PO ~ Pl; CO = 10 ~ ........ .....15 ~ B ~ BPS.
Similarly, it can be shown that Cl = 0 ~ 1 ~ 2 ....... ~ 6 ~ BPS.
By appropriate selection of encoder signals, certain check code patterns are not produced for the all ZEROS and all ONES data signals. As seen from Figure 4d, that all ZERO and all ONES data signals produce check code bits which do not have all ONES or all ZEROS. This ensures that when there is a catastrophic memory failure rendering the memory inoperative that ~6~7Z

the check bit signals enable the detection of the failure. That is, such failures could give rise to an all ZEROS or all ONES pattern of data and check bit signals. Therefore, the failure could go undetected.
The decoder circuit 10-50 is shown in detail in Figure 3b. The circuit 10-50 is constructed in accordance with the parity check matrix of Figure 4c. It should be noted that this matrix does not include PDE or PBE
columns. The reason is that the errors designated by these columns have been incorporated into the generation of check code bits by encoder circuit 10- 30 and produce syndrome bits which include an even number of binary ONES
upon the occurrence of such errors as mentioned previously.
Referring to Figure 3b, it is seen that the decoder circuit 10-50 includes a plurality of exclusive OR circuits 10-500 through 10-520 arrang-ed as shown. Similar to encoder circuit 10-30, the summing of the different binary ONE columns of the matrix of Figure 4c required for the generation of syndrome bits SO through S5 is also accomplished by means of parity generator/checker circuits. As indicated by Figure 4c, SO and Sl require summation of 12 column signals, and S3, S4 and S5 require summation of 11 column signals. Certain data bits (i.e., RDO, RD6 through RDll, RD12) are summed by exclusive OR circuits 10-500 through 10-508.
Since syndrome bits SO and Sl are produced from an even number of column signals and syndrome bits S2-S5 are produced from an odd number of column signals, both the even and odd output terminals of circuits 10-510 through 10-520 are utilized as explained herein. As mentioned previously, the signals read out of memory 10-40 are complemented. Accordingly, the input signals to each of the exclusive OR circuits are normally in a binary ONE state (i.e., positive voltage level). This means that the output signals RDV, RDW, RDY and RDZ are also in a binary ZERO state. Also, the even out-put terminal, designated E of each of the circuits 10-510 and 10-512 are normally binary ONES while the same terminal of each of the circuits 10-514, 10-516, 10-518 and 10-520 are normally binary ZEROS. The odd output termi-nals, designated 0, of each of the circuits 10-510 through 10-520 are in a state which is complementary to the even output terminal associated therewith.
Figure 3c illustrates the circuits of block 10-60 which locate and correct single bit errors in addition to producing byte parity signals and error signals. As seen from the Figure, the block 10-60 includes a plurality of error location circuits 10-62, a plurality of correction cir-cuits 10-64, a parity circuit 10-66 and a plurality of error generation cir-cuits 10-68 arranged as shown.
The circuits 10-62 designate the particular bit which requires correction in the case of a single bit error. The circuits 10-62 include a plurality of decoder circuits 10-620 through 10-628 each of which receive ;; different combinations of syndrome bit signals. The decoder circuits may be considered conventional in design. For example, they may employ circuits such as an SN74S138 manufactured by Texas Instrument Inc.
As seen from Figure 3c, each decoder circuit has three enable in-put terminals and three binary select input terminals. The syndrome signals applied to the enable input terminals in the case of an error select one of the five decoder circuits while the syndrome signals applied to the select input terminals select the particular bit to be corrected. For example, where syndrome bits SO-S5 have a value 011010, results in the selection of decoder circuit 10-628 and in the forcing of signal ED14 from a binary ONE
to a binary ZERO ~i.e., from a positive voltage level to a zero voltage level).
A different one of the output signals ECO through EDB from the cir-gL1~4t~697;~

cuits 10-62 is applied as one input of a particular one of the plurality of exclusive OR circuits 10-640 through 10-657 of the data bit correction circuits 10-64. Each exclusive OR circuit both corrects and inverts the state of the data bit signal applied as a second input thereto. More speci-fically, normally the signals applied to each exclusive OR circuit is a binary ONE placing the output terminal of each circuit at a binary ZERO.
When no correction is designated, the decoder signal (e.g., signal ED4) re-mains a binary ONE. Therefore, the signal present at the output terminal of the exclusive OR circuit is the complement or inverse of the input data signal (e.g., signal CRD4 = ~~4). When correction is required, the decoder signal is forcedto a binary ZERO state. Therefore, the signal present at the output terminal of the exclusive OR circuit is the same as the input data signal (e.g., signal CRD4 = RD4).
As seen from Figure 3c, the parity circuit 10-66 includes exclu-sive OR circuits 10-660 through 10-666 and a pair of AND gates 10-668 and 10-669 arranged as shown. Parity bit CBPO represents odd parity for bits 0-7 and A while parity bit CBPl represents odd parity for bits 8-15 and B.
She above can be seen from Figures 4a and 4b. CO (encoder) = 10 ~ 12 ~ 13 ~ 14 ~ 15 ~ B ~ BPs where BPS = 0 ~ 1 ~ 2 ........... ~ 7 ~ A ~ 8 ~ 9 ...... ~ 15 ~ B. Substituting the value for BPS into the expression for CO results in the following CO = 0 ~ 1 ~ 2 ..... ~ A ~ 8 ~ 9. By applying signal RDX to exclusive OR circuit 10-660, this effectively cancels out bits 8 and 9 (i.e., RDX = RD8 ~ RD9). Thus, signal CBPO = 0 ~ 1 ~ 2 .... 7 A and represents odd parity for bits 0-7 and A. The same is true for Cl.
In Figure 3c, normally RCO is a binary ONE and signal RBPO is also a binary ONE. When data bit signals RD8 and RD9 are equal, RDX is a binary ZERO. Signal RBPO assumes the same state as signal RCO. When signals RD8 and RD9 are unequal, RDX is a binary ONE. Signal RBPO is the complement of 6~72 the state of signal RCO.
In the case of no correction, signal EBPO is normally a binary ONE
which means that signals ECO, ED8 and ED9 are normally binary ONES. There-fore, signal CBPO corresponds to the complement of signal RBPO. In the case of a correction when signal EBPO is forced to a binary ZERO, signal CBPO
assumes the same state as signal RBPO. The circuits 10-662 through 10-666 operate in a similar fashion to produce signal CBPl.
The last group of circuits in Figure c generates error signals REDD and YELL. The circuits include a NAND gate 10-680, and AND gate 10-682 and an exclusive OR circuit 10-684 arranged as shown. The signal YELL sig-nals the system of Figure 1 when the memory subsystem 10-1 detected a single bit error in a data word which it corrected. The signal REDD signals the system when the memory subsystem 10-1 detected an uncorrectable error which includes a double bit error, a bus parity error or a partial write error.
When there is no error, syndrome signals SOO through S5E are normally all binary ONES. This causes signal RE to be a binary ZERO which causes signal REDD to be a binary ZERO. The circuit 10-684 in this case forces its odd output terminal to a binary ZERO and its even output terminal to a binary ONE.
In the case of a correctable error where there is an odd number of syndrome bits, circuit 10-684 forces its odd terminal to a binary ONE
and its even terminal to a binary ZERO. Hence, signal REDD remains a binary ZERO. Thus, the state of signal RE does not matter in this case.
When there is uncorrectable error where there is an even number of syndrome bits, two or more of the syndrome signals SOO-S5E are binary ZEROS.
This forces signal RE to a binary ONE. The circuit 10-684 forces its even output terminal to a binary ONE and its odd output terminal to a binary :: ~

6~7~

ZERO. This causes AND gate 10-682 to force signal REDD to a binary ONE.
DESCRIPTION OF OPERATION
With reference to Figures 1-3c and Figures 4a-4e and 5, the opera-tion of the apparatus of the preferred embodiment will now be described.
Referring first to Figure 5, it is seen that the bus cycle is 300 nanose-conds in duration. Data is available from a device for an interval of 60 nanoseconds starting at 100 nanoseconds from the start of the cycle as shown in Figure 5.
When the memory subsystem 10-l is addressed and it is not busy, a memory cycle of operation is begun. At this time, the bus has completed 150 nanoseconds of its cycle. After 30 nanoseconds from the start of the memory cycle, valid memory address signals BSADOO-BSAD23 appear at the ad-dress circuits of memory 10-40. During a write cycle, the data signals are available at encoder circuit 10-30, 50 nanoseconds from the start of the memory cycle. At 90 nanoseconds, valid data with check code bits are available for writing into memory 10-40.
As seen from Figure 5, data signals appear at the output of memory 10-40, 400 nanoseconds from the start of the memory cycle. After an interval of 100 nanoseconds, the corrected data is applied to the data selector circuits and bus 20. During a write cycle of operation, data is written into memory 10-40 within 470 nanoseconds and the memory subsystem 10-1 is again available after 620 nanoseconds.
In the case of a byte write operation, the new data bit signals together with check bits are present at the input circuits of memory 10-40, 570 nanoseconds from the start of the memory cycle. A write cycle is begun, at 570 nanoseconds and the new data will have been written into memory 10-40 by 970 nanoseconds from the start of a memory cycle. The memory is available for operation, 1360 nanoseconds from the start of the cycle. The 'f`~6~72 additional delay ensures proper operation of the MOS memory.
It should be noted that if it was necessary to check the parity of the data signals applied to the memory subsystem 10-1, it would require increasing the bus cycle by 50 nanoseconds. The reason is that the memory subsystem would have to make the check and acknowledge this via bus 20. The increase in the bus cycle is illustrated by dotted lines in Figure 5.
An example illustrating the operation of memory subsystem 10-1 in accordance with the present invention will now be discussed with reference to Figures 4d and 4e. It is assumed that one of the devices of Figure 1 applies words A, B, C and D in succession to memory subsystem 10-1 for writing into four successive memory locations during four successive bus cycles. In the first case, the words A through D are shown with no errors.
In accordance with the matrix of Figure 4a, the encoder circuit 10-30 of Figure 3a generates values for check code bits CO through C5 by summing the data and parity bits in each word as designated by the binary ONE bits in the matrix of Figure 4a. The values of the check code bits produced by encoder circuit 10-30 are as indicated.
As illustrated by Figure 5, the data and check code bits of each word are written into memory subsystem 10-1 within the time interval indi-cated. It will be appreciated that from the point of view of memory sub-system operation, there is no recognition of any error present in the stor-ed data until it is read out during a read cycle of operation.
Assuming that a device requests read out of the same four data words, it is seen from Figure 4e that the four words A through D read out from memory 10-40 appear inverted. When they are applied to decoder 10-50, this results in the generation of syndrome bit signal SO through S5 which are all binary ZEROS indicating the presence of no errors (see Figure 4e).

5~72 Referring to Figure 3c, it will be noted that when the syndrome bits SO through S5 are all ZEROS, signals SOE and SlE are binary ZEROS
while signals S2E through S5E are binary ONES. This causes the output sig-nals ECO through EDB to remain binary ONES which simply results in the com-plementing of each of the signals RDO through RDB by the exclusive OR cir-cuits of block 10-64. The signals SOO through S5E condition the error gen-eration circuits 10-68 which cause signals REDD and YELL to be binary ZEROS
(i.e., signal RE is forced to a binary ZERO while the E terminal of circuit 10-684 is forced to a binary ONE).
It can be seen from the above how the arrangement of the present invention generates the appropriate check code and syndrome signals for several different coded words containing no errors.
Now, it will be assumed that bit 0 of one of the bytes of word A
when presented to memory subsystem 10-1 by a device was in error and there-fore contained bad parity. Accordingly, this results in a binary ONE being included in column BPS of Figure 4d. As seen from Figure 4d, this causes check code bits C0 and Cl to be binary ZEROS while check code bits C2-C5 remain binary ONES.
When a device requests for read out of word A during a subsequent read memory cycle of operation, this results in decoder circuit 12-50 forc-ing syndrome bits S0 and Sl to binary ONES. Syndrome bits S2-S5 remain binary ZEROS. This causes decoder circuits 10-510 and lC-512 of Figure 3b to force signals SOE and SlE to binary ONES. The signals S20 through S50 remain binary ZEROS. Accordingly, the even number of ONES in the syndrome bits causes circuit 10-684 Gf Figure 3c to force its even output terminal to a binary ONE and circuit 10-680 to force signal RE to a binary ONE which results in AND gate 10-682 forcing signal REDD to a binary ONE. This sig-nals an uncorrectable error condition to the system.

- . ~

J6~72 It will be appreciated that where there is a single bit error con-dition, this causes one of the columns of syndrome bits in Figure 4f to con-tain an odd number of binary ONES. For example, it is assumed that when word A is read out from memory subsystem 10-1, it contains an error in bit 0. The bit values appear complemented when read out and hence these values are designated by A in Figure 4f.
The decoder circuit 10-50 forces syndrome bits SO, S3 and S4 to binary ONES when bit O is a binary ZERO. Syndrome bits Sl, S2 and S5 remain binary ZEROS. As seen from Figure 4f, word A without errors causes all of the syndrome bits to be binary ZEROS.
More specifically, with reference to Figure 3b, signal SOE is forced to a binary ONE and signals S30 and S40 are forced to binary ONES.
Signal S10 remains a binary ONE while signals S20 and S50 remain binary ZEROS. This results in a code of 001 being applied to the enable input ter-minals of each decoder circuit and a code of 011 being applied to the select input terminals of each decoder circuit. This enables the decoder circuit 10-620 and causes it to force signal EDO to a binary ZERO. This in turn causes the exclusive OR circuit 10-640 to force signal CRDO to a binary ZERO. The odd number of binary ONES causes the circuit 10-684 to force signal YELL to a binary ONE indicating the occurrence of a corrected single error condition.
It will be appreciated that the decoder circuits 10-620 and 10-626 apply signals ECO, ECl, ED7, EDA, ED8 and ED9 to parity circuit 10-66.
Since there are no errors assocaited with any of these bits, both AND gates 10-668 and 10-669 force their outputs to binary ONES. The pairs of signals RCO, RDX and RCl, RDW cause exclusive OR circuits 10-660 and 10-662 to force their outputs to binary ZEROS. The result is that circuits 10-664 and 10-666 force signals CBPO and CBPl respectively to binary ONES.

~ :' Where there is a single bit error associated with any one of the signals RCO, RDX, RCl or RDW, this causes corresponding ones of the decoder circuitS 10-620 through 10-626 to force an appropriate one of signals ECO, ED8, ED9, ECl, ED7 or EDA to a binary ZERO. As mentioned above in signal RBPO
assumes the state of signal RCO when signa] RDX is a binary ZERO. When RDX
is a binary ONE, signal RBPO is the complement of signal RCO. When there is a correction, signals EBPO and EPl are forced to binary ZEROS. Signals CBPO and CBPl assume the states of signals RBPO and RBPl respectively.
By having the data error locator circuits 10-62 provide signals from which the correct parity bits can be produced, reduces substantially the amount of circuits normally required for generating parity signals.
It will be noted that the error locator circuits in response to multiple error conditions produced by double data bit error, a bus parity error or byte write error are not enabled by the syndrome bits SO through S5. That is, the syndrome bits SO through S5 in such instances contain an even number of binary ONES in those column~s) of the matrix associated with the error condition(s). The combinations of syndrome signals applied to the decoder circuits 10-620 through 10-628 produce signals only at the un-used output terminals of these circuits. Hence, no correction takes place.
In accordance with the present invention, the occurrence of a partial write error also will be detected as an uncorrectable error condi-tion. For example, it is assumed that during the read portion of a byte write operation (see Figure 5), the error generation circuits 10-68 detect the presence of a double error in word A. This results in signal REDD
being forced to a binary ONE. During the write cycle of the byte write operation (see Figure 5), the encoder circuit 10-30 causes check code bits C4 and C5 to be forced to binary ZEROS and the new and odd data bytes select-'6~7~

ed by circuits 10-20 and 10-26 are written into memory 10-40.
When word A is read out during a subsequent read cycle of opera-tion, the decoder circuit 10-50 forces syndrome bits S4 and SS to binary ONES. The error generation circuits 10-68 are conditioned by the even number of binary ONES to force its even output terminal to a binary ONE.
This results in signal REDD in being forced to a binary ONE signalling the uncorrectable error condition to the system of Figure 1.
It will be appreciated that a double error in a word also causes the circuits 10-68 to force signal REDD to a binary ONE indicating an uncor-rectable error condition. For example, it is assumed that bits O and 1 of word A are both binary ZEROS when read out during a read cycle of operation.
This causes the decoder circuit 10-50 to force syndrome bits S4 and S5 to binary ONES. This in turn causes the circuit 10-684 to force its even out-put terminal to a binary ONE which results in signal REDD being forced to a binary ONE.
From the foregoing, it is seen how the arrangement of the present invention is able to detect and signal the presence of a variety of uncor-ractable error conditions to a system while enabling the system to operate at maximum speed and efficiency. Moreover, the present invention provides the foregoing without having to increase the number of check code bitSre-quired to be stored. Also, the arrangement of the present invention mini-mi7es the amount of error detection and correction circuits thereby result-ing in increased system reliability.
It will be appreciated by those skilled in the art that many changes may be made to the preferred embodiment of the present invention.
For example, this could include changes in the number of bits included in a word, the type of bus system and type of circuits.

Claims (21)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OF PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a data processing system including a memory subsystem having a memory for storing groups of data signals, each group including a number of data bits and error detection and correction (EDAC) means including an en-coder for generating a group of check code bit signals for each of said groups of data signals for storage in said memory together with the group of data signals associated therewith and a syndrome decoder for generating a group of syndrome bit signals in response to each group of data signals and group of check code bits read out from said memory, said group of syndrome signals for detecting correctable and uncorrectable error conditions within said group of data and check code bits signals, said EDAC means further including EDAC correction circuits comprising:
a plurality of decoder circuit means, each having a number of input terminals and a number of output terminals including first and second groups, said number of input terminals of each decoder circuit being connected to receive a different combination of said group of syndrome signals from said syndrome decoder;
a plurality of data bit correction circuit means connected to re-ceive each said group of data signals read out from said memory, said plura-lity corresponding to said number of data bits, each of said data bit correc-tion circuit means being connected to a different one of said first group of output terminals of one of said plurality of decoder circuit means and being connected to receive a different one of said number of data bits; and, said plurality of decoder circuit means being conditioned by said group of syndrome signals to force a predetermined one of said first group of output terminals of one of said plurality of decoder circuit means to a predetermined state for enabling correction of the check bit by one of said plurality of said correction circuit means when said group of syndrome sig-nals designate the presence of a correctable error condition and said plura-lity of decoder circuit means being conditioned by said group of syndrome signals to force one of said second group of output terminals of one of said plurality of decoder circuit means to said predetermined state for inhibit-ing correction of any of said data bit by said plurality of correction circuit means when said group of syndrome signals designate the presence of an un-correctable error condition.

2. The system of claim 1 wherein said group of syndrome signals in-cludes first and second groups of binary signals, said first group of binary signals being coded to designate which one of said plurality of decoder cir-cuit means is to be enabled for operation and said second group of binary signals being coded to designate which one of said number of output terminals is to be forced to said predetermined state, and said number of input terminals of said plurality of decoder cir-cuit means includes first and second groups of input terminals said first group of each decoder circuit means being connected to receive said first group of binary signals and said second group of each decoder circuit means being connected to receive said second group of binary signals.

3. The system of claim 2 wherein said first group of input terminals are enable inputs and said second group of input terminals are select inputs, said first group of input terminals of each decoder circuit means being con-nected to receive a different combination of said first group of syndrome signals and said second group of input terminals of said plurality of decoder circuit means being connected to receive the same combination of said second group of syndrome signals.

4. The system of claim 3 wherein said first group of said output ter-minals includes no greater than one-half the total number of said output terminals.

5. The system of claim 4 wherein said first group and second group of input terminals correspond to one-half the total number of said input termi-nals.

6. The system of claim 1 wherein said predetermined state is a binary ZERO state and wherein each of said data bit correction circuit means in-cludes an exclusive OR circuit, said exclusive OR circuit being conditioned by said predetermined state from one of said second group of output terminals to complement the state of said data bit signal to correct the correctable error condition.

7. The system of claim 6 wherein said correctable error condition corresponds to a single bit error and said uncorrectable error condition includes double bit and check code bit error conditions.

8. The system of claim 1 wherein said encoder is connected to receive at least one parity bit coded for indicating the validity of a group of data signals associated therewith, said encoder generating said group of check code bits from said group of data signals and said one parity bit to include at least one check bit signal for deriving the state of said one parity bit and wherein one of said plurality of decoder circuit means forces a predeter-mined one of said second group of output terminals to said predetermined state for indicating that said derived state of said one parity bit is in error, said EDAC correction circuits further including logic circuit means connected to said predetermined one of said second group of output terminals and said one check bit signal for producing a signal corresponding to the correct state of said one parity bit derived from said one check bit in parallel with any correction of said data bit signals.

9. The system of claim 8 wherein said logic circuit means includes:
first logic gating means connected to receive said one check code bit signal and predetermined ones of said data bit signals required for deriving the state of said one parity bit signal;
second logic gating means connected to predetermined ones of said first group of output terminals which indicate the correctness of said one check code bit signal and predetermined ones of said data bit signals; and output logic gating means connected to said first and second logic gating means, said output logic gating means being conditioned by said first and second logic gating means to generate said signal corresponding to the correct state of said one parity bit.

10. The system of claim 9 wherein said first logic gating means and output logic gating means each include an exclusive OR circuit.

11. A data processing system including a memory subsystem comprising a memory for storing data signals received from a plurality of devices, said data signals including a number of groups of data bits and a correspond-ing number of parity bits for indicating the validity of said groups of data bits, an encoder for generating a group of check code bits derived from said data signals for writing into said memory together with said number of data bits and a decoder for generating a plurality of syndrome signals from said number of data bits and check bit signals accessed from said memory for locating errors in said data signals, said memory subsystem further compris-ing:
error location circuit means connected to said decoder for generat-ing signals designating locations of single bit and double bit errors, said circuit means including a plurality of decoder circuits, each decoder cir-cuit having a number of input terminals for receiving said syndrome signals and a number of output terminals for generating said signals indicating said locations of said single bit and double bit errors;
a plurality of data bit correction circuits, each being connected to receive a different one of said number of data bits; and, conductor means for connecting each of said plurality of data bit correction circuits to a different one of said output terminals of one of said decoder circuits which designates the presence of single bit error in said different one of said number of data bits, said plurality of decoder circuits in response to said syndrome signals designating single and double bit errors being operative to produce a predetermined signal at a connected one of said output terminals to enable said plurality of correction circuits for correction of only single bit errors in said data bits.

12. The system of claim 11 wherein a number of said check code sub-system bits generated by said encoder designate the states of said number of said parity bits, and wherein said subsystem further includes logic circuit means connected to receive said number of said check code bits and connected to a number of connected and unconnected output terminals of said plurality of decoder circuits, said logic circuit means being operative to produce a number of signals corresponding to the correct states of said number of parity bits in parallel with any required correction of said data bits.

13. The system of claim 12 wherein said number of parity bits and check code bits is one and wherein said logic circuit means includes:
first logic gating means connected to receive said check code bit and predetermined ones of said data bits required for deriving the state of said parity bit;
second logic gating means connected to a predetermined one of an unconnected output terminal which indicates the correctness of said check code bit and to predetermined ones of said connected output terminals which indicate the correctness of said predetermined ones of said data bits; and, output logic gating means connected to said first and second gat-ing means, said output logic gating means being conditioned by said first and second logic gating means to generate said correct state of said parity bit.

14. The system of claim 9 wherein said first logic gating means and output logic gating means, each include exclusive OR circuits.

15. The system of claim 11 wherein said group of syndrome signals in-cludes first and second groups of binary signals, said first group of binary signals being coded to designate which one of said plurality of decoder cir-cuits is to be enabled for operation and said second group of binary signals being coded to designate which one of said number of output terminals is to produce said predetermined signal.

16. The system of claim 15 wherein said number of input terminals of each decoder circuit includes a group of enable inputs and a group of select inputs, said enable inputs of each decoder circuit being connected to re-ceive said first group of binary signals and said select inputs of each de-coder circuit being connected to receive said second group of binary signals.

17. A data processing system including a memory subsystem having a memory for storing groups of data signals, each group including a number of data bits and at least one parity bit for indicating the validity of said data bits and error detection and correction (EDAC) means including an encoder for generating a group of check code bits from said number of data bits and said parity bit of each group for storage with said number of data bits of said each group and a decoder for generating pairs of complementary syndrome signals in response to said data bits and said group of check code bits, said pairs of complementary syndrome signals for detecting double bit errors and single bit errors in said number of data bits, said group of check code bits and said parity bit, said memory system further comprising:
error locator circuit means connected to said decoder for receiving predetermined ones of said pairs of said complementary syndrome signals, said error locator circuit means including a number of decoder circuits, each de-coder circuit having a number of input terminals connected for receiving a different combination of said predetermined ones of said pairs of complemen-tary syndrome signals and a number of output terminals for generating pre-determined output signals indicating the location of single bit errors in said data bits and check code bits and double bit errors;
a plurality of data bit correction circuits, each being connected to receive a different one of said number of data bits and being connected to a predetermined one of said output terminals of one of said decoder circuits which designates the presence of a single bit error in said different one of said number of data bits; and, logic circuit means for generating said parity bit, said circuit means being connected to receive at least one of said check code bits and predetermined ones of said data bits and said circuit means being connected to a number of said output terminals of predetermined ones of said decoder circuits which generate signals indicate the location of single bit errors in said one of said check code bits and said predetermined ones of said data bits, said plurality of decoder circuits in response to said predetermin-ed ones of said pairs of complementary syndrome signals being operative to force different ones of said output terminals to a predetermined state for conditioning said plurality of data bit correction circuits and said logic circuit means for correction of only single bit errors enabling the correction of said number of data bits and the generation of said parity bit to proceed concurrently.

18. The system of claim 17 wherein said logic circuit means includes:
first logic gating means connected to receive said one check code bit and said predetermined ones of said data bits;
second logic gating means connected to said predetermined ones of said output terminals which indicates the correctness of said one check code bit and said predetermined ones of said data bits; and, output logic gating means connected to said first and second logic gating means, said output logic gating means being conditioned by said first and second logic gating means to generate said one parity bit.

19. The system of claim 18 wherein said first logic gating means and said output gating means each include exclusive OR circuits.

20. The system of claim 19 wherein said predetermined ones of said pairs of complementary syndrome signals first and second groups of binary coded signals, said first group of binary coded signals designating which one of said number of decoder circuits is to be enabled and said second group of binary coded signals designating which one of said number of output terminals of said designated decoder circuit is to produce one of said predetermined output signals.

21. The system of claim 20 wherein said number of said decoder circuits is equal to more than one-half said number of check code bits and less than said number of said check code bits.