FR2489986A1 - INPUT-OUTPUT MODULE FOR AN ELECTRONIC COMPUTER - Google Patents

Abstract

I / O MODULE OF AN ELECTRONIC COMPUTER INCLUDING A PLURALITY OF INTERFACE CIRCUITS CONNECTED TO A BIDIRECTIONAL INTERNAL BUS, AND A CONTROL UNIT WHICH, IN RESPONSE TO THE INSTRUCTIONS SENT BY THE CENTRAL LOGIC UNIT CPU, ENGINES THE MICRO- ORDERS FOR THE EXECUTION OF INPUT-OUTPUT CYCLES INCLUDING AN ID DATA INTERFACE UNIT CAPABLE OF CONNECTING A BIDIRECTIONAL GB DATA BUS, CONNECTED TO THE CPU, TO A COUPLE OF IDB, ODB BUSES; A UGP PERIPHERAL MANAGEMENT UNIT WHICH GENERATES THE CI CODE OF THE INSTRUCTION TO BE EXECUTED AND SELECTS IF THE IP PERIPHERAL UNIT FOR WHICH THIS CI CODE IS INTENDED; A UT TERMINATION UNIT THAT MANAGES ERROR SIGNALS; A UDB BUS DECOUPLEMENT UNIT SUITABLE FOR DECOUPLING BETWEEN THE TWO UNIDIRECTIONAL BUSES IDB, ODB; A PRIORITY UP UNIT SUITABLE TO SEND TO THE UGP PERIPHERAL MANAGEMENT UNIT THE PR CODE OF THE PRIORITY IP INTERFACE UNIT.

Description

The present invention relates to a functional unit

  input-output terminal for an electronic computer, which will be called a module thereafter, comprising a plurality of units

  input-output interface and auxiliary circuits.

  Each interface unit creates a communication channel between the central logic unit (CPU) of the computer and a peripheral unit relative to the computer (or vice versa)

as well as data exchange.

  The data transfer operations between the central memory or the CPU of a computer and the peripheral units, through the interface circuits, require the execution of a series of instructions. In order not to unnecessarily engage the CPU, it is advisable to delegate the management of these operations to

  off-center bodies that interact directly with the

  interface cooked. These off-center members, hereinafter called control units, preferably have a simple structure, which however limits the number of interface circuits that each control unit can manage. The input-output part of the computer thus takes a modular structure in which

  each module contains at least a plurality of inter-

  face and the control unit which manages them; the message sent by the CPU contains the address of the module, that of the interface of the

  module and the instruction for the control unit to do accom-

  complete an operation by activating the appropriate firmware.

  The input-output module for an electronic computer according to the present invention provides a plurality of interface circuits connected in parallel to each other to a bidirectional indoor bus, means for managing a plurality of unidirectional channels capable of connecting directly them

  peripheral units in main memory, a control unit

  Pole which, in response to the instructions sent through a command bus by the central logic unit, hereinafter called the CPU, generates the micro-orders for the execution of the input-output cycles, and is characterized by the fact that it includes: - a data interface unit capable of connecting a bidirectional data bus, connected to the CPU, to a pair of unidirectional indoor buses; a peripheral management unit which, in response to messages sent by the CPU through the bidirectional data bus and one of the unidirectional buses generates the code of the instruction to be executed and selects the peripheral unit to which said code is intended; which in response to a request sent by one of the interface circuits or by the means for

  channel management for direct access to peripheral units

  ques the central memory generates a request code which it sends to the CPU through a bidirectional command bus; - a termination unit which manages the error signals emitted by other circuits of the module and by its own control circuits, generating a request transmitted to the CPU through the peripheral management unit; a bus decoupling unit capable of decoupling the two unidirectional buses between them and connecting them to the bidirectional bus to which the interface units and the termination unit are connected; a priority unit capable of sending to the peripheral management unit the code of the highest priority interface unit and / or the means for direct access to the memory, which require to be connected to the CPU , authorizing

  the issuance of the corresponding request.

  The invention will be better described with reference to an example

  illustrated in the attached figures in the-

  Figure 1 shows the block diagram of a module

according to the invention.

3.

  Figure 2 shows the correction control circuits

formal data.

  Figure 3 shows the circuits for determining the priority

  you. Figure 4 shows a simplified block diagram of

the UT termination unit.

  Figure 5 shows a simplified block diagram of

  the PMU peripheral management unit.

  In the block diagram of FIG. 1, the following functional blocks have been indicated: - interface of the commands IC: it is interested in the signals which direct the exchange of signals and / or instructions, through the command bus BC , between the CPU and the module; - UCM module control unit: manages execution

  different input-output cycles generating micro-

  MO commands which, indicated overall in the figure as COM with the instructions issued by the interface of the IC commands,

  manage the other organs of the module: an example of

  tion of the UCM unit is illustrated in the patent application filed in France on 13 AUGUST 1981 under NI 81 15686 - IP peripheral interfaces (IP1 ...... IPn: provide a connection path between the CPU and P peripherals ; an exemplary embodiment of the latter is illustrated in the patent application filed in France on July 9, 1981 under

  n0-81 / 13479 in the name of the plaintiff.

  - priority unit UP: identifies among the peripherals which send the most priority request I, assigning the maximum priority to the error signaling request of the input-output module; - ID data interface: connects the general bus GB to the unidirectional buses IDB and ODB; DM: manages a plurality of unidirectional channels for direct access to the central memory; an exemplary embodiment of the latter is illustrated in the patent application filed in France on July 9, 1981 under the number 81/13478 in the name of the applicant; - UGP peripheral management unit: generates the selection signal SI of the peripheral interfaces and the operating code CI of the instructions to be executed and, in response to the highest priority request, it generates the RIC request code to send to the CPU at through the BC command interface; - UT termination unit: manages the error signals generated as part of the module; it contains

  the command register and the module status register, apparently

  to those present in the IP interface units; - UDB bus decoupling unit: decouples the ODB and IDB buses connected to the bidirectional IOB bus between them

  the IP interfaces and the UT termination unit are connected.

  In FIG. 2, the units for the interface of the data ID-, for the decoupling of the UDB bus are illustrated diagrammatically, and only with regard to the part relating to the control of

  the formal accuracy of the data, that of UT termination.

  Each data word comprises a preset number of significant bits followed by at least one parity bit: 'the diagram in Figure 2 shows the circuits which check

  -the formal correction of the data exchanged with the CPU.

  The significant bits of the data sent on the IOB bus by an IP peripheral interface are sent to the parity generating circuits GP1 and GP2 belonging respectively to the data interface ID and to the termination unit UT, to which the parity bits sent by IP: the parity bits PA generated by GP2 are compared by the circuit-CP3 of the routing unit UT with those sent by IP, causing if necessary the IOE alarm, and by the circuit CP2 of the interface of data ID to those who are

  supplied by CP1, causing the IBE alarm if necessary.

  Since even the IP peripheral interfaces have circuits for parity checking - (not shown in the figure) a possible error is signaled by the IP peripheral interface and by the UT termination unit, but it cannot be propagate to the CPU because the parity of the data is regenerated by GP1 compared to the interface of the data ID

  with that generated by GP1 and added to the bits signi-

  fictitious (emitted by the IP interface) before sending the data to the CPU through the general bus GB. The data coming from the general bus GB is checked in parity by the circuit CP1 of the interface of the data ID, which can generate the error signal GBE, by the circuit CP3 of the termination unit UT which compares the parity with it. that which is supplied by the circuit GP2 possibly generating the error signal IOE and, if they are intended for a peripheral interface IP, by the circuits for controlling the parity of the interface itself. An erroneous data coming from the general bus GB therefore activates the control circuits of all the organs of the

module it reaches.

  Even the termination unit UT exchanges data with the general bus GB from which it receives the command speech, which is written in the command register and to which it sends the content of the status register: the command speech is controlled by the circuits CP1 and CP3 according to the methods illustrated above, the content of the status register arrives, through the IOB and IDB buses to the generator GP2 of the termination unit UT which generates the parity PA for the circuit CP2

(the CP3 circuit is prohibited).

  All error signals generated in the module par-

  come to the termination unit UT where they are stored in the status register and where they cause the emission of messages

for the CPU.

  All data and command transmissions on the general bus GB and on the command bus BC are carried out by means of pilot stages of liana D and line receivers R,

  as also shown in the figure for the data.

  The interface of the IC commands therefore includes the pilot stages and the receivers used for the exchange of signals with the CPU. The circuit arrangement which makes it possible to highlight the highest priority of the I requests sent by the peripheral IP interfaces will now be described with reference to the

  diagram of FIG. 3. It comprises a plurality of circuits

  off-center PC cooked, present in all peri-

  IP spheres and in the UT routing unit, and a centralized part indicated in figure 1 by the UP blocks and, in

party, UGP.

  The request RQ generated inside the peripheral interface IP displays, - in the absence of the signal i, the bistables FB and (at the first pulse of the synchronism clock FS) FF which generates I prohibiting gate 1 and making door 2 suitable. All requests reach a PE priority encoder which provides at all times the code associated with its highest priority input; this code, stored in the register PRR, arrives at the decoder DEC which activates the wire SI corresponding to

  the IP interface. more priority by making it suitable.

  In the IP interface, the signal SI passes through gate 2 to constitute the IRQ request signal which remains until the CPU accepts the request and sends the IAK signal, or until another interface more priority activates its own signal I. The arrival at the PE encoder of a signal I transmitted by a higher priority interface drops the signal SI (and consequently IRQ) while remains the request I which will hardly be accepted the CPU will have satisfied the requests sent

  by more priority devices.

  DMA requests issued by interface units have priority over I requests: they merge

  in a PD priority encoder whose DP output controls a multiple

  MX tiplexer which connects it to the PRR register as soon as the CPU has completed the current cycle at the moment when a request is made

of DMA.

  The module itself, through the UT termination unit, accesses

  from PE and PD coders, whose input it occupies

assigned the highest priority.

  The module request therefore always has priority.

  The priority of an interface only depends on its posi-

  tion in the module and the correct operation of the priority circuit is independent of the actual presence of all the printed circuit boards carrying the interface circuits. This obviates one of the main drawbacks of a known type of circuit arrangement in which a signal propagates from one circuit to another from the highest priority, stopping when it finds a request for this arrangement. is not only slower because the signal propagation time has to be taken into account, but also requires that all the plates be present or that the plates, if necessary, removed for whatever reason, be replaced by appropriate plates which

  guarantee the electrical continuity of the priority circuit.

  In a preferred embodiment the priority coders PE, PD relating to the requests I and the requests of DMA, and the multiplexer MX constitute the block. UP (FIG. 1) while the register PRR and the decoder DEC are included in the 'unit

UGP device management.

  In Figure 4 we have plotted a simple block diagram

  folded from the UT termination unit.

  The command word sent by the CPU to characterize

  the module by authorizing it, or not, to fulfill certain functions

  tions, DMA, etc. arrives at the IOB bus, is checked in parity (GP3, CP3, IOE alarm signal) and, on command of the CPU, is

written in the RCM register.

  The alarm signals generated by all the auto-

  control with which the functional units which include

  place the confluence module in the RSM status register where they are memorized: the presence of at least one alarm activates the adder S which generates the signal RQ for the

  PC priority, not shown in detail because it is essential

  similar to that present in circuits

IP interface in Figure 3.

  The CPU can request to receive, through IOB buses,

  IB and GB, the content of the status register (status word).

  The termination unit also includes a DEM decoder which, in response to the operating code CI of the instructions which the module must execute, activates one of its IST outputs; either the DEM decoder or the priority circuit CP are rendered

  suitable for the presence of a signal on the SI wire.

  8. FIG. 5 shows a simplified block diagram of the device management unit UGP, where we have indicated - the register SCR which stores the addresses sent by the CPU through the buses GB and ODB: these addresses are decoded, by activating one of the selection wires SI, by the same decoder DEC to which the register PRR accesses (FIG. 3); - the ISR register which stores the operating code CI of the instructions sent to the module by the CPU;

  - the logic of generation of SRQ requests which, in response

  IRQ requests generated by the module or by the inter-

  faces and those of DMA (DRQ) generates RIC requests to

send to the CPU.

  In a preferred embodiment the SRQ logic

  includes a ROM addressed by IRQ and DRQ requests.

  Without going beyond the limits of the invention, it is possible for the technician to modify the number and the functions.

  completed by the units that make up the module; let's quote uni-

  as an example, the fact of bringing together in a single functional unit. centralized elements (PE, PD, MX, PRR, DEC) of the

  priority circuit or the ISR register and the DEM decoder.

Claims (8)

  1. Input-output module of an electronic computer comprising a plurality of interface circuits connected in parallel between them to a bidirectional indoor bus, means for managing a plurality of unidirectional channels capable of directly connecting the peripheral units in the central memory, a control unit which, in response to the instructions sent through a command bus by the central logic unit, hereinafter called the CPU, generates the micro-orders for the execution of the input cycles- output characterized by the fact that it comprises: - a data interface unit (ID) capable of connecting a bidirectional data bus (GB), connected to the CPU, to a pair of unidirectional indoor buses (IDB, ODB) ; - a peripheral management unit (UGP) which, in response to messages sent by the CPU through the bidirectional data bus (GB) and one of the unidirectional buses (ODB) generates the code (CI) of the instruction to execute and select (SI) the peripheral unit (IP) for which said code (CI) is intended; which, in response to a request (IRQ) sent by one of the interface circuits (IP) or by the means (DMA) for channel management for direct access of peripheral units to the central memory generates a request code (RIC) which it sends to the CPU through a bidirectional command bus (BC);   - a termination unit (UT) which manages the signals   error errors emitted by other circuits of the module and by its own control circuits, generating a request (IRQ) -   transmitted to the CPU through the device management unit   risks (UGP); - a bus decoupling unit (UDB) capable of decoupling the two unidirectional buses (IDB, ODB) between them and connecting them to the unidirectional bus (IOB) to which the interface units (IP) and the communication unit are connected termination (UT); - a priority unit (UP) capable of sending the device management unit (UGP) the code (PR) of the highest priority interface unit (IP) and / or the means of direct access to memory (DMA) which request to be connected to the CPU, authorizing the emission of the corresponding request (IRQ, DRQ). 2. Input-output module according to claim 1, characterized in that the termination unit (UT) accesses the priority unit (UP) with the highest priority, than the direct access means to memory (DMA) have priority over interface units (IP) and that the order of priority between analog circuits (IP or DMA) is not determined   only by their position in the frame.   3. Input-output module according to claim 1, characterized in that the data interface (ID) comprises:   - at least one pair of airline pilot stage (D) - reception   line driver (R) capable of decoupling the two unidirectional buses (IDB, ODB) between them by connecting them to the data bus (GB); - a first circuit for the parity check (CP1), able to check the formal accuracy of the data coming from the data bus (GB) and to generate a first error signal (GBE)   - a first parity generator (GP) which, in response to the significant bits of a data word coming from the bidirectional bus (IOB), generates at least one parity bit which   is added to the significant bits before sending the data word   born on the data bus (GB); - a second circuit for parity control (CP2) which compares the output of the first parity generator (GP1) with (au) bits (PA) sent (o) by the termination unit (UT)   generating a second error signal (IBE).   4. Input-output module according to claim 1, characterized in that the termination unit (UT) and the interface units (IP) comprise a priority circuit (PC) consisting of - a first bistable ( FB) displays by the signal present at the output of a first door (1) to the first input of which is applied a request signal (RQ) generated within the framework of the unit (IP, UT); - a second bistable (FF) whose data entry   is connected to the output of the first bistable (FB), whose   synchronization input is connected to a synchronization clock   nism (FS) and whose output (I) is applied to the second, inverted input of the first door (1) and to a first input of a second door (2); - the second door (2) of which a second input is connected to the output of the first bistable (FB) and of which a third input is connected to the selection wire (SI) of the interface unit (IP) or of termination ( UT), the output signal from the second gate (2-) constituting the request (IRQ) sent to the peripheral management unit (UGP); - a third gate (3) authorized by the signal present on the selection wire (SI) of the interface (IP) or termination (UT) unit to pass a signal (IAK) emitted by the CPU, after receiving the request, to reset the first bistable (FB);   further characterized by the fact that the outputs (I) of all priority circuits (PC) are connected to the inputs of a first priority encoder (PE) whose output is connected to a first input of a multiplexer (MX ) to the second input from which it is connected to the output (DP) of a second priority encoder (PD) to the inputs of which the requests (DMA) for direct memory access sent by the units are applied   interface (IP) and the fact that the output (PR) of the multiple-   xeur (MX), stored in a first register (PRR), arrives at a first decoder (DEC) which activates one of the selection wires (SI).   5. I / O module according to the claims   2 and 4 characterized in that the output (I) of the unit   termination (UT) is connected to the highest priority inputs   the first (PE) and second (PD) priority encoder.   6. Input-output module according to claims 1,   3 and 4, characterized in that the termination unit (UT) comprises: - a second parity generator circuit which, in response to the significant bits of a data word coming from the bidirectional bus (IOB), generates at least a parity bit (PA) sent to the second circuit for parity check (CP2) of the data interface unit (ID) and to a third circuit for parity check (CP3); - the third circuit for parity control (CP3) which compares the output (PA) of the second parity generator circuit (GP2) with (par) bits of parity of the data word coming from the bidirectional bus (IOB), generating a third error signal (10E); - a command register (RCM) capable of storing a command word sent by the CPU; - a status register (RSM) capable of storing the error signals generated in the module and the content of which (status word) is sent to the CPU in response to an instruction sent by the CPU itself;   - an adder circuit (S) which, in response to the present   that of at least one error stored in the status register (RSM), generates it. request signal (RQ) for the priority circuit (PC); - a second decoder (DEM), authorized by the signal present on the selection wire (SI) of the termination unit (UT) and able to decode the code (CI) of the stored instruction   in the device management unit (PMU).   7. Input-output module according to claims 1, 4   and 6 characterized in that the perimeter management unit   spherical (UGP) includes: - the first register (PRR); - a second register (SCR) able to memorize the addresses sent to the module by the CPU through the data bus (GB); - the first decoder (DEC) to the inputs of which the outputs of the first (PRR) and of the second (SCR) register are connected; - a third register (ISR) capable of storing the codes (CI) of the instructions sent to the module by the CPU; - a request generation logic (SRQ) which, in   response to requests (IRQ) generated by the inter-   face (IP) and termination (UT) and requests (DRQ) sent by direct memory access means (DMA), generates a   request code (RIC) to send to the CPU.   8. Input / output module according to claim 1 characterized in that the request generation logic (SRQ) comprises a memory limited to reading (ROM) addressed by said requests (IRQ, DRQ).