CH640645A5 - Data transfer unit - Google Patents

Description

The present invention relates to data transfer units.

An incessant problem in the field of data processing has been the development of a data processing architecture capable of being suitable for the transfer of information between two or more independent data processing systems. In the past, the exchange of information between data processing systems has been carried out using a recording of the information emanating from a system on a medium accessible to a second data processing system. In the business world where high information delivery speeds are required, the delays involved in the recording technique are unacceptable. This is why it is necessary to provide a logic system to ensure a dynamic exchange of information between independent data processing systems. The attempts made so far to carry out such a dynamic exchange of information have not made it possible to combat the blocking states which can occur when data processing units on different communication lines try to communicate with lines remote communication at very close times via the same information channel. Other problems arise because the logic control system significantly affects the transmission speeds on communication lines that require an exchange of information. Still other problems arise from the fact that there is a need to develop special software to implement intersystem logic.

The object of the invention is to provide a transfer unit which avoids the blocking states of the prior art by means of parallel bidirectional transfer channels, a dynamic allocation of priorities and a capacity for processing transfer cycles to continue the routing of information over the communication lines between which the information is to be exchanged, and requiring no special software to allow any data processing unit to communicate with a remote communication line through the intermediary of the data transfer unit. This is therefore transparent to the software in the sense that the lines linked together appear as a single line for any data processing unit communicating with a remote communication line via a data transfer unit. .

If the transfer unit is to serve as a transfer agent for a data processing unit for which it was not composed, the data in the transfer unit must be modified. As there may be pending cycle time requests at any time during the operation of a transfer unit, pending requests must be met in order to avoid an interruption in the flow of information. In addition, commercial use requires that a transfer unit be brought back to a connected logical state in the shortest possible time.

Another incessant problem in the field of data processing has been to avoid deadlocks in systems comprising several communication lines electrically interconnected by double transfer units, in which each line is connected to central processing units, units for controlling peripherals and memory units.

In an assembly in which several central processing units are connected to a local communication line attempting to communicate with units connected to another communication line and in which one of these central processing units, which has a low priority, has transmitted a cycle time request to the transfer unit the cycle time requests of this low priority unit can be interrupted by the higher priority units before a response from a distant line is received.

Another object of the invention is to provide a data transfer unit allowing a reorganization of the cycle time requests of the central processing units of high priorities until the low priority unit receives a response from the line. distant. Otherwise, the low priority unit could be denied access to the remote line for an indefinite period of time.

In the past, the exchanges of information between data processing systems have been carried out by means of interconnection logic limited to bit transfers and to multiplexed bidirectional transfers. In addition, the intersystem logic controlling exchanges between communication lines was synchronized with the operation of the lines, which considerably affects processing speeds.

Another object of the invention is to provide a data transfer unit in which the communication between the transfer units is asynchronous and the transfer of information in the transfer units is bidirectional and simultaneous.

In prior systems, a data processing unit on a local communication line initiating a request to a remote communication line caused the flow of information on the local line to stop until a response was received. received.

Previous systems have attempted to exchange information between communication lines by satisfying service requests in the order of their appearance. This resulted in delays of s

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memory transfer unacceptable when memory requests must wait for a response. The data transfer unit according to the invention enabling the mentioned aims to be achieved is defined in claim 1.

Line requests can be received in any sequence, and can be identified at the line transfer rate. The transactions can then be staggered in order of priority to ensure optimum efficiency so as to transfer information between communication lines without significantly affecting the transmission speeds on the lines. More particularly, a transfer transaction is identified and the information originating from a line is loaded into a register designated at the rate of transmission on the line. Then, transactions can be served in parallel. Memory transfers are separated from other transfers to avoid unnecessary delays that would occur when memory transfers have to wait for a response from a slower data processor.

In a data processing system, central processing units and memory units are associated with separate logical addresses. Known systems have been limited to information transfers between two communication lines only. In addition, address translation has been limited to a single range of contiguous addresses applied to memories and other devices. These known devices also added an offset to a local address to communicate with a remote data processing unit. This process of shifting a local address is time consuming, which greatly affects the speed of data transfer over the lines.

Another limitation of known systems results from the fact that a single constant offset value was added to a variable address range. In the event that it is necessary to have access to an address not included in a range of remote addresses, this range of addresses cannot be offset due to the constant offset. The range must therefore be widened, which exposes a larger number of addresses than is necessary for consultation by a requesting data processing unit.

Advantageously, in the unit according to the invention, a translation logic provides several ranges of address translation to ensure communications between two or more communication lines, so that a data processing unit on any line is capable of having access to a contiguous range of addresses covering all address processing units on all interconnected lines. In addition, by executing a translation, the local address is replaced in the memory instead of being modified in order to overcome the speed limits of the previous systems.

The data transfer unit is intended to operate in a data processing assembly comprising several communication lines, each line providing a common communication path for several data processing units containing memory units, data control units. peripherals, data transfer units and central processing units which are interconnected therewith. Each line is in electrical communication with a transfer unit and the transfer units in turn are in electrical communication in pairs, which ensures the establishment of inter-system communications between data processing units on different communication lines without interference with the data transfer speeds.

A problem arises when known solutions are applied for the verification of data and control circuits in transfer units. If both a local unit and a remote unit electrically interconnecting a local line and a remote line are to be verified by being disconnected, the communication lines concerned can no longer exchange information. If the units are verified in direct connection and when information is exchanged between the lines, there is a probability that the local and distant lines are both used only for the verification operation, while the other information transfers stop on the lines. In addition, the verification operation may be affected by requests received by the remote unit from other data processing units on the remote line.

According to one embodiment of the invention, the data transfer and the operation of the control logic of the local and remote units can be checked in direct connection without affecting the data transfer speeds on the remote line or without using the remote line resources. In addition, the remote unit neglects all communications received from any other data processing unit on the remote line.

Another incessant problem in the field of data processing has been the detection of errors in information transfer in relation to missing or unresponsive recipient units. In the past, a communication line in a system having two communication lines, each of which provides a common information path for multiple data processing units, was allowed to stop operating if a blocking state occurred. following a recipient unit not responding. To obviate the transfer error, it was necessary to perform a manual restart.

Software systems have also been used to indicate the occurrence of such transfer errors. If a central processing unit on a line ran software until it produced a flag error, software assistance was lost when the line was blocked. No indication of the source of an error could be obtained. The alternative was to place a central processing unit with error detection software in the intersystem logic system. This alternative not only destroyed the transparency of the intersystem logic, but also overlapping complicated the linking logic. Losing its transparency, the intersystem link logic appears as another controller on a line. Data transfer speeds were thus significantly compromised. In systems interconnecting multiple lines of communication, another problem arises, in that special software was required for each line of communication in order to transfer information in the inter-system link logic.

A disease common to most error detection systems in data processing sets is that errors are simply indicated, but are not eliminated.

According to one embodiment of the invention, the transfer unit comprises an error detection and elimination logic which requires no special software or any special special software. The error detection system in a local transfer unit in communication with a local line and with a remote line through a remote unit, detects and indicates the presence of errors as they arise. the source of the local line. As the equipment and software errors that may occur are anticipated, errors are detected before a line blockage occurs. When an error is detected, the detection system sends a response to the local line to complete a local line cycle, freeing up the line for other information transfers.

In the preferred embodiment, the transfer unit is made for a data processing system comprising several intersystem links in order to carry out the transfer of information between two or more communication lines each forming a common information path for several data processing devices electrically connected to these lines.

More particularly, an asynchronous information acquisition means captures, at the transfer speed on the line, the binary information appearing on a contiguous local line and this information is stored in a separate location among several reserved file locations of so as to ensure in parallel several line communications of different types. An information decoding means in electrical communication with the information acquisition means practically identifies with the

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speed of transfer on the line of binary information to be processed by the transfer unit. An information translation means in electrical communication with the information acquisition means selectively converts, at practically the speed of transfer on the line, the local address information to the remote information address and the information of 'remote address in local address information. A logic control means in electrical communication with an information decoding means and the information translation means, and which responds to the information acquisition means, performs a selective reconfiguration of the transfer unit in order to control bidirectional transfer of information in this unit.

The invention is explained in more detail in the following with reference to the accompanying drawings in which:

- figs. 1 to 3 are functional diagrams of a first architecture of a data processing system incorporating the invention;

- fig. 4 is a block diagram illustrating sets of double transfer units providing a communication path between two communication lines;

- fig. 5 is a partial block diagram showing the alternating logical paths in the double assemblies in order to produce a communication path between two communication lines;

- fig. 6 is a time diagram of the operation of a set of transfer units;

- fig. 7 is a block diagram of another architecture of a data processing system incorporating the invention;

- figs. 8A to 8D compose a detailed functional diagram of a data transfer unit according to the invention;

- fig. 9 illustrates graphically the exchange of information between a transfer unit and a communication line;

- fig. 10 is a general block diagram showing a pair of transfer units forming the interface between two communication lines;

- fig. 11 illustrates graphically the exchange of information between two transfer units;

- fig. 12 is a logic state diagram of the operation of a transfer unit;

- fig. 13 is a partially functional and partially graphical diagram of the exchange of information between a local communication line and a remote communication line through a pair of transfer units;

- figs. 14a-14Z, 14AA-14AC are detailed logic diagrams of the transfer unit illustrated in fig. 8.

In fig. 1 to 3, one can see, in functional form, some examples of architecture of data processing system according to the invention.

In the example of fig. 1, two transfer units also called intersystem link units (IS L) 10 and 11 provide an interface between two data processing systems each comprising a bus called a communication line. Each communication line is linked in order of priority with a memory unit, peripheral control units (PCU) and a central processor (CPU). More particularly, the ISL unit 10 is in electrical communication with the memory unit 13, the peripheral control units 14 and 15 and with the central processor 16 via the communication line 12. The ISL unit 11 is in electrical communication with the memory unit 17, the peripheral control units 18 and 19 and with the central processor 20 via the communication line 21. A detailed description of the communication system can be found in U.S. Patent No. 3,939,981.

The system illustrated in fig. 1 establishes communications with any of the communication lines by means of devices connected by each communication line. For example, the central processor 13 can be in communication with the devices connected to the communication line 12 or it can be in communication via the ISL units 10 and 11 with the devices connected to the communication line 21. A An essential feature of the system is the convertible memory function of the ISL units, as will be explained below. The memory units 13 and 17, and the central processors 16 and 20 can thus have the same addresses. The peripheral control units can also have the same addresses provided that they are not shared.

Fig. 2 illustrates a slightly different system architecture, in which several ISL units can be linked to the same communication line. Several communication paths can thus be established between a communication line and another line. In addition, all peripheral control units can be connected to a communication line and access to these control units can be obtained by means of ISL units connected between these control units and the communication line.

The ISL units 30 and 31 are each in electrical communication with a communication line 32. The unit 30 can also be in communication with a communication line 33 via an ISL unit 34. Furthermore, the ISL unit 31 can be in communication with a communication line 35 via an ISL unit 36. This can also be in communication with communication line 35 and with communication lines 32 and 33 through the ISL units 30, 31 and 34. Similarly, the unit 34 can be in communication with the communication line 33, and with the communication lines 32 and 35 through the ISL units 30, 31 and 36. Any device connected to any one of these three communication lines can therefore be in communication with any other device in the system of FIG. 2. The central processors and the memory units 37, 38, 39, can have the same addresses as indicated above, and can be shared over time. Device control units can have the same addresses only if they are not shared over time.

The system architecture illustrated in fig. 3 shows redundant communication paths. For example, a communication line 40 can be in communication with a communication line 41 via a communication mesh 42 comprising a pair of ISL intersystem link units 42a and 42b, or via communication links 43, 44 with their respective ISL units. In the event that the mesh 42 is inactive, the communication can always be established via the meshes 43 and 44. This multiple capacity is achieved by means of a time logic which will be described later, incorporated in each ISL unit, in which an alternate communication path is sought when a communication path is blocked. The memory units 45, 46 and 47 are connected to the respective communication lines.

Fig. 4 illustrates, in the form of a simplified block diagram, a pair of ISL intersystem link units establishing a communication path between two communication lines. Each of the ISL units 50 and 51 creates a path for data and control information between the devices connected to the communication lines 52 and 53. ISL units are identical and each contains a register file of sufficient width to block all of the data. '' transfer of communication lines, including control information and integrity control information. More particularly, the channel number and the address from a local communication line 52 are read by a logical recognition unit 54 forming part of the local ISL unit 50. If the information received contains a channel number or an address which is recognized by the unit 54, the address and the data received are stored in a file 55 comprising four locations. If communication is required between a local line 52 and a remote line 53, the channel number and address received by the local unit 50 undergo conversion per unit of translation logic 56 before being trans5

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remote line 53 via remote ISL unit 51.

In the event that a communication request is launched by the remote line 53, a channel number and an address are read by a logical recognition unit 57 forming part of the remote ISL unit 51. If this information is recognized, the data and the address from the remote line are stored in a remote file 58 comprising four locations. If communication is required with local line 52, the channel number and address are routed to local line 52 through the translation logic unit 59 and the local ISL unit 50. For convenience, both lines are called local line and distant line. This local / remote relationship normally depends on that of the lines which launched a transfer cycle. The ISL unit that receives information from an adjacent line is therefore called the local ISL unit.

The four location codes in files 55 and 58 indicate the logical operations performed by ISL units to control traffic through these units. Files are used to temporarily store the information received from the line. In this way, an ISL unit is not linked to a local line if delays are encountered during the search for access to a remote line. By using register files, all local line traffic flows at normal transfer speed on that line and each of the file locations has a function reserved for a specific type of line transfer. Table 1 shows the types of cycles that can occur during which line information is stored in file registers. Memory write cycles require that the specific register to which they are assigned be empty. This condition is verified via flip-flops which are located in each ISL unit. A read cycle requires that a specific response be preserved in a remote ISL unit. This requirement relates to a general line characteristic which requires that each second half of the cycle (response) is always accepted, and this requirement is satisfied by resetting the flip-flop. Once a write request passes from a local ISL unit to a remote ISL unit, a flip-flop of the full file is reset to zero in order to complete an operation. Conversely, a flip-flop of the full file is not reset during a write request until a response is received from an addressed device connected to the remote line. No request can be accepted by the local ISL unit until the previous response is fully served by the remote ISL unit.

There are two separate information transfer paths through which an ISL inter-system link unit or assembly responds to communication requests. In response to memory requests (MRQ) passing through an MRQ location of a register, an ISL set initiates a response on a local line without first interrogating a remote line. It is important that the ISL unit responds to such requests and releases the local line as quickly as a conventional memory unit. For requests passing through an operation retry request (RRQ) location, the ISL set searches for the response from the destination unit connected to the remote line. Since the destination unit can respond either with an acknowledgment signal (ACK), or with a negative acknowledgment signal (NAK), or with a waiting signal (WAIT), the ISL assembly cannot give a meaningful response to the requesting unit before an actual response is available.

When a local ISL set receives an RRQ request, it responds with a WAIT wait response. The requesting unit connected to the local line then makes a new request until it receives a different response. While the requesting unit is busy, the remote ISL set addresses the destination unit and obtains an ACK, NAK, or WAIT response.

Each time the requesting unit initiates a request cycle, the local ISL set responds with a wait response until an ACK or NAK signal is received from the destination unit. The local ISL set then compares the information received during the request cycle with the content of the RRQ location in the register. If the requesting unit is the same unit as the one which launched the original request, the local ISL set applies the response received from the remote ISL set to the local line. If the latter receives an ACK, NAK or WAIT signal from the destination unit, the local ISL set initiates a similar response on the local communication line.

Each ISL intersystem link set can, with respect to a communication line, restore the receptivity state to a memory of an I / O controller or processor at different times, as it intercepts transfer of information on one line and restart it on a different line. Each ISL set is configured by storing data in translation memories to respond to certain memory addresses, central processor addresses, and channel numbers. During system operation, each ISL set monitors all line traffic and responds to the individual request cycle in a range of identification numbers on behalf of a destination device connected to a remote line to which the cycle was intended. When a local ISL set responds to a line request (BSDCNN), it passes information from the local line to the remote ISL set. This then starts the request cycle on the remote line. The response cycle of the destination unit follows a similar path in the opposite direction and is finally routed to the unit that is the source of the request.

Except with regard to the configuration mode of the ISL assembly which will be described later, an ISL assembly has minimal visibility with regard to the software. The goal is to provide ISL sets that are transparent, allowing the same functions that are established between two devices connected on the same line to be established between two devices connected on different lines.

As an ISL assembly interconnects two communication lines, it can be used as a component in the realization of multi-line configurations. The ISL assembly can undergo any configuration ranging from a simple line extension to configurations that require the sharing of a memory, interruptions from one central processor to another, and double accesses to input controllers /exit. In addition, closed systems can contain multiple lines which are connected by multiple ISL assemblies.

Figs. 5 and 6 illustrate the order of the actions executed during a transfer of information between two communication lines. Fig. 5 illustrates this sequence in functional form, while FIG. 6 illustrates this sequence of actions by means of a time diagram.

We will first refer to the functional diagram of FIG. 5. A request cycle (BSDCNN) is generated by a device connected to a communication line 60. During this request cycle, the register 61a of the file, which corresponds to the type of cycle requested, is explored to determine whether another request occupies the file at this time. In the event that the register is empty, the data associated with the signal BSDCNN is stored in the local register 61a. In addition, it is determined whether or not the interface device 62a of the associated ISL assembly can act as an agent to service the request originating from the communication line 60. If the interface device 62a cannot act as an agent, the BSDCNN signal is neglected. In the case where the interface device can accept the signal, an ACK, NAK or WAIT signal can be transmitted in response to the communication line 60. More particularly if the device to which a communication is to be transferred is a memory unit connected to a communication line 63, an ACK signal is normally sent as a response. If the destination device is a peripheral control unit, it is a WAIT signal which is generated until it is determined whether the peripheral unit will or will not generate an ACK, NAK or WAIT signal . The communication line 60 is then released to continue processing other cycle requests. In the event that the interface device 62a becomes temporarily occupied

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after it has been determined that it can act as an agent for the local line request, this device responds with a WAIT signal.

When it has been determined that a device for which the information to be transferred is intended is available, a local cycle is programmed in the ISL 61 assembly. Programming is required to avoid conflicts with a response or request initiated by the communication line 63. When a first local cycle in the ISL assembly is completed, the interface device 62a is loaded with the address, the control signals and the data coming from the communication line 60. A second local cycle is then launched until a remote cycle is completed in the ISL 64 assembly in order to empty the interface device thereof. In conjunction with programming, ISL assemblies also follow a priority scheme in which memory demands supplant those of other devices, and in which local cycles supersede remote cycles. When the ISL assembly 64 begins a remote cycle, the information stored in the interface device 62a is transferred to a register 64b of the file. At this time, the ISL 64 assembly attempts to send a MYDCNN signal to the communication line 63. When a line cycle is established for the ISL 64 assembly, the information stored in the file register 64b is provided by an addressed device connected to the communication line 63. The information provided by the line 60 is thus transferred to the communication line 63 practically in its original form.

In the case where a device connected to the communication line 63 initiates a cycle request to enter into communication with a device connected to the communication line 60, the operation described above is repeated with the course of the local cycle occurring in the ISL 64 assembly and the unfolding of the remote cycle occurring in the ISL 61 assembly. More particularly, the line 63 sends a signal BSDCNN which is stored in a register 64a of the file. A local cycle is then launched to store the address, control and data signals coming from the line 63 in an interface device 62b. When a remote cycle appears in the ISL assembly 61, the information stored in the interface device 62b is applied to the communication line 60 via a register 61b of the file.

We will now refer to the time diagram in fig. 6. Waveform 65 illustrates a BSDCNN signal initiated by a communication line in response to a cycle request and waveform 66 illustrates the occurrence of local ISL cycles. Waveform 67 illustrates the period during which information is transferred from a local register to a remote register via a transfer unit. Waveform 68 illustrates the occurrence of remote ISL cycles and waveform 69 illustrates a period during which communication is established between a remote file and a device connected to a remote communication line. It is understood that the waveforms shown in FIG. 6 illustrate representative time periods and not specific periods. It is the order of occurrence of the signals that is essential, not their duration.

A first local communication line generates a BSDCNN signal represented by a pulse 65a which is received by a local ISL assembly connected to the communication line. If the interface device is available, the information provided by the local line is stored in this device. The local ISL unit then begins a local cycle represented by the pulse 66a during the duration of which a response to the signal BSDCNN can be generated in order to indicate the availability of an interface device. Upon the occurrence of a transfer cycle pulse, illustrated by pulse 67a, a remote cycle request is initiated. During a remote cycle illustrated by pulse 68a, the information stored in the interface device is transferred to a remote file register connected to a remote communication line. A line cycle request is then initiated by the remote ISL unit and a line cycle is made available to that unit in order of priority.

During this period of time, illustrated by pulse 69a, a BSDCNN cycle is generated on the remote communication line in response to pulse 69a in order to establish a communication channel between a device connected to the communication line and the remote file registry. The information provided by the local line is then applied to the remote communication line. The device addressed by a channel number comprising the information can then receive the information and launch an ACK signal or possibly either a NAK signal or a WAIT signal as described above.

Fig. 7 is a block diagram illustrating another architecture of a data processing system, in which several communication lines can be linked to a single communication line to which all the peripheral control units of a data system can be connected data processing. In addition, if a virtual memory concept is adopted, the memory units of the remote system can be connected to a communication line while the memory units of the local system can be connected to the communication lines communicating directly with the central processors.

The remote memory units 70-72 and the ISL units 73 and 74 are in electrical communication with a communication line 75. The ISL unit 73 is also in electrical communication with an ISL unit 76 connected to a communication line 77. In addition , the ISL unit 74 is in electrical communication with an ISL unit 78 connected to a communication line 79. A central processor 80, an ISL unit 81 and a local memory unit 82 are also connected to the communication line 79. A central processor 83, an ISL unit 84 and a local memory unit 85 are connected to the communication line 77. The architecture of the system thus described allows the use of virtual memory concept according to which the central processor 83 can have access not only to the local memory unit 85, but also to the remote memory units 70 to 72. In a similar manner, the central processor 80 can have access to the local memory unit 82 and to the remote memory units ntes 70 to 72.

The ISL unit 81 is also in electrical communication with an ISL unit 86 connected to a communication line 87. The ISL unit 84 is in electrical communication with an ISL unit connected to the communication line 87. Several control units peripherals 89 are also connected to the communication line 87 to allow the central processors 80 and 83 to have access to common information sources.

Fig. 8 illustrates the routing of data through an intersystem link unit. The control logic for this unit will be described later with reference to Figs. 14.

With reference to fig. 8, a data transceiver 90 receives the data from a local communication line and applies this data to a data line 91 connected to the input of a data file register 92. The line 91 has a capacity of transfer of 16 bits and register 92 has a capacity of 4 x 16 bits. Line 91 is also connected to an input of a comparator 93 whose purpose is to compare the data on the line with the data stored in register 92. The zero bit conductor of line 91 is connected to an input a reset signal generator 94. This also receives a 16-bit initialization instruction via bit conductors 8 to 16 of a 24-bit local address line 96. In response to these signals, the generator generates a reset signal on a line 97 in order to reset the intersystem link unit, as will be seen below with reference to FIGS. 14.

Line 96 is connected to the output of an address transceiver 98 which receives address information from the local communication line. These conductors of bits 8 to 16 of line 96 are connected to the input of an address comparator 99 and the conductors of bits 0 to 9 are connected to the input 12 of a memory address multiplexer of 10 bits 100. Conductors of bits 0 and 1 are connected to input 11 of multiplexer 100 during the response period to 1/0 output load orders. The conductors of bits 8 to 17 of line 96 are connected to input 12 of a s

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10-bit channel address register 101 while the conductors of bits 18 to 23 are connected to the input of a function decoder read-only memory 102. Line 96 is also connected to an address file register 4 x 24 bits 103 and a second comparator 93 input to compare the data on line 96 with the content of register 92.

An address receiver 104 receives address information from a remote communication line and applies this information to a three-state 24-bit address line 105 which is connected to an input of a code decoder 106 via a 4-bit line 107 comprising the conductors 20 to 23. The conductors of bits 20 to 23 of the address line 105 are connected to the 4-bit output of the read-only memory 102. Bit lines 5 to 17 of line 105 are connected to the output of a 13-bit random access memory control register 108 and lines of bits 0 to 23 are connected to the 23-bit output of register d address 103 via a line 110. In addition, line 105 is connected to a 24-bit input of comparator 93 while the conductors of bits 8 to 23 of the line are connected to input 12 d an address multiplexer register 111. The conductors of bits 14 to 17 of the line are connected s at input 11 of an address multiplexer 112. The conductors of bits 14 to 17 of line 105 are connected to input 11 of 4 bits of a memory with selective translation access of 16 x 4 bits 113, the conductors of bits 14 to 17 are connected to an input 12 of a central processor address register 114, the conductors of bits 0 to 23 are connected to an input of interface output control device 115 and the bit conductors 8 to 17 are connected to an input 12 of the register 101.

The data received from a remote communication line is applied, via data receivers 116, to a 16-bit three-state data line 117. The conductors of bits 2 to 15 of this line are connected to the input of a selective access memory progressive counter 118. This counter applies a 3-bit write validation command signal to a line 119 and a 10-bit counting signal to the inputs of the memory command register to selective access 108 via line 120. Data line 117 is also connected to the output of a 16-bit data file transmitter register 121 which applies the information received from register 92 on the three-way line states. The input of the register 121 is connected to an input of the line comparator 93, to the output of the data file register 92 and to an input 1/1 of the multiplexer 111. A third input 1/3 of the multiplexer 111 is connected to the output of the address multiplexer 112, a second input 2 of which is connected to a 4-bit line 122. The 16-bit output of the multiplexer 111 is connected to the address transceiver input 123. The output of this device is applied to the local communication line.

The data file register 92 supplies the data to the comparator 93 during the transfer cycles of the local communication line, to the address multiplexer 111 during the response cycles and to the register 121 during the internal cycles of the link unit. intersystem.

Bit conductors 6 to 15 of line 117 are connected to input II of a memory with selective access memory address translation memory 125 having a capacity of 1.0K x 11 bits. A write validation input 12 of this memory is connected to the bit conductor 5 of the data line 117. A third input 13 of the memory 125 is connected to the output of the multiplexer 100. The memory 125 provides 10 bits of l memory address translated either at the input of a memory reference register 126, or at the input of an input / output load register (IOLD) 127. The memory 125 also applies a bit command signal busy via a line 128 connected to an input of an internal data multiplexer 129. The output of register 126 is connected by a three-state line 130 having a capacity of 10 bits to a second input of the multiplexer 129 and, via the control device 115, to the remote communication line.

The output of the register 127 is also connected, via the line 130, to the control devices 115 and to a third input of the multiplexer 129.

Bit conductors 6 to 9 of line 117 are connected to input II of register 114, the output of which is connected to input II of a central processor definition selective access memory 131 having a capacity of 16 x 4 bits. The input 12 of the memory 131 is connected to the bit conductors 0 to 3 of the line 117 while the input 13 of the memory 131 is connected to the bit conductor 3 of the line 117. The output of the memory 131 is connected to input 15 of multiplexer 129 and to input II of control devices 115. Bit conductors 6 to 9 of line 117 are also connected to an interrupt channel register 132, bit conductors 0 to 15 are connected to the input of a clock and status logic unit 133, the bit conductors 10 to 15 are connected to the input of an interrupt level register 134 and the conductors of bits 0 to 15 are connected to input II of data multiplexer 129. Bit conductors 0 to 4 of line 117 are connected to the input of a mode control register 135, bit conductors 0 to 3 are connected to input II of a central processor source address register 136 and to input II of register 136, and the co Bit drivers 6 to 9 are connected to input 12 of register 136. Bit driver 3 of line 117 is connected to the write enable input of memory 131.

The output of register 132 is connected, via line 122, to input 12 of the address multiplexer 112 as described above, and to input 14 of the data multiplexer 129. The logic unit 133 applies the status bits of the intersystem link unit to the input 13 of the multiplexer 129, and the output of the register 134 is connected to the input 12 of the data multiplexer 129. The output of the register 135 is connected to a control logic which will be described later with reference to FIGS. 14. The output of register 136 is connected to input 12 of memory 113, the output of which is connected to input II of a data multiplexer 137.

The input 12 of the multiplexer 137 is connected to the output of the multiplexer 129, to the input 13 of a data multiplexer register 138 and, via control devices 139, to the remote communication line. The output of the multiplexer 137 is connected to the input 12 of the multiplexer 138. The input II of the latter is connected to the address output of a rotary switch HEX 140 and the output of the multiplexer 138 is applied to the communication line local through data transceivers 141.

Multiplexer 138 provides transceivers 141 with a 16-bit signal. Bits 6 to 9 are supplied by the multiplexer 137, bits 0 to 5 and 10 to 15 are supplied by the multiplexer 129. Bits 0 to 15 from the multiplexer 129 are applied to the control devices 139.

An input from a selective access memory 142 having a capacity of 1024 x 1 bit is connected to the output of register 101. A write validation input 12 from memory 142 is connected to bit conductor 4 of line 117 and the output of the memory 42 is connected to the input 8 of the data multiplexer 129. A control logic which will be described later with reference to FIGS. 14 applies control signals to the conductors 143-145 leading to the inputs of a cycle generator 146. In response to these control signals, the generator 446 generates time signals, as will be seen below.

A brief description of the operation of the communication lines is given in the following to facilitate understanding of the types and formats of instructions and other information received from a communication line by an ISL intersystem link unit. The description of the ISL unit / communication line interface will then be followed by a description of an interface between ISL units and a description of the operation of the unit in FIG. 8 in response to specific line cycle requests.

A communication line provides a communication path common to all devices connected to the line. The line is

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asynchronous by design, which allows devices with different speeds to operate efficiently in the same system. The bidirectional feature of the line allows any two devices to communicate with each other at a given time. The transfer of information between the devices forms a master / slave relationship, the device requesting and receiving access to the line becoming the director device (master) and the device addressed by the master becoming the slave device.

All information transfers are made between master and slave device and each transfer is called line cycle. The line cycle io is the period of time during which the requesting device (master) requests the use of the line. If no other device with a higher priority has made a line request, the use of the line is granted to this requesting device. The latter then transmits its information to the slave device which acknowledges receipt of the communication.

If the request from the requesting device requires a response, the slave device assumes the role of master and the calling unit, which was previously the master, becomes the slave device. Communication between a master device and a slave device requires a response from the slave device when the latter transfers data. In this case, the information request requires a cycle and the transfer of information to the requesting device requires an additional line cycle to complete the function.

A director unit (master) can address any other device connected as a slave unit by applying the address thereof on the address conductors of the line. There are 24 address conductors which can have either of two interpretations depending on the state of the memory reference signal (BSMREF). If the BSMREF signal is at logic level 1, the following format is applied to the address conductors:

0

23

Memory byte address

LSB

If the BSMREF signal is false, the following format is applied to the address conductors:

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7 8

17 18

23 40

Variable uses Destination channel number

Function code

Three types of communication are allowed on a line: a memory transfer, an input / output transfer and an interruption. When devices connected to a line transfer control information, data or interrupt signals, they address each other by a channel number. Along with this channel number, a 6-bit function code is transferred to specify the functions to be performed.

When a director unit requests a response from a slave unit, the director unit switches the line write signal (BSWRIT) to a logic level of zero. In addition, the director unit provides its own identity to the slave unit via a channel number. This is coded on the line's data conductors in the following format:

0 9 10

Source channel number

Variable uses

A channel number exists for each device in a system except for a memory which is identified only by a memory address. The channel number of a slave unit appears on the address line for all device transfers other than 65 memory. This device compares this channel number with its own stored channel number. The device which detects an equivalence is the slave unit and it must respond to this cycle. The response cycle is sent to the control unit by a reference transfer. A second line half cycle signal (BSSHBC) accompanies a transfer in order to identify the line cycle as being that expected by the control unit.

The central processor channel numbers are limited to the range from 00016 to OOF16. The 6 most significant bits of the channel number are set to zero by the central processor logic and the 4 least significant bits only are available. The central processor channel numbers are not used by other devices.

Tables 2 and 3 summarize the common types of line operation, each type requiring one or two line cycles. Information transfers that are considered write operations require only one line cycle while transfers that are considered read operations require an additional line cycle for the response.

Table 4 gives a complete list of the signals exchanged between the ISL link logic and the communication line. These signals are also illustrated in FIG. 9, the legend of which is given in table 15.

The interface signals mentioned below provide the link functions required by a device connected to a communication line to initiate, accept or refuse a line cycle request. It is understood that, when describing these signals, the terms true and false must be interpreted in relation to the signs -I- and - associated with the mnemonic signal. For example, a signal BSREQT— is at a logic level zero when it is true and at a logic level 1 when it is false. A BSAUOK + signal is at logic level 1 when it is true and at logic level 0 when it is false.

The line request signal (BSREQT—), when true, indicates that one or more devices connected to the line request a line cycle. When this signal is false, no request is pending. The data cycle now signal (BSDCNN—), when true, indicates that a specific director unit (for example, a central processor, memory, or control unit) has been granted a line cycle and placed the information on the line for a specific slave unit. When this signal is false, the line is not busy and may be in the inactive case between line cycles. The acknowledgment signal (BSACKR—), when true, indicates to the control unit that the slave unit has received and accepted a specific transfer from the control unit. The negative acknowledgment signal (BSNARK-) indicates to a control unit that a slave unit refuses a specific transfer. For example, a slave unit may refuse to accept a transfer when a busy control unit is addressed for data transfer. The WAIT signal (BSWAIT—), when true, indicates to a control unit that a slave unit cannot accept a specific transfer at this time. The slave unit can be temporarily occupied, and the director unit must reissue successive requests until the transfer is accepted.

The following signals transfer information during a line cycle. Bit conductors BSDT00— to BSDT15 can compose a unique data word, channel number code, lower order address bits or a priority decoding level depending on the operation performed. Thus, data, an address, control information, register information or status information can be routed on the 16 data conductors of a communication line. The 24 address conductors (BSAD00— to BSAD23—) of a line can dial a 23-bit main memory address to select one of 8 million words. Address conductors can also dial a channel number code, an input / output function code on conductors 18 to 23 or even a combination of the three for an IOLD operation (input / output loading) which will be described more far.

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The following signals serve as data, address, and control signals that transfer and control information during a line cycle. The BSMREF signal, when true, indicates that the address conductors 0 to 23 on the line contain a full main memory address. When false, this signal indicates that the address conductors contain a channel number on conductors 8 to 17 with or without function code on conductors 18 to 23, or that the address conductors contain a code address of main memory module on conductors 0 to 7.

The BSWRIT— signal, when true, indicates that a master (master) unit is transferring data to a slave unit. When this signal is false, the initial line cycle signals a read request and the line's data conductors contain the channel number of the requesting unit. If the slave unit accepts the request, this unit responds with a read response during the second line half cycle (BSSHBC). The BSWRIT signal - is true for all operations, except a request to read a control unit or central processor memory, and a read command in / out of central processor. These operations require a response request to provide information to the control unit through a separate line transfer.

The signal BSSHBC—, when true, indicates to a control unit that the information generated by a slave unit is the information previously requested during an initial line cycle.

The BSBYTE— signal, when true, indicates that a current transfer is a byte transfer rather than a word transfer. This signal is used only during memory write operations.

The BSLOCK— signal, when true, indicates that a control unit has requested a change of state of the memory unit latch flip-flop. This signal also authorizes a read-modify-write operation which makes it possible to perform the three cycles for a calling unit without interruption. The first cycle is a read cycle in which the line address conductors contain the memory address, while the data conductors contain the channel number of the calling device. The second cycle is a response cycle during which the line address conductors contain the channel number of the requesting device, while the data conductors contain the data read from the main memory. The third cycle is a write cycle during which the address conductors contain the address of the memory, while the data conductors contain the data to be written into memory. A device can therefore read and modify a specific location in memory while preventing any interruption by another device connected to the line. The memory can however be consulted by other memory requests after the second of the three cycles described above.

The BSDBPL— signal, when true, indicates that a control unit requests a double-word operand from a slave unit. During the first line half cycle, the signal BSDBPL— is returned to the calling unit to indicate that another word is following.

The BSREDD - and BSYELO - signals indicate an error. The BSREDD— signal is generated only by a main memory unit which contains error detection logic. When true, the signal indicates that the memory detected an error during the second half-cycle of a read operation. The BSYELO— signal is generated only by a main memory unit which contains error detection logic. When true, this signal indicates that the memory has detected and corrected an error during the second half-cycle of a read operation.

Three signals are used to indicate the parity of address bits and data bits on a communication line: the address parity signal PSAP00— and the data parity signals BSDP00— and BSDP08 -. The logic level of the signal PSAP00— indicates the odd parity of the address bits 0 to 7. The logic level of the signal BSDP00— indicates the odd parity of bits 0 to 7 of a 16 bit data word; this parity signal therefore indicates the parity of the left byte of a word. The logic level of the signal BSDP08 - indicates the odd parity of bits 8 to 15 of the data word, that is to say the parity of the right byte of this word.

Two signals are used to indicate line continuity and the integrity of logic tests in each device. These quality signals are the BSQLTO - and BSQLTI - signals. If they are continuously true, these signals indicate that each test has been completed successfully. These signals are relayed from device to device from one end of the line to the other and back. This test provides effective continuity control for all available devices.

Nine signals (BSAUOK + to BSIUOK +) are used to monitor link interruptions. All of these signals must be true to validate any device that requests a line cycle. If several devices simultaneously request a line cycle, the cycle is granted to a device only according to the priority level as described above. The memory has the highest priority level and the central processors have the lowest priority level. During simultaneous requests, the requesting device with the highest priority level receives the nine true signals. The other devices receive eight or less depending on their priority level in descending order.

The BSMYOK + signal indicates to a device having the immediately lower priority level that a generating device and certain other devices having a higher priority level have not requested a line cycle within a predetermined time interval. A line cycle can therefore be granted to a unit with a lower priority level if it so requests.

The last four interface signals shown in Table 4 are asynchronous in terms of the functions they perform during launch and normal control of line cycles. The BSRINT - signal, when true, allows all control units to re-initiate an interrupt that has previously been refused by a central processor via a negative acknowledgment signal. The signal BSMCLR— indicates that the CLR push-button (reset) on the control panel of the central processor is pressed or that a sequence is actually operational. If any of the conditions exist, an initialization operation is effectively performed in and for all available devices. When the BSPWON + signal is true, this signal indicates that all power devices in the system are functioning properly. This signal is true when the supply energy is stabilized and it becomes false a few milliseconds before the energy fails.

The communication lines are connected to the ISL intersystem link units through a group of transceivers ensuring the equivalent electrical characteristics required for all line connections, thereby enabling data, address and signal signals. most control signals to be routed to and from ISL units. Fig. 10 schematically illustrates the interface connections between two ISL units. The direction of routing of the signals exchanged between the units is illustrated in fig. 11: the 29 signal routing arrows correspond, from top to bottom, to the order of the signals mentioned in table 16.

The asynchronous interface between the two ISL units of fig. 10 comprises two identical unidirectional lines LIO and L20 which provide parallel bidirectional processing of the information between the two units. Fig. 11 illustrates the transfer of information on one of these two lines. The signals routed on one of these lines is described briefly in the following.

When a local ISL unit needs to transfer information to the remote ISL unit, the local unit sends an RMTSTB + remote sampling signal to the remote unit. This can identify the type of line cycle by the state of the four control signals that accompany RMTSTR +. There is a control signal for

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each type of line cycle (memory request, memory response, operation retry request and operation retry response). The remote unit uses the RMTSTR + signal to sample the four control signals and introduce them into the priority network of its control logic, and it acknowledges receipt of the information by sending an XFRDUN + signal to the local unit. When the local unit receives this last signal, the transfer cycle is completed.

The GENMRQ— (generated memory request) signal, when true, indicates that the local ISL unit has completed a local memory request cycle and requests the remote ISL unit to execute a remote memory request cycle . The GENMRS— (generated memory response) signal, when true, indicates that the local unit has completed a local memory response cycle and instructs the remote unit to execute a remote memory response cycle. The generated operation restart request (GENRRQ—) signal, when true, indicates that the local unit has completed a local operation restart request cycle and requests the remote unit to execute a cycle request to restart remote operation. A GENRRS— signal (generated operation retry response), when true, indicates that the local unit has completed a local retry response cycle and requests the remote unit to execute a response cycle of remote raise. An operation retry response signal (RMRESP—), when true, indicates that a remote ISL unit has received a response during a remote operation retry request cycle. The RMRESP— signal is used by the local ISL unit to sample two response conductors from the remote communication line, namely the ACK and NAK conductors, and to initiate a comparison cycle. The remote line acknowledgment signal (RMACKR +), when true, indicates that the remote unit has received an acceptance response from the remote communication line. This signal is used during operation restart request cycles during which the response from the slave unit must be obtained before initiating a response to the control unit. A negative remote line acknowledgment signal (RMNAKR +), when true, indicates that the remote unit has received a negative acceptance response NAK from the remote communication line. The RMNAKR + signal is used during operation retry request cycles during which a slave unit response must be obtained before initiating a response to a master unit. A response acknowledgment (ANSWAK +) signal, when true, indicates that a local unit has transferred an ACK acceptance response while completing a local operation retry request cycle. The ANSWAK + signal is used by the remote ISL unit as the time signal for processing the associated operation retry response cycle.

A signal translated channel number (XLATOR +), when true, indicates that the local ISL unit has detected a central processor channel number on the local communication line. On reception of this signal, the remote ISL unit performs a conversion of the channel number on bits 6 to 9 present on the communication line. The XLATOR + signal is used when an ISL unit transfers interrupts from central processor to central processor, or processes either an output interrupt control instruction or an input interrupt control instruction.

A remote function signal (RMTFUN +), when true, indicates that a local ISL unit has received an order addressed to a remote ISL unit.

An ISL reset signal (MYMCLR—), when true, indicates that the local ISL unit is performing a reset sequence. A signal (TWINCN—) (ISL unit connected), when it is true, indicates that the remote ISL unit is connected correctly. An address parity error signal (LCAPER +), when true, indicates that the local ISL unit has detected an address parity error on the communication line. Upon receipt of this signal, the remote ISL generates incorrect address parity during a remote communication line transfer. In this way, the error can be passed to the final destination before being reported.

A data parity error signal (LCDPER +), when true, indicates that the local ISL unit has detected a parity error in the data on the communication line. Upon receipt of this signal, the remote ISL generates an incorrect data parity signal during a transfer of remote communication lines. In this way, an error is transferred to the final destination before the error is reported.

A nonexistent memory signal (NOXMEM—), when true, indicates that a remote ISL unit has received a negative acceptance response NAK 'from memory during a request to write to memory. Upon receipt of this signal, a local ISL unit attempts to generate an interrupt. A signal (WTIMOT +), when true, indicates that the remote controller has exceeded the time limit. Upon receipt of this signal, the local ISL unit attempts to generate an interrupt signal. A signal (RMTOUT—), when true, indicates that the remote ISL unit has received no response, i.e. neither an ACK signal, nor a NAK signal, nor a wait signal WAIT.

The transfer of information between ISL units forms a local-remote relationship. The unit which transmitted the information is called the local unit and the unit receiving the information is called the remote unit. All information transfers between ISL units are from local unit to remote unit and each transfer is called transfer cycle. This local / remote relationship is similar to the master / slave relationship on the communication lines. When a director (master) unit requests a cycle on a line, the ISL unit which intercepts the cycle becomes a local unit.

In other types of cycle requests, a slave unit must respond with an ACK, NAK, or WAIT signal, with a high probability that any of the three responses can occur. In these cases, an ISL unit cannot give a meaningful response to a controlling unit until the destination slave unit has responded. The following types of line cycle request can occur: input / output device output request, input / output device input request, memory read request test and block signals, interrupts.

In the event that one of these types of line cycle requests is received at a local ISL unit, the ISL unit responds with a WAIT wait signal. The director unit connected to the local line can then initiate the line cycle request until another response is received. While the director unit is thus occupied, the remote ISL unit addresses a slave unit in order to obtain an ACK or NAK response. During the next line cycle request from the director unit, the local ISL unit provides the response from the slave unit. The ISL unit that addresses a slave unit on a remote line becomes a remote ISL unit. When the communication requests a response, a unit that was previously controlled becomes a controlling unit. In addition, a remote ISL unit in the previous cycle becomes a local ISL unit.

There are three basic cycles which are generated in an ISL unit: a local cycle, a remote cycle and a transfer cycle. A local cycle is generally launched to act on the information in the address file register 103 and the data file register 92. A local cycle can also be launched when no remote cycle or file information cycle is pending, but when there is however an ISL cycle interrupt, a timeout allocated to a memory or a timeout allocated to an input / output device. Local cycles can also occur during a zeroing sequence of the director device in order to increase the content of the selective access memory counter 118 to a value of 1024, and to initialize all the locations of the access memory selective in the ISL unit. When an ISL unit begins a local cycle to process information from the address file or the data file, no transfer cycle can be in progress.

A remote cycle is initiated by a remote ISL unit to receive information from a local unit. If local cycle requests

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and remote are received simultaneously, the local cycle request is honored first. Remote cycles can occur in response to any of the following four remote instructions: generated memory request, generated memory response, generated operation retry request, and generated operation retry response. To initiate a remote cycle, an ISL unit must not be engaged in either a local cycle or a line comparison cycle.

A transfer cycle is initiated to transfer information from a local ISL unit to a remote ISL unit. A local ISL unit transferring data to a remote ISL unit generates a transfer cycle and initiates the initiation of a corresponding remote cycle. The transfer cycle ends at the initiative of the local ISL unit when a remote cycle is detected in the remote ISL unit.

When it generates one of the cycles described above, an ISL unit can be in one of the three main logical states. More particularly, a central processor instruction can load the mode command register 135 with a binary signal suitable for placing an ISL unit in one of the following three logical states: zero setting, stop and direct connection. The passage from one of these states to the other occurs in response to an I / O device control command or to a connected power supply sequence. The input / output instructions can be initiated by the local communication line or by the remote communication line.

The logic state set to zero is transient. This state is established when a control instruction requests the initialization of an ISL unit, or when a connected supply sequence is launched. In the reset state, a local central processor can reset the local ISL unit by setting each translation cell in memory 125 to logical state 1 and clearing all other register and memory locations. As a result, the information relating to the configuration of the ISL unit is deleted in the memories 113, 125, 131 and 142. The ISL unit therefore does not respond to any line cycles, except for cycles relating to a channel number .

An ISL unit is placed in the shutdown state either automatically from the zeroing state, or in response to a control command required by it. When the ISL unit goes from the direct connection state to the stop state, it retains all the configuration information in the memories 113, 125, 131 and 142 which existed previously in the stop state. While in the stopped state, the unit does not respond to any line cycles except those relating to the channel number of this unit. It is only during a stop state that the ISL unit accepts instructions to modify the configuration information.

The direct connection state is taken in response to a control instruction specifically requesting that the ISL unit be put into data transfer. In this state, the ISL unit responds to line cycles concerning the channel number of this unit on the condition that they are not configuration control instructions, and it responds to line cycles targeting memory locations 142 having a bit 1 (channel occupancy bit) and the locations in memory 125 having a bit 1 (memory occupancy bit). The ISL unit can however be configured to operate in special test mode. This test mode refers to line responses occurring during a test and verification phase which will be described later.

An ISL unit can also be placed in any of five logic control modes indicated by an input / output device output instruction word. The control modes include reset mode, stop mode, resume mode, circulation mode and NAK operation restart mode.

The zeroing mode indicated by the contents of register 135 occurs when any of the following conditions occur: 1) a zeroing function of the steering device is produced during application of the supply energy to the ISL unit, 2) a power failure occurs, 3) an initialization bit

(zero bit conductor in lines 90 and 116) is in state 1 in an output command, 4) a zeroing function of the directing member is produced while a reset push button director zero is depressed on an operator control panel.

The appearance of any of the first three conditions gives rise to the initialization of all the configuration data in the ISL unit.

When a line director reset function is produced, the ISL unit remains in a logical state in progress and the ISL configuration remains unchanged. A director device reset sequence is initiated simultaneously in the local ISL unit and the remote ISL unit. The sequence continues until the ISL registers (interrupt channel register 132, interrupt level register 134, mode control register 135) are set to zero. The ISL unit interrupt level is thus set to zero. Local operation restart cycles are generated during the zeroing sequence of the control device, and the counter 118 sees its content increase to the value 24 (CNTR1K). When the CNTR1K signal is valid, it ends the zeroing sequence. All random access memory locations in the ISL unit are then initialized and the ISL unit responds only to line traffic destined for its channel number.

In stop mode, an ISL unit responds only to line cycles concerning its own channel number. Any instruction which tries to communicate via the ISL unit is neglected and gives rise to timeout, as will be seen below. Any memory or input / output device read cycle that is accepted before receiving a stop command is completed before putting it into stop mode.

In recovery mode, the ISL unit is returned to direct connection mode. The unit responds to line cycles targeting its channel number on the condition that there is no configuration command instruction. In addition, the ISL unit responds to the occurrence of busy bits at the outputs of memories 125 and 142.

The relationship between the logical states and the logical control modes that an ISL intersystem link unit can take is illustrated in fig. 12. The three logical states that an ISL unit can take are the direct connection state 150, the stop state 151 and the reset state 152. If a unit is in direct connection and receives a command command of output of input / output device to put it in recovery mode, the direct connection state is resumed as illustrated by the loop 153. If the logical decision is to pass from the direct connection state 150 to the stop state 151, l The ISL unit must be placed in logic stop control mode to make this switch.

When the ISL unit receives a control mode ordering it to go into stop mode while it is in the stop state, the stop state is reintroduced as illustrated by the loop 154. If the ISL unit must go from the stop state 151 to the reset state 152, the ISL unit must be put into zero mode to effect this passage. The reset state 152 is temporary, this is what the broken lines symbolize in FIG. 12. When it is set to zero state, the ISL unit automatically goes into stop state 151, as symbolized by the line 155 in FIG. 12. The zeroing state may also be taken from the direct connection state 150 via a zeroing control mode and in response to a power up or power off action. food. If a power failure occurs while the ISL unit is in the direct connection state, the unit will remain in this connection state for approximately 1.5 ms to allow status notification between communication lines.

When a control word is stored in the mode control register 135 of FIG. 8, the output of the register indicates to the control unit the type of response required from the ISL unit. When the zero bit is in logic state 1, the setting mode of the director device is controlled. When bit 1 is at state 1, a recovery mode is commanded. A stop mode is commanded when bit 1 is at zero level. Bits 2 and 3 in register 135

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control the circulation mode and bit 4 controls the NAK restart mode of operation. More particularly, the ISL unit initiates a NAK response when bit 4 is in logic state 1, and a WAIT wait response when bit 4 is in logic state zero.

It is understood that neither the circulation mode nor the NAK operation restart mode are represented in the state diagram, since they have no effect on the logical states of the ISL unit. The circulation mode is a test mode during which the local and remote ISL units and the interface logic between the ISL units are tested. The NAK retry mode allows a NAK response to be sent to a device that has requested service during an ISL unit busy state. This mode is used to temporarily place a device on a higher priority from a communication line while the ISL unit responds to a central processor.

The operation of the ISL unit shown diagrammatically in FIG. 8 is described in the following. During the operation of the unit, the information is received from the local communication line via transceivers 90 and 98 and is stored in registers 92 and 103. These jointly constitute four storage locations 40 bits to identify the type of information transfer to take place. An MRS memory response is assigned the location with the highest priority level, location 3. The next priority level is assigned to location 2 where an MRQ memory request is stored. An MRS operation retry response is stored in location 1 and an RRQ operation retry request is stored in location zero.

There are two separate logical decision paths taken by an ISL unit for processing line requests. In a first approach, the ISL unit responds to a line cycle request without interrogating a remote communication line. In the second approach, the actual response from the destination unit must be obtained by an ISL unit before a response can be made to a line cycle request. For each request, there are three possible responses: an ACK acceptance response, a NAK negative acceptance response, and a WAIT wait response.

The ISL unit makes an ACK acceptance response if the file location is not full, or a WAIT wait response if the file location is full. The ISL unit never responds with a NAK response to the following line cycle requests: memory read request, memory write request, memory read response, memory read request and reset, d request 'write to memory and reset, and input / output device input response.

It is important that the ISL unit responds to line cycle requests and frees up the line to avoid unnecessary reduction in cycle speeds. If an ISL unit accepts a memory request cycle and receives a NAK response from the remote line, the ISL unit must initiate an interrupt on the local line to obtain a write cycle, or generate a second line half cycle with incorrect priority for a read request, as will be seen below.

A local MRQ cycle occurs in response to an activity bit at state 1 in registers 92 and 103 when the information received from the local line is stored. The memory request is generated to read or write to the remote memory. In the case of a read, the location 2 of the registers 92 and 103 remains filled and these locations are reset only when a response is received from the remote memory. The response is in the form of MRS data loaded into location 3 of the registers of the remote ISL unit, corresponding to registers 92 and 103 of FIG. 8. The remote ISL unit then requests a cycle to transfer the data to receivers 104 and 116. The data is then applied to transceivers 123 and 141 via lines 105 and 117, and from there they are sent to the local communication line. Address information is obtained from register 92 during a remote cycle in the local ISL unit. At the end of the transfer of data from the remote communication line through the ISL unit of FIG. 8, a new cycle request can be received from the local communication line.

It is understood that there are four communication line cycles which concern a read operation between communication lines interconnected by a pair of ISL intersystem link units. On the other hand, a read operation on a single communication line only involves two line cycles. Each local cycle presented to an ISL unit must be doubled on a distant line. The number of cycles required for a transfer of information between communication lines is therefore doubled compared to that required for the transfer of information on a single line.

We will now describe two other information transfers, namely the RRQ operation retry request transfer and the RRS operation retry response transfer. The RRQ transfer never initially gives rise to an ACK signal. A WAIT wait signal must initially be initiated until a response is received from a device connected to the remote line. An RRQ transaction occurs, for example, when a memory location needs to be read to determine if it is being used. If not, the data contained in the location can be modified or replaced. Once an RRQ request is made, a full bit is set in the zero location of registers 92 and 103 to indicate a busy state. A local ISL cycle is then generated and is followed by a remote ISL cycle and by a remote communication line cycle as described above. When a response is received from the remote line, the response and a remote response control signal (RMRESP) are sent to the local ISL unit. It is understood that a WAIT wait response is indicated by the absence of an ACK or NAK response.

As previously described, when an ISL unit receives a line cycle request, selective line control signals are queried to determine which of four locations in registers 92 and 103 are used to receive binary coded information from the line. Each of the four locations is associated with a busy bit called a full bit. This bit is true when an associated location is loaded and designated to be associated with an ISL unit. Such a designation occurs in association with the generation of busy bits by the memories 125 and 142 of FIG. 8.

The solid bit prevents other information from being loaded into the corresponding location. The other three locations of registers 92 and 103 can be loaded if a full bit is not set there. A full bit is reset, whenever the content of the corresponding location is no longer necessary for the use of the ISL unit. For example, the full bit of the memory request location will be reset when the interface output devices 115 and 139 are loaded during a local MRQ memory request cycle of a memory write operation. In the case of a memory read operation, however, the full bit is not reset until a remote memory response cycle (MRSCYR) occurs.

Each location of registers 92 and 103 is also associated with a local activity bit (2DO bit) which excites the cycle generator 146. More particularly, the generator is excited by the activity bits of the local ISL unit and by a remote activity bit (RMT2D0—). When a local cycle is generated, the corresponding activity bit is set to zero.

When a free state appears in the local ISL unit and a line cycle request on the local line, a line comparison cycle is started in the local ISL unit. The comparator 93 compares the 40 zero location bits of the registers 92 and 103 with the information received from the transceivers 90 and 98 associated with the local line. If an equivalence appears, the response received from the remote line is sent to the requesting device on the local communication line.

It is thus clear that, when a device connected to the local line requests a line cycle on the distant line, this device

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receives a wait signal from the local ISL unit until a response is received from the remote communication line. If the response is an ACK or NAK signal, the local device continues to request the line cycle. As long as the response is a wait response, the local device continues to allow RRQ request signals to be generated. The central processors control the generation of an RRQ signal in an ISL unit when input / output commands or a memory test instruction are launched. The peripheral control units can also control the generation of RRQ signals when an interrupt instruction is sent to a central processor on a remote line.

When a write operation is requested, the full bit in the registers 92 and 103 is reset to zero when the information stored in the registers is loaded in the control devices 115 and 139. Other communication requests can then be done by the local line. If the read operation is requested, the central processor takes a waiting state until the data is received from the remote line. The full bit in registers 92 and 103 therefore remains at state 1 until the data is received from the remote line.

In a system comprising several central processors, the comparator 93 may indicate that a non-equivalence in the case where a central processor with a high priority level connected on a local line tries to gain access to a local ISL unit which has stored previously information from a central processor having a lower priority level. To avoid central processor blocking, a NAK negative acceptance operation restart logic which will be described later is activated by the central processor having the lower priority in order to send a NAK signal to the central processor having the level of higher priority.

It is understood that the structure of the ISL unit illustrated in FIG. 8 provides several communication paths between the local and remote communication lines. More specifically, the local ISL unit allows four information transfer transactions to be queued in registers 92 and 103. One of the transactions may be in progress during a local ISL cycle while the other three are pending. During this period, only selected control signals from the remote ISL unit are received. Any other information supplied by the remote ISL unit to receivers 104 and 115 is inhibited. When the local cycle and the other pending cycles are completed, the local ISL unit begins a remote cycle during which the information contained in the receivers 104 and 116 is sent on the lines 105 and 117 to the transceivers 123 and 141, respectively. A typical operation of the local ISL unit can thus take place in the following manner. The local communication line can hear a BSDCNN signal which is sent to the local ISL unit to load registers 92 and 103. The remote ISL unit can then supply or send information to receivers 104 and 116. As a local cycle has priority over a remote cycle, the information contained in registers 92 and 103 is first sent on lines 105 and 107 to the remote ISL unit via the interface output devices 115 and 139. The logic level of lines 105 and 117 is then changed to apply the receiver outputs 104 and 116 to the transceivers 123 and 141 and thus to the local communication line.

The four transaction types, the priority levels assigned to the transactions and information transfer cycles, and the architecture of the ISL units are used jointly to carry out information transfers without significantly affecting the transfer speed on the communication lines. . In the preferred embodiment described herein, a line cycle has a duration of about 175 to 300 ns. In this approximate time range, no influence was detected on the routing of information on the communication lines.

In the light of the above, we will discuss in the following a more detailed description of the routing of data between the local communication line and the remote communication line. ISL intersystem link units work in two modes: an information transfer mode and a configuration mode.

In the information transfer mode, an initial BSDCNN signal of the local line is received by the transceivers 90 and 98 (fig. 8) and then loaded into the registers 92 and 103 if the registers are found empty. If a memory request (MRQ) is to be served during a local ISL cycle, the information of the local line is entered in location 2 of registers 92 and 103. If the full bit of the registers is not at state 1, location 2 is loaded unconditionally with the information, whether or not the local ISL unit is available as an agent to service this cycle. While the data information is written in the registers 92 and 103, the transceivers 90 and 98 address the address memory 125 via the multiplexer 100. If an activity bit, which will be explained later , is present in the address space, an MRQ cycle is started. In addition, the address contained in the location addressed in the memory 125 is loaded into the memory reference register 126. When the local unit undergoes a local cycle, a memory address is therefore available.

Memory address conversion appears in bits 0 to 9 of memory output 125. Bits 0 to 9 represent up to 1024 memory modules of 8.0K, while bits 10 to 23 represent a memory module 8.0K. There is therefore a total of 8.0 megamultiplets of memory which can be addressed via communication lines. The memory 125 constitutes a means for translating any one of the 1024 modules addressed during a memory request cycle. Translation enables communication between devices connected to separate communication lines, in which similar memory devices can have the same addresses.

Each ISL unit contains a channel number memory having a capacity of 1024 bits, such as the random access memory 142. Each bit of the memory is called activity bit and represents a channel number. More particularly, the activity bits represent the channels which do not actually exist on the local line, but which require the ISL unit to respond. The ISL unit accepts any reference to a device other than a memory whose channel number corresponds to an activity bit located at logic level 1.

When the loading of location 2 of the data register 92 and of the address register 103 is complete, a full memory request bit is set to state 1 if each of the following three elements occurs: a bit of memory activity is produced by translation memory 125, the memory reference signal received from the local line is true, and the line blocking signal from the local line is false. The full bit in turn causes the establishment at state 1 of a 2D0 activity bit, by which a cycle generator 146 is controlled and launched a local MRQ memory request cycle.

While the devices 115 are loaded from the registers 103 and 126, a data word in the register 92 is routed by the transmitter register 121 and the line 117 to be applied to the input II of the data multiplexer 129. The output thereof is selected to apply the signal at its input II to the control devices 139. The control devices 115 and 139 form the local half of the interface unit 62a of FIG. 5 as suggested by the broken line. The other half of the interface unit 62a is part of the remote ISL unit 64.

When the local cycle is completed, the logic control system initiates a sampling signal to validate the control devices 115 and 139 and thus initiate a transfer cycle in order to convey the information from the local communication line to the remote ISL unit.

In the event that the remote ISL unit requests an MRQ memory request, the local ISL unit in FIG. 8 starts a remote cycle during which the address information and the data of the remote communication line are applied via the d5

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receivers 104 and 116 on lines 105 and 117, respectively. When the local ISL unit begins the remote cycle, the logic control system for that unit signals the end of the transfer cycle to the remote ISL unit. The interface between the ISL units is then free to perform other information transfers.

Bits 0 to 23 of line 105 are applied by the multiplexer register 111 to input II of the transceivers 123. The data word on line 117 is applied to input II of the data multiplexer 129 whose output is applied through the register of the data multiplexer 138 to the transceivers 141. When the logic control system initiates a sampling signal to validate the transceivers 123 and 141, the information received from the line remote communication is applied to the local communication line in order to complete the remote cycle. In the foregoing, the operation of an ISL inter-system link unit has been described during a local cycle and a remote cycle in response to a memory request.

If an RRQ operation restart request is received from the local line by the local ISL unit, the line information is applied by the transceivers 90 and 98 to lines 91 and 96 respectively. The information is loaded into registers 92 and 93 as described above. Bits 8 to 17 of the address, which identify a director device (master device having launched an order) on the local communication line, are applied by line 96 to input II of the channel address register 101. The latter then addresses the memory 142. If a bit 1 occupies the address space, the output of the memory 142 goes to logic level 1, identifies the local ISL unit as an agent to service the request launched by the master device. The control logic reads the output from memory 142 and then sets the full RRQ bit in registers 92 and 103 to state 1. No other information can therefore be loaded in the registers before a response is received. received from the remote communication line. The control logic also launches sampling pulses as described above to route the address information stored in the register 103 on lines 105 and 147 in order to apply this information to the input 12 of the devices 115. The 16 bits of data received from file 92 are routed by the transmitter register 121 and line 117 to input II of the multiplexer 129. The register 92, however, may or may not contain valid data. If the master device has issued an exit or write command, the data is transferred to an addressed device connected to the remote communication line. If the command launched by the master device is a read command, the only information that must be transferred to the remote ISL unit is the address of the master device. No data should be transferred.

If a read order has been received from the local communication line, the address of the master device on the local line is stored in the data register 92. In addition, the read order is transferred to the logic of control of the remote ISL unit as will be seen below with reference to FIGS. 14. The control unit of the remote ISL unit reads the read order and then launches the address of the remote ISL unit by actuating a rotary switch corresponding to switch 140. The address of the ISL unit is found applied via a data multiplexer analogous to multiplexer 138 and via remote transceivers analogous to transceivers 141 to the remote communication line during the remote operation retry request cycle . When the remote transceivers have received a response from the remote communication line during a second line half cycle, the address information received by the remote transceivers is compared to the remote address code by a comparator d addresses such as comparator 99. If an equivalence is detected, the comparator signals this to the remote control unit. The 2D0 activity bits at location 1 of the remote address and data registers are then set to state 1 by the remote control logic in order to initiate an RRS operation restart response cycle in the remote ISL unit. The data received from the remote file registers is then transferred to the remote interface output control devices. When starting a transfer cycle in the remote ISL unit, the data is routed to the receivers 104 and 116 of the local ISL unit. In response to the transfer cycle, the local ISL unit initiates an RRS operation restart response cycle in order to route the data received from the receivers 116 to the transceivers 141 and then apply it on the local line. More particularly, the data received from the remote ISL unit by the receivers 116 are applied by the line 117 to the input II of the multiplexer 129 to be then applied to the input 13 of the multiplexer 138. The output of the latter is applied via the transceivers 141 on the local communication line. To complete the read operation, the address of the director device which is stored in the data register 92 is applied by the multiplexer 111 to the transceivers 123 connected to the local communication line.

The transfer of information in the ISL units is now described in connection with specific input / output instructions traversing the ISL units. The format of these instructions is irrelevant for ISL units specific to a device connected to a remote communication line. They simply appear to ISL units as data which are routed through the ISL units to a communication line. If an input / output instruction is transferred by the local ISL unit to the remote unit, an ACK signal received from the remote unit in response to the instruction sets the full bit in registers 92 and 103 to the state 0. Another transfer of information is thus established from the local communication line. In the case of a read command launched by the local ISL unit, the full bit remains at logic level 0 until the data is received from the remote ISL unit. In addition, data from the remote line cannot be routed to the local unit before an ACK signal from the addressed device connected to the remote line is transferred to the calling device connected to the local line.

Since the local ISL unit must be in the quiescent state before a line comparison cycle can be executed, it is conceivable that the requested data from the far line can be received before a quiescent cycle occurs . As the remote control logic ensures that the data is not transferred from the remote unit to the local unit before an ACK response appears, the data of the remote line is stored in the remote data file and in the remote address file until an appropriate response has been made.

When the data requested from the remote ISL unit is routed to the local ISL unit, the full bit of registers 92 and 103 goes to state 0 in order to free the transfer path RRQ for another transfer of information.

When an input instruction is sent by the remote and local ISL units to the local communication line, the local unit applies the channel address fixed in the rotary switch 140 to the multiplexer 138 so that this address is then applied by the transceivers 141 to the local communication line. In response to this address, the local line generates a second line mid-cycle signal (BSSHBC signal) and a device address. The BSSHBC signal is received by the transceiver 90 and the device address is received by the transceiver 98. The address is compared in the comparator 99 with the identification code of the local ISL unit. If there is an equivalence, the comparator 99 signals the fact to the local control unit. This then generates an ACK signal which is launched on the local communication line. It is understood that all the second line mid-cycles give rise to an ACK response and not to a WAIT or NAK response. The data of the local line are immediately stored in the registers 92 and 103. A local RRS cycle is then queued by the local control logic, and when the cycle is started, the information stored in the data register 92 is routed through register 121 and line 117 to input II of data multiplexer 129. Its output is applied to transmits5

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output transceivers 139. During a transfer cycle, the information contained in transceivers 115 and 139 is applied to the receivers of the remote ISL unit. When the information from the remote ISL unit is received at the receiver 116 in response to a request from a device connected to the local communication line, the address of this device stored in the data register 92 is applied to the input II of the multiplexer 111, then at the input 12 of the transceivers 123 to then be applied to the local line. The data from the remote ISL unit is applied by the line 117 to the input II of the multiplexer 129 and to the input 13 of the multiplexer 138 so as to be finally applied to the transceivers 141.

Memory test instructions in transfer mode are memory requests that use the internal operation restart path in the ISL unit to check a remote memory before responding to a local device. The associated data paths are identical to those of a local MRQ cycle except that the address is found in the memory reference register 126. The other bits 10 to 23 are received from the address register 103 by means of line 105 and applied to input 12 of transceivers 115. Bit 23 is the memory address translation bit for the test instruction. It is understood that the inputs 12 and 13 of the transceivers 115 are multiplexed. Thus, during the local ISL cycle, the address is supplied by the memory reference register 126 and the file register 103 to the transceivers 115. The data extracted from the data register 92 are applied by the transmitter 121 and the data multiplexer 129 to transceivers 139. No translation takes place in the remote ISL unit. The other operations of the remote ISL unit during the test instruction are the same as for a normal input / output cycle.

Before describing the passage of communication line interruptions in ISL units, it may be useful to describe in more detail the central processor channel number conversion. In addition to the channel number recognition function, an ISL unit performs conversion of the channel number to a central processor channel number in the range of 000lfi to 00F16. In the architecture of a central processor, the central processor channel number determines the location of the reserved memory on a line. Channel 0 uses locations 0 to 255, channel 1 uses locations 256 to 511, etc. Normally, the central processor with the lowest priority level is assigned to channel 0, and the processor with the next priority level is assigned to channel 1. When the same channel number assignments occur for more than one line , the channel numbers must be converted to avoid conflicts.

Fig. 13 illustrates the flow of channel number recognition and translation information for two cases. The first case concerns a line cycle request initiated by a local communication line, the second case concerns a local response to a remote line cycle request. In the first case, a destination channel number is applied by the address line 96, according to the format indicated in 156, to the selective access memory 142 and to the destination conversion selective access memory 131. The memory 131 contains activity bits indicating whether a local ISL unit will accept a particular channel number. A channel number conversion table is stored in two 16 x 4 bit selective access memories, a memory in the local ISL unit and a memory in the remote ISL unit. The memory located in the local ISL unit is called memory for converting destination channel numbers, for example memory 131. The memory located in the remote ISL unit is called memory for converting source channel numbers, for example memory brief 113.

In the second case in which a local response is made to a remote line cycle request, a source channel number is applied by the data line 91 to the memory 113 of the remote ISL unit.

Each ISL unit also contains a channel number selector. The local ISL unit comprises a channel selector 157 and the remote unit comprises a channel selector 158. The selected channel numbers can either be untranslated channel numbers for channel numbers of devices other than central processors, or channel numbers translated for the central processor channel numbers. A translated channel number is selected whenever one of the following three conditions is satisfied: 1) the central processor channel numbers on the address line are translated by the destination conversion table, (2) the central processor channels that are on the data line during central processor to central processor interrupts are translated by the source conversion table, and 3) the central processor channel numbers that are on the data line as part of 'an output interrupt command instruction are translated by the source conversion table, except when they are intended for the ISL unit.

The formats of the destination and source channel numbers applied by the remote ISL unit on the remote communication line are illustrated at 159 and 160 respectively.

There are four cases in which a central processor channel number translation occurs. In the first case, a device connected to a local communication line can try to interrupt a central processor connected to a remote communication line. The local ISL unit then launches a local operation restart request cycle when it detects an activity bit in the addressed cell of the memory 142, if the location 0 of the files 92 and 103 is empty. The interface output control devices 139 are loaded from the data multiplexer 129, the input II of this multiplexer receiving the data from the transmitter register 121. The bits 0 to 13 and 118 to 23 of the output control devices 115 are loaded from the address register 103 while bits 14 to 17 are loaded from destination memory 131. This in turn is addressed by address register 114 receiving bits 14 to 17 from registers 103.

A second case is that in which an input / output instruction intended for a device connected to a remote communication line comprises a function code of 03. Such a code identifies an instruction to control output interruption.

During a remote RRQ cycle, bits 6 to 9 on line 117 are applied to address memory 113 through register 136. The output of memory 113 is applied to local line through multiplexer 137, the multiplexer register 138 and the transceivers 141. The output of memory 113 therefore replaces the data bits representing a central processor channel address in the interrupt control information intended to be applied to a device connected to the remote communication line.

In the third case, the information flow is identical to that of the second case, except that the memory 113 gives the source central processor channel address in the given area of a local processor / remote processor interrupt instruction. The area given in the interrupt instruction contains the address of the interrupt source and the interrupt level.

The fourth case occurs when an input / output instruction intended for a device connected to a remote communication line contains a function code of 02 which identifies an input interrupt command instruction. During the local RRS cycle in the remote ISL unit, which is generated in response to a second line half cycle initiated by the addressed device connected to the remote communication line, data bits 6 to 9 of register 121 are applied via address register 114 to memory 131. The output of this memory is loaded in bits 6 to 9 of the interface control devices 139. Bits 6 to 9 represent the address of a remote central processor to be suspended.

Returning to the passage of the input / output instructions in the ISL units, it is understood that an interrupt is a cycle generated by a central processor or a peripheral control unit, and launched towards a central processor. More specifically, during a

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BSDCNN cycle, the address received from the local communication line by the transceivers 98 is presented to the channel address register 101 in order to address one of the 1024 locations of the memory 142. If the output of this memory changes to a logic state 1, the local ISL unit of FIG. 8 becomes an agent for the BSDCNN transfer cycle. In particular, the central processor addresses occur between positions 00 and 0F of the rotary switch. When the output of memory 142 goes to a logic state 1 and when the six higher order bits 0 to 5 of the address on line 96 are 0, the slave device is a central processor. As such a case appears in a line cycle other than a second line half cycle, the cycle in question is an interrupt cycle. Thus, if the local ISL unit receives the address of a central processor for which the ISL unit becomes an agent, the line cycle must be an interrupt cycle. During an interrupt cycle, the addresses of the central processors are convertible.

When it is determined that the local ISL unit should become an agent for an interrupt cycle, the control logic of the local ISL unit waits for a next RRQ cycle (operation retry request cycle). When the local ISL unit begins such a cycle, the remote ISL unit receives an address and converted data from the local ISL unit. The converted address is applied to the remote communication line to interrupt the addressed central processor. This responds with an ACK or NAK signal. These signals are sent directly to the local ISL unit via comparator 93 as described above. If the local ISL operation restart path is occupied to service a previous instruction, an interrupt cannot be processed. The ISL unit then sends a NAK response signal and generates an interrupt recovery instruction for the local line when the previous instruction is completely executed. The local line can then initiate an interrupt request to the adjacent ISL unit. If the interrupt did not result in a NAK response, then the interrupt prevents a central processor from acquiring other line cycles. In the case of several central processors, an ISL control instruction called restarting of operation NAK, is launched to realize the situation in which a central processor having a high priority level initiates a request after a central processor having a level of lower priority has acquired a line cycle waiting for a response. The response to the instruction to restart operation NAK temporarily satisfies the central processor having the higher priority level to allow the central processor having the lower priority level to complete its task. This organization prevents a blockage which could freeze the communication path between the communication lines.

There are two central processor input / output instructions by which a central control processor identifies for a peripheral control unit the address of a central processor to be interrupted and the priority level of the interrupt. The two instructions are the output interrupt control instruction and the input interrupt control instruction. These instructions must be translated if the central control processor is connected to a communication line and when the peripheral control unit is connected to another communication line. The source conversion memory 113 and the destination conversion memory 131 provide the conversion of the interrupt control information. The paths for the conversion data streams are the same as those described above for cases two and four.

The description of the operation in information transfer mode of the ISL unit ends in FIG. 8 by the description of the operation of the other devices used during the data transfer. For this purpose, it should be noted that the same devices can have other functions during the configuration mode of the ISL unit. The function decoder read-only memory 102 decodes the instructions of the local communication line intended for the ISL unit appearing in bits 18 to 23 of the address present on the line, 96. Such instructions can be received during the transfer information and during configuration mode. During information transfer mode, the instructions may contain the input status, the input identification code, the reset / interrupt timer mask, and the output command words. All other instructions on the line are answered in the configuration mode, as discussed below.

Table 6 is a decoding table for the read-only memory 142.

The mode command register 135 is loaded during the execution of a command word which will be described later in order to indicate an operation either in information transfer mode,

either in ISL unit configuration mode. The timing and status logic unit 133 includes a control timer internal to the ISL unit, a timeout unit for input / output, a timeout unit for the ISL line cycle, and a unit for exceeding the time allocated to the communication line cycle that is encountered only when an ISL unit is connected to a communication line to which no central processors are connected. The rhythm units collectively validate the ISL unit in order to be transparent in the operation of the communication lines. The logic unit 133 also includes status bit generators indicating the operating mode of the ISL unit, the clocks which are enabled, the presence of an interrupt, the type of interrupt, etc.

The interrupt channel register 132 and the interrupt level register 134 are loaded during an output interrupt control command to the ISL unit. The registers 132 and 134 are used by the ISL unit during an interrupt generation.

The interrupt channel register 132 is a four-bit register indicating the address of the central processor to be interrupted. The interrupt level register 134 is a six-bit register which indicates the priority level assigned to the interrupt. A central processor connected to a communication line can read the interrupt level in order to control the progress of the software internal to the central processor.

When a central processor must be interrupted, the output of the register 132 is applied to the input 12 of the address multiplexer 112. The output of the latter is transmitted through the multiplexer 111 and the transceivers 123 in order to provide the address of the central processor which is to be interrupted. For this purpose, bits 6 to 9 of the address line are overplanted with four bits coming from register 134. The output of this register is applied to input 12 of data multiplexer 129 and from there to bits 10 to 15 of the data multiplexer / register 138. Bits 0 to 9 of the multiplexer / register are supplied to the rotary switch 140 in order to signal to an interrupted central processor that the ISL unit is the unit which caused the interruption.

In response to a mask address instruction which will be described later, the counter 118 and the control register 108 are loaded with the address and the write validation signal for each selective access memory. An output mask data instruction loads the translation data into the locations of the translation memory addressed by the output mask address instructions.

The cycle generator 146 includes decision control logic for selecting the operation cycle and for generating time signals to control the operation of the ISL unit during the selected cycle. The cycle generator receives two input signals. The first is a remote cycle signal received from line 143 from the remote ISL unit. The second input signal is the 2D0 file register activity bit received from line 144 to indicate a local ISL cycle request. In response to these two input signals, the generator 146 produces time signals to control the operation of the ISL unit.

The input / output load register (IOLD) 127 is loaded with the translated address of the memory module when an input / output load instruction is sent to a controller. The instruction includes two sub-instructions: the memory address and the

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range of memory. The memory address part requires a memory translation. Thus, the translation bits of the selective access memory 125 are loaded into the register IOLD in response to such a loading instruction.

During the description of the operation of an ISL unit in response to an IOLD instruction, the memory locations will be designated by the addresses of the memory modules. Module addresses are bits translated from a memory address. A local memory unit has 32.0K bits of memory and includes four modules of 8.0K slots. A local memory unit therefore responds to module addresses 0,1,2 and 3. In the preferred embodiment described, the remote local communication lines have memory units of four modules each. In addition, local and remote ISL units are considered to provide visibility to each line of communication. Thus, each line has access to eight memory modules.

When a central processor connected to a local communication line instructs a peripheral control unit connected to a remote communication line to communicate with a memory module in connection with the remote line, the local central processor initiates an IOLD instruction to the remote device control unit. This instruction designates a memory module address having a higher level than the address of any memory module available on the local line. The local ISL unit responds to a channel activity bit in memory 142 corresponding to the remote device control unit and uses address bits on bits 0 to 7 of the address line 96 and the bit lines 0 and 1 of the data line 91 in order to address the translation memory 125. In the location addressed in the memory 125, the converted address of the remote peripheral control unit is located stored. This converted address is transferred to the IOLD register 127 in order to be transferred to the remote ISL unit during a request to retry RRQ operation cycle. Receiving the translated address, the remote device control unit has direct access to the remote memory module.

In the event that a local central processor instructs a remote peripheral control unit to communicate with a local memory module, the local processor initiates an IOLD instruction to the local ISL unit. This unit accepts the instruction and uses the 24-bit address present on lines 91 and 96 in order to address the random access memory 125. The output of this memory is stored in the IOLD register 127 and sent subsequently to the remote device control unit as described above. The remote device controller in turn addresses a memory module having a higher level address than the address of any memory module connected to the remote line. The remote ISL unit is configured to convert the memory module address provided by the remote device control unit to a memory module address on the local line with which the remote device control unit is to enter in communication. The only difference between an IOLD instruction and a current input / output instruction resides in the source of the signals applied to the input of the transceivers 115. In an IOLD instruction, bits 0 to 9 are supplied by register 127 instead of be it through register 126.

The IOLD instructions are accepted by an ISL unit each time they address a channel number which is recognized by the channel mask memory 142. The ISL unit performs a translation of the address part of the instruction. The format of the instruction is shown in Table 7. The translation applies to the 10 most significant bits of the address contained in bit positions 0 to 7 of address line 91 and in bit positions 0 and 1 of data line 96. The 10 most significant bits of the address in the IOLD instruction are replaced by the content of the location addressed in the address translation memory 125.

During the initialization of the ISL unit, the memory 125 is loaded with all bits 1. The software of the central processor connected to a communication line must simply load the specific locations in this memory which are supposed to be addressed by the IOLD instructions . If an IOLD address falls outside of the designated locations, it is translated into an address between 8.0 million and 8.0 million minus 8.0K words. As long as the addressed memory is not used with a system containing an ISL unit, any programming error leads to a nonexistent resource state signaled by an input / output controller.

When configuring an ISL unit to process IOLD instructions, two cases must be considered. In the first case, a controller consults a memory module connected to the remote line in response to an IOLD instruction launched on the local line which refers to a memory module of the local line. The address translation location in memory 125 corresponding to the local memory module must be loaded with the most significant bits of the module of the remote line. The controller then searches for the IOLD memory address on the remote line.

It is understood that an activity bit for the remote memory module in the memory 125 has no effect on the IOLD address conversion. If the addressed location contains an activity bit 0, the memory physically exists on the local line. If it is a bit 1 which occupies the slot addressed, the memory module is visible to a central processor connected to the local line but it is physically located on the remote line.

In the second case to be considered, a remote controller consults a memory module on the local line in response to an IOLD instruction on the local line. As the memory module is actually on the local line, the memory 125 produces an activity bit 0. It can be seen that in this case two address translations are required. A first translation to transfer the IOLD instruction to the remote controller and a translation to allow the remote controller to have access to the local memory.

In ISL unit configuration mode, the ISL unit responds to a total of nine input / output instructions which transfer data to or from an ISL unit. These input / output instructions are shown in Table 8. No data transfer between communication lines occurs during configuration mode. On the contrary, the ISL units are charged during this mode in order to establish communication between the lines during the information transfer mode.

In the intersystem link unit there is an active / passive state switch which will be described later with reference to FIGS. 14. This switch controls the visibility of the ISL unit to the configuration instructions. The effect of the switch on the state of acceptance by the ISL units of the instructions of the local and remote lines is shown in Table 9 and described below. In the active state, the ISL unit responds to any configuration instruction received during the configuration mode. If the ISL unit is in the passive state, it responds only to the selected configuration mode instructions. Thanks to the passive active state switch, the local and remote ISL units can be configured from a line or from independent lines.

In the description which follows, a cycle generated from a communication line will be called "local cycle". A cycle generated by the interface between intersystem link units will be called "remote cycle". When a line instruction is sent to an ISL unit, the ISL unit detects its address in comparator 99 and decodes a six-bit function code (on line 96) in read-only memory 102. The output thereof is retained in an output register for internal use. The address comparator 99 sets the activity bit 2D0 and the full bit to state 1, thus launching a local RRQ cycle which is used to control the data flow for all the ISL instructions. The RRQ cycle activates the function code decoder 106. When the readout memory output bits 102 are applied to the decoder 106 via the line

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at address 105, one of the sixteen possible output conductors is activated to indicate the specific instruction to be executed.

ISL instructions cause one, two, or three internal ISL cycles to start. These local input or output instructions initiate a single RRQ cycle during which data is loaded into a specific register or read into a specific register. The input instructions also give rise to the generation of a second half-cycle (BSSHBC) by the local ISL unit intended for a master central processor which has requested data. The output instructions from remote ISL devices produce two cycles. The first cycle is a local RRQ cycle during which data from the data register 92 is transferred to the remote ISL unit as in a normal RRQ cycle. In addition, the information on line 105, which contains the function codes provided by the read-only memory 102 and other specific function code information is presented to the control device 115 in order to be transferred to the remote ISL unit. The second cycle occurs in the remote ISL unit as a remote RRQ cycle during which data is stored in the same manner as the information appearing on lines 105 and 117 of the local ISL unit.

Remote ISL device input instructions require three cycles. The first cycle is the same as for the exit instructions. The second cycle is the same as for the output instructions except that the data are read in specific registers and presented on a data line corresponding to line 117 of the remote ISL unit, and transferred to the local ISL unit by through interface control devices corresponding to the devices 139. In the local ISL unit, data is received by the data receivers 116 during a remote RRS cycle. The RRS cycle is generated to transfer the data of the local line through the data multiplexer 129 and the multiplexer / register 138 to apply them to the data transceivers 141. The address is extracted from the data register 92 and applied by through the multiplexer / register 111 to the transceiver 123.

As described above, each ISL unit has a channel number which is used when a central processor addresses an ISL link unit. When an instruction must pass through an ISL unit, the central processor destination channel number is used. A central processor connected to a specific line can address the local ISL unit on the local line or it can address the remote ISL unit through the local ISL unit. The channel numbers of each ISL unit are determined by dip switches. In principle, the ISL instructions in Table 8 apply to any ISL unit and can be launched from any line. The active / passive switch in each pair of ISL units allows or inhibits the possibility of this ISL unit being controlled from the local line.

A first instruction which is described is an output command instruction having a function code 01 as shown in table 8. The given area of the instruction word gives the mode command as indicated in table 10 in which an X indicates that 'a binary state 0 or 1 can occur. There are two test mode bits: bits 2 and 3. One bit indicates the memory reference mode and the other bit controls the response of the ISL unit to a local line cycle or a remote line cycle.

System initialization is controlled by bit 0 of the instruction. The bit is read by the generator 94 in order to empty the selective access memories of the ISL unit. Bits 0 and 1 of the instruction put the ISL unit into a transfer state of information other than data when servicing existing requests. Thus, if the ISL unit has agreed to act as an agent for a communication line cycle, the ISL unit will continue to serve this request until all of the communications required to satisfy this request have been completed. Any other data transfer request that appears after the start of the configuration mode instruction is ignored. The instruction places the ISL unit in a mode that allows it to service current communication line requests. In the case of a system comprising several central processors, the NAK / restart logic can be activated by bit 4 of the control word in order to send a negative acceptance response NAK to a central processor having a higher priority level in order to allow a data transfer in the ISL unit to continue for a central processor having a lower priority level.

The control word receives the highest priority level in the ISL system because it controls the operating mode. It can be launched only when the ISL unit is in an active state. When in a passive state, the ISL unit does not accept the output command instruction. This requires two cycles, as described above, which load the mode control register 135 both in the local ISL unit and in the remote ISL unit.

The output interrupt command instruction having a function code 03 loads the registers 132 and 134 with interrupt data during the configuration mode when the unit is in an active state only. If the ISL unit is in a passive state, this instruction is not accepted. The exit interrupt command can be issued to the local ISL unit or to the remote ISL unit and requires one or two cycles as described above.

This instruction comprises sixteen bits which identify the central processor channel number and the level of interruption that the ISL unit will have when it interrupts the central processor. The instruction has the following format:

0 5 6 9 10 15

To ignore

Channel number

Interrupt central processor level

Register 132 is loaded with the four-bit address of a central processor that the ISL unit must interrupt when an interrupt condition is encountered. The six most significant bits of a central processor address are always bits 0. The register 134 is loaded with a six-bit area which designates the level of interrupt that the interrupted central processor uses to define the level of interrupt priority.

The timer reset instruction, function code 27, commands the reset of all timer status bits to 0. This instruction also commands the validation of the rhythm of the local or remote sequence controller, the validation and the blocking of the input / output and restart timing, and the validation or the blocking of the remote ISL interrupts. The memory rhythm is always enabled. When one of the rhythm errors appears, the rhythm must be reset to zero by the reset rhythm instruction.

As previously described, the output timer data and the status information of the output timer are loaded into the logic unit 133 which thus indicates the status of each operation of the timer.

The timer reset instruction can also be used to turn the sequence controller timer on and off during data transfer mode and configuration mode or during active or passive states. If the rhythm is not sampled within a predetermined period of time, an interrupt having a high priority level is processed within the interrupt architecture of a central processor. In the event that the flow of the logical decision process is unable to leave a central processor control loop, the rhythm of the sequence controller is validated to provide an output means. In the preferred embodiment described here, there is provided a local sequence controller timer and a remote sequence controller timer. Each rhythm and the interrupts emanating from this rhythm can be controlled by the central processor. The reset timer can be assigned to either the local ISL unit or the remote ISL unit, and it can generate one or two

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cycles as previously described. The format of the reset timer instruction is defined in Table 11.

The output mask address, function code 08, and the output mask data instruction, function code 11, initiate an ISL unit configuration by writing to the memory address conversion memory 125, the memory channel mask 142 and the central processor conversion memories 113 and 131.

The output mask address instruction can only be sent to an ISL unit when it is in the active state and only to the local ISL unit. Thus, a single cycle is necessary as described above, the output mask address instruction loads into the counter 118 the address and the write validation information relating to the specific conversion memories in which data presented during an output mask data instruction must be written. More particularly, the counter 118 is used to address the memory 125, the memory 142, the central processor destination memory 131 and the central processor source memory 113 during the configuration period of an ISL unit. The address of the memory location to be modified is stored in the counter 118 and applied to the memory control register 108. This is a three-state device which is linked to the address line 105. The contents of this register are used to address the address conversion memory 125, the channel address registers 101, the central processor address register 114 and the central processor address register 136. The data appearing on the data line 117 are thus written in the addressed locations.

The output and input mask data instructions operate the counter 118. By the action of the counter, continuous locations in the random access memories can be addressed without having to reissue output mask address instructions. The counter facilitates this operation by controlling sequential addressing from a starting location.

When the output mask address instruction is sent to a local ISL unit, the data received from the local line and stored in the data register 92 is applied by the register 121 and the line 117 at the input of the counter. from memory 118.

As described above, ten bits of a memory address are used to address 1024 memory locations via a memory address multiplexer 100 and a channel address register 101. The thirteen bits applied to counter 118 include an address representing one of the 1024 locations in memories 142 or 125, and a validation signal to authorize the writing of data in any or all of the translation memories.

The four least significant bits are used to address the memories 311 and 111. The bits 3,4 and 5 of line 117 represent the write validation signals.

When bits 3, 4 and 5 of line 117 are applied by counter 118 and control register 108 on line 105, they become address bits 5, 6 and 7, respectively. Address bit 5 authorizes writing to memories 131 and 113. Address bit 6 validates the channel mask memory 142 and address bit 7 validates the memory mask memory 125. We thus see that in response to the output mask address instruction, the ISL unit stores in the counter 118 the addresses of random access memories in which data must be written. For this purpose, bits 0 to 15 of the data register 92 are stored in the counter 118. Among the sixteen bits, ten represent the addresses of the memories and three bits are write command bits.

The output mask data instruction, which can be issued only during a configuration mode while the ISL unit is in the active state, presents data to be written to the location addressed by the address instruction output mask. The output mask data can be sent to the local ISL unit or to the remote ISL unit and requires one or two internal cycles as described above. In response to this instruction, the data stored in the data register 92 is sent to the data line 117 via the register 121. The function code is provided by the read-only memory 102 as described above, and it is decoded by the function code decoder 106. The output of this decoder instructs the local control logic s to route the data present on line 117 to one of the memories 142, 125, 113 and 131 for a write operation. The starting address of the location in the identified memory, in which data must be written, is identified by the counter 118. The address is applied on line 105 via the control unit io memory 108 in order to address one of the cells of the identified memory. Bits 5, 6 and 7 at the output of counter 118 become write validation signals for memories 131, 113, 125 and 142.

The specific sequencing of the write operation is controlled by the cycle generator 146. Write pulses are generated for each validated memory of the local ISL unit. Data can thus be written in one or all the memories.

The local ISL unit as well as the remote ISL unit can be loaded by an output mask data instruction. The output mask address instruction, on the other hand, is only applied to a local ISL unit. Thus, if data has been written to a local memory from location 0, another output mask address instruction will not be issued for writing to remote memories from location 0. Only an output mask data instruction issued for the remote ISL unit is required.

It can therefore be seen that the address mask and output mask instructions work in pairs in order to load the four configuration memories of the ISL unit. The format of the instructions so to load the memory address conversion mask memory 125 is explained below:

35 Mask output address

Data mask output

40

The output mask address instruction establishes the starting location of the memory counter 118. The output mask data instruction loads an amount defined by 10 bits into a em

45 previously designated placement, and it activates the counter. To load the next consecutive location, only the output mask data instruction must be issued. The memory activity bits (Hm) are all initialized to 0 and the memory mask data is initialized with bits 1.

50 For loading the channel mask memory 142, the instructions have the following formats:

j5 Address mask output

Data mask output

The output mask address instruction sets the starting location of a memory counter 118. The output mask data instruction loads the channel activity bit (HC) to cause the ISL unit responds to this channel number. In addition, 65 the output mask data instruction operates counter 118. To load an HC bit in a subsequent consecutive location, only the output mask data instruction must be issued.

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To ignore

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To ignore

Mask address

0 3 4 5 6 15

Channel number

Address

In order to load a central processor conversion memory, memory 131 or 113, the address and output mask data instructions have the following formats:

0 2 3 4 11 12 15

Address mask output

MBZ

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MBZ

PC translate from

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Data mask output

PC translate up

To ignore

The output mask address instruction identifies a central processor channel number 15. The output mask data instruction defines the value into which the channel number is converted when it traverses the ISL unit. Furthermore, the output mask data instruction actuates the counter 118 to increase its content to the next consecutive value. 20

The entry instructions are now described. The input interrupt command instruction, function code 02, is similar to the output interrupt command instruction. The instruction requires one or three cycles as described above for the local and remote ISL instructions, and the ISL unit must be in configuration mode and in the active state. However, instead of loading the interrupt channel register 132 and the interrupt level register 134, the instruction routes the data to the internal data multiplexer 129. The data is then routed through the transmitters. receivers 138 to data transceivers 301. The contents of data register 92, which contains the address of the master device, is routed to address transceivers 123 through the multiplexer / register d 'address 111.

The input interrupt command instructs the ISL to apply the contents of the interrupt registers 132 and 134 to the data multiplexer 129. The register 132 provides four bits which indicate a channel number of central processor, and register 134 provides six bits indicating the interrupt level. The instruction format is the same as for the output interrupt command instruction.

The input mask data instruction, function code 10, controls the reading of the content of the memory cell which has been addressed previously by an output mask address instruction. More particularly, the local control logic reads 45 the address loaded into the counter 118 and initiates a reading of each of the memories 113, 125 and 142. A bit of channel mask is read in the memory 142, ten bits of translation of memory and one activity bit are read from memory 125, and four central processor definition bits are read from memory 131. A total of sixteen bits are therefore applied by the transceivers to either the local communication line. , or to the remote communication line. The input mask data can be sent to the local ISL unit and the remote ISL unit, which gives rise to one or three cycles as described above. 55

The input mask data instruction further provides the possibility of further increasing the counter 118 when it has been loaded to an initial value. The location 0 of a random access memory is first read, followed by 1024 input mask data instructions extracted from the 1024 locations. Like the 60s

memory data must be a hex code 03FF when initialized, any other data indicates that a translation bit or activity bit occupies the address in memory. The ISL unit must be in configuration mode and in the active state. 65

The format of the input mask data instruction is given below in comparison with the format of the output mask address instruction:

Input mask data instruction

The output mask address instruction sets the starting position of a counter 118 to state 1. The input mask data instruction supplies the content of the addressed position and advances the counter. To read the next position, only the input mask data instruction must be issued. The input mask data instruction returns the content of all configuration memories at the same time. For a specific address, the corresponding memory translation address, the memory activity bit, the channel activity bit and the translation channel number of the central processor are returned. Since the central processor channel number translation memory has only sixteen locations, an output address of 0 returns the same position as if it were 01016,02016, etc.

The input status word instruction, function code 18, controls the reading of the status bits stored in the logic unit 133. The state of the timers, the occurrence of pending interrupts and the state ISL unit logic can thus be determined. The status word instruction can be issued either during data transfer mode or during configuration mode, and regardless of the status, active or passive, of the ISL unit. The status bits are defined in Table 12.

Another input instruction is the input device identification instruction which can be issued during the information transfer mode or during the configuration mode of the ISL unit, with this unit in the active state. or passive. The identification of the ISL unit is a fixed number which is identical for each ISL unit regardless of the address. The instruction is unique in the sense that only the local identification is read, regardless of whether the local ISL unit or the remote ISL unit is addressed. If the remote ISL unit is not electrically connected to the local ISL unit, the identification number that will be read on the local line will be, for example, a hexadecimal number 2400. If each of the ISL units is electrically connected and when powered up, the identification number can be, for example, a hexadecimal number 2402. The input device identification instruction can thus be used for a diagnostic programmer to determine whether a local ISL unit and / or a remote ISL unit is connected.

The operation of the ISL unit in test mode will now be described. In an output command word instruction, there are two test bits as described above. Bit 2 is called the total test mode bit and bit 3 is called the remote test mode bit. When bit 2 is at state 1, each of the ISL units is put into test mode. When bit 3 is at state 1, only the remote ISL unit is put into test mode.

Operation in test mode uses one of two logical paths. When bit 2 (total test mode) is at state 1, the logical path used is a round trip memory loop. A round trip logic path for an input / output device requires setting the local test mode bit and the remote test mode bit to 1.

In the round trip memory loop, the local ISL unit and the remote ISL unit must be configured to work on addresses initiated by the local communication line. More particularly, when a central processor initiates on a local communication line a memory reference instruction in which an address other than a local memory address is indicated, the local ISL unit transfers a translation of this information to the unit

Central processor translation channel number

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ISL remote. If the specified address is configured in the remote ISL unit, the latter returns the information to the local ISL unit. A round trip loop is thus established in order to convert the information back into the local ISL unit in order to apply it to the local line. It is understood that even when a memory address does not exist on the local line or the remote line, the local and remote ISL units can be configured to recognize the memory address and act as an agent for the cycle. associated memory. The ISL units then send ACK acceptance signals in response to the memory address as described above. io

An important feature of the test mode is that the local and remote ISL units can be checked dynamically without interrupting the operations performed by the system on a remote communication line. No device connected to the remote line is used, and only one line cycle is lost. Another feature of this test mode is that no running task is interrupted before being completed.

When a test loop has to be established with an input / output device, the same logical paths as for the data are used. The ISL cycles which are generated in the ISL 20 units are however different. In addition, the channel address register 101 and the channel mask memory 142 are controlled in place of the memory address register 100 and the memory address conversion memory 125 which have been used during the memory test. In operation, an input / output instruction is issued for a channel number. As the channel number is carried by an input / output request and not by a memory request, the channel number is not convertible. Instead, the channel number which should not refer to channel numbers on the local line or the remote line is converted to a memory address on the loop going to the local communication line.

For a read or write operation in the local memory, the memory request is transferred to the remote ISL unit via the local ISL unit, then returned to the remote unit through the ISL unit. local. It is understood that if the selected channel number is either on the remote line or on the local line, an acceptance signal ACK is generated outside the ISL units. Thus, a channel number which is not recognized by the local line or by the distant line must be applied to the channel mask memory 142. Like the selective access memories 40

can be configured to recognize the channel number, the channel is transferred from the local ISL unit to the remote ISL unit and then returned to the local ISL unit. The channel number with the remainder of the address must be converted to an actual memory address on the local line in order for a successful test to be detected. 45

The test mode bits having the value suitable for initiating an input / output loop test also carry at state 1 the memory reference line in the local control logic. When the information on the loop from the remote ISL unit is received in the receivers 104 and 115 and loaded in the multiplexers 111 and 138, so the address contained in the channel number becomes a memory address. A memory location on the local line can thus be read or written to carry out a logical test. A distinction between the memory loop test and the input / output loop test is that during the memory loop test, only the 55 memory request and memory buffer response cycles are used.

During the input / output loop test, the dunning request and dunning response cycles are used. Memory cycles are always confirmed while input / output cycles are not initially confirmed. Instead, a wait response is issued before a local retry request cycle is performed in the remote ISL unit. In response to the establishment of a local RRQ cycle in the remote unit, a remote RRQ cycle is generated in the local ISL unit. When the remote RRQ cycle is generated in the local ISL unit, the input / output instruction is converted to a memory address from the local memory and transferred from the local ISL unit to the remote ISL unit. .

When the comparator of the remote ISL unit, corresponding to comparator 99, detects an equivalence, the remote ISL unit transfers to the local ISL unit an ACK acceptance signal. When the line comparator 93 of the local ISL unit detects an equivalence, the acceptance signal ACK is transferred to the local line. The central processor connected to the local line launching the stimulus request is thus satisfied and stops launching the stimulus requests. It is clear that two loop tests can be carried out in order to verify the logic of the local ISL unit and the logic of the remote ISL unit. A test is made in response to a request for reminder and another test is made in response to a request for memory.

Returning to the ISL unit configuration mode, it is understood that an ISL unit is configured by the use of input / output output instructions. More particularly, the command instruction performs the loading of the mode command register 135, the interrupt command word performs the loading of the interrupt channel register 132 and of the interrupt level register 135, and the instruction for resetting the timer to 0 loads the logic unit 133. In addition, the output mask address instruction performs the loading of the counter 118 and of the command register 108. The given mask mask instruction output is used to load the data into the selective access memories of the ISL unit. The data loaded into the ISL unit during a configuration of the unit can be checked by using the input / output input instructions.

Each ISL unit includes 5 timers which will be described with reference to Figs. 14, these timers used to detect and lift stop states. The timers are reset to zero by the reset instructions described above. If a second line half cycle from memory does not arrive within a predetermined period indicated by a memory stop timer, the ISL unit completes a read request cycle by sending the requesting device a non-data word. valid. In the preferred embodiment described here, the predetermined time period is set to about 6 | aces.

If a second line half cycle is not received from an input / output controller within about 200 ms, for example an input / output unit stop timer sends a signal to control the unit ISL so that it completes an input request cycle by sending to the requesting device a meaningless data word with an incorrect parity and a RED indicator bit at state 1. The stop rhythm is validated by the instruction resetting the timers to 0.

If a local line cycle is not completed within 7 us, an unresponsive response timer issues a signal for the ISL to initiate a negative NAK confirmation signal. It is a service for the line rather than the ISL unit and this signal is intended for configurations in which the line does not have a central processor. The NAK signal produces the same effects as a NAK signal for nonexistent resource and it can cause other actions in the ISL unit if it is involved in the cycle.

A sequence controller timer is provided to facilitate the use of ISL units in redundant systems. Once the rhythm controller is activated by an input / output instruction, the rhythm generator sends a logic signal if it is not reset more frequently than once per second at a rate of 60 Hz.

When the rhythm controller sends a logic signal 1, the local line and the distant line are interrupted. Sequence controller timer interruptions can be blocked by proper adaptation of the reset timers instruction.

The restart stop timer is started when an ISL unit issues a WAIT wait signal following an operation restart and is reset to 0 when a confirmation or negative confirmation signal is sent. If more than 100 ms, for example, has passed and the operation retry cycle is not completed, the ISL unit will not respond to other line cycle requests from an original master device. . The line will exceed the allotted time and the requesting device will be notified of a stop. The rhythm controller is enabled under the command of a reset instruction.

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Each timer controls the logic levels of the status bits, as shown in Table 12.

Each ISL unit includes a status register in logic unit 133. The local status register contains information relating to the local ISL unit as well as a composite status bit representing certain conditions in the ISL unit distant. In the event that the remote interrupt bit in the local state register is in state one, the detailed state is obtained by reading the remote register through the local ISL unit. Three mask bits are produced to block specific interrupt and status conditions. These mask bits are set to 1/0 during the instruction to reset the timers / interrupt mask (function code 27) to 0.

Figs. 14 make up a detailed logic diagram of an ISL unit. It is understood that the logical systems constituting an ISL unit are distributed throughout the unit and share common logical elements. The input and output conductors of these logic elements are connected to other logic elements distributed over the 29 drawing boards forming figs. 14.

In these drawings, the logic elements are designated by a code comprising 3 digits. The input and output signals are identified by a 5-digit code: the first 3 digits designate the logic element that produced the signal, the last 2 digits designate the corresponding output pins of the logic element.

For example, signal 24102 is produced by an inverter 241 (fig. 14B3). It is obtained at the output pin 02. The input signal from the inverter 241 is the signal 24006 produced at the output 06 of the device 240.

Each signal is also designated by a mnemonic code composed of 9 characters: 6 literal characters forming the mnemonic designation, a designator (+) or (-) indicating the state for which: is true, and 2 decimal digits to differentiate the signals having the same mnemonic designation. The sign (+) of a designator indicates that the signal must be in state 1, the sign (0) indicates that the signal must be in state 0.

The following description is a functional description of the ISL unit.

The output signal 25103 is applied to the input of a monostable flip-flop 370 which generates a confirmation signal 37005 and a negation signal 37012. The negation signal 37012 is a pulse of negative pace having a duration of 1.5 ms.

The negation signal 37012 is applied to the clock input of a D 531 flip-flop. This responds to the trailing edge of the negation signal 37012 which is applied approximately 1.5 ms after the leading edge of the line signal under voltage 10535 (fig. 14A) is detected. The output signal 53109 collected at the output of the flip-flop 531 is applied to an input of an EXCLUSIVE gate 290. A reset signal from the master device connected to the local communication line 24305 is applied to another input of door 290. Signal 24305 is the confirmation output of a D flip-flop 243. A reset button for the master device, provided on the control panel, applies to a control / receiver device 242 (fig. 14B) a signal 10407 coming from the connector 104. The device 242 produces an output signal 24214 which is applied to a clock input of a flip-flop 243 (fig. 14L). A signal 93213 is applied to the CD input of flip-flop 243, this signal coming from the remote ISL unit. The signal 93212 ensures that the flip-flop 243 is only set to state 1 if there is no setting of the master device in the remote ISL unit.

The energized line signal 53109 or the master device reset switch 24305 starts a master device reset sequence by setting the output signal 29006 of the EXCLUSIVE gate 290 to state 1.

The output signal 29006 is applied to an inversion controller 468. An inverted output 46808 is applied to a delay line 467 producing a delay of 200 ns. The output signal 46707 is applied to the reset terminal of flip-flop 243. This ensures that a pulse of 200 ns is applied to the logic

ISL in order to execute the reset function regardless of the duration of the line signal to 0 10407 on the line. A resistor of 100 129 129 for delay line 467 is used to form the electrical termination of the signal.

At the end of a 200 ns pulse, signal 46707 sets flip-flop 531 to zero. The negative output of flip-flop 531, signal 53108, is applied to the clock terminal of a flip-flop D 511 in order to put this flip-flop in state 1. Putting in state 1 of flip-flop 511 starts the process internal reset.

The master reset function for the ISL unit is generated by one of four signals. The first signal 24306 is the complementary output of flip-flop 243, this signal being controlled by the local control panel. The second signal 93212 is the master reset signal produced by a remote control panel. The third signal 91612 is produced by an initialization instruction or a power-on state of the remote communication line. The fourth signal is the initialization instruction or a power-up state of the local communication line. Three of the signals are applied to the inputs of a reversing OR gate 734. An output signal 73406 is applied to an input of an OR gate 831. The fourth signal, signal 53109, is applied to the other input of the gate 831. An output signal 83111 from the OR gate 831 is applied to the 4 inputs of a NAND gate 830 which produces the reset signal for the flip-flops and registers. Signal 83006 is inverted by an inverter 448 whose output 44806 is used to set 0 flip-flops and registers. Certain flip-flops and certain registers require confirmation signals while other flip-flops and other registers require the negation signal.

Signal 83006 is applied to the clock terminal of a flip-flop 470. The output signal 47005 of flip-flop 470 starts the master reset sequence. Initially, when the 200 ns 46707 pulse was generated, the 40 ns 46712 pulse was applied to a NAND gate 512. Signal 53109 was applied to the other input of gate 512. The signal 51208 output from gate 512 is applied to an OR gate 469. As the output signal 46908 of the latter is normally at state 1, this output signal goes to state 0 in order to reset the flip-flop to 0 470 when the signal 51208 goes to state 0. The sequence which has just been described ensures that the system is put in initial state after the pulse 46707 of 200 ns is brought back to its normal state 1.

The signal 58109 produced at the output of the JK flip-flop 581 (fig. 14N) is also applied to the input of the NI 469 gate (fig. 14L). This signal 58109 is brought to state 0 in order to reset the flip-flop 470 to 0 when a request to restart an operation is processed. The flip-flop 470 is thus reset to 0 40 ns after the signal 10407 has been received on the line. Flip-flop 470 is restored to state 1 by the leading edge of signal 83006 in order to start the sequence for resetting the master.

The signal 53109 is applied to an inverter 868 whose output 86804 is applied to an input of a control device 870 (fig. 14AB). An output signal 87014 from the device 870 is sent on the remote line to indicate that the ISL logic unit is in the master reset mode. A signal 91612 is received on the remote line by the logical unit ISL and applied to an input of an NI 734 gate to indicate that another unit is in the reset mode of the master. An output signal 73406 from the gate 734 is applied to the other input of the OR gate 831, so that the signal 83111 described above is generated in order to establish alternately in state 1 the flip-flop 470 during the climb. signal 83006.

The reset sequence flip-flop 0 470 is therefore set to state 1 in the local ISL unit and in the remote ISL unit. Signal 47005 is applied to an AND / OR gate 388 (fig. 14V). The output signal 38808 is applied to an NI 608 gate, the output of which is applied to the CD input of a D flip-flop 464. A signal 60408 is applied to the clock input of flip-flop 464, this signal being obtained at the output of an AND 604 door. A signal 17612 is applied to an input of the AND 604 door. The signal 17612 is the output

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of a negated OR gate 176. The signal 38808, which is the output of gate 388, is applied to the input of gate 176.

The clock signal 60408 which controls flip-flop 464, as we have just seen, also controls a flip-flop D of ISL cycle 441. This flip-flop is set to state 1 each time an ISL cycle is produced and the local cycle flip-flop 464 is set to state 1 when the condition which produces an ISL cycle is due to a request from a local communication line. Remote cycle flip-flop 572 is set to state 1 when an ISL cycle is initiated from a remote communication line. When the flip-flop 441 is set to state 1, its output 44109 is applied to the input of a power supply control device 322. The output signal from this is applied to a delay line 374 producing a delay of 125 ns. The various output signals from delay line 374 are used to control the flip-flops during the ISL cycle. In particular, the signal 37411 which is produced after a delay of 50 ns resets the flip-flop 441 to 0. The output signal 44109 is therefore a pulse of 50 ns. When the flip-flop 464 is in state 1, its output signal 46405 is applied to a 4-bit register 490 in order to control the loading of the latter with the input data. The register 490 input signals are the memory request signal 48305, the operation retry request signal 58109, the operation retry response signal 58810 and the memory response signal 35106.

The logic shown in fig. 14V also determines the priority and it also determines whether the local operation or the remote operation will have access to the ISL cycle. The update sequences

0 of the master have the highest priority level although the cycle which executes this sequence has the lowest priority level. However, functions with a higher priority level are controlled to allow the reset operation.

For example, the local operation restart request signal 581Ó9 is generated at the output of a JK flip-flop 581 (fig. 14N). This flip-flop is set to state 1 during the initialization sequence. A signal 83006 is applied to the input S of a flip-flop D 632 which is set to state 1 if the signal 83006 is in state 0. The output signal 63209 is thus brought to state 1. If there is no data on the line, signal 21510 is in state 1. The output of NAND gate 559, i.e. signal 55906, then goes to state 0 and this signal is applied to the input S of flip-flop 581. This is set to state 1. The output signal 58109 is to state 1 and is applied to the input CJ of a JK 584 scale. This is also set to the state

1 during a reset sequence via signal 53108 applied to an OR gate 605. The output signal 60506 is applied to the input S of flip-flop 584, so that it is set to state 1, in order to block any other request coming from the communication line.

The output signal 58109 produced by flip-flop 581 is applied, as indicated above, to the input of register 490 (fig. 14V) and loaded into the register under the control of signal 46405. The corresponding signal 49010 produced at output from register 490 is applied to AND gate 5831 which is one of the four AND gates which define the four basic ISL cycles. These doors 583, 590, 486 and 493 are described below. In this case, the output signal 58306 is selected from the request to restart local operation operation.

During the master reset sequence, a predetermined bit profile is stored in the 1024 addresses of a memory with selective access. The counters 744, 745 and 746 are initially set to 0 by the reset signal 83111 generated by the OR gate 831 as described above. The counters 744, 745 and 746 are then actuated in order to progress by their 1024 positions before being reset to 0. The counting signal is launched by the output 47006 of the flip-flop 470 (fig. 14L) which is applied to an input an NI 908 door (fig. 14Q). The output signal 90812 is applied to the input of an AND gate 740. The local operation restart request signal 90002 is applied to another input of the gate 740. The output signal 74003 is the progress signal count which is applied to an input of an AND gate 747 and the output signal 74711 thereof is applied to terminal +1 of the counter 746. The signal 90002 is generated when the signal 58306 produced by the AND gate 583 (fig. 14V) is applied to an inverter 900 (fig. 14U). The output of the inverter is the signal 90002. An end of pulse signal 37606 is applied to an input of the gate ET 747. The signal of 125 ns 37407 received from the delay line 37415 (fig. 14V) is applied at the input of an inverter 377 whose output signal 37712 is applied to the input of an inverter 376 generating the signal 37606. This 125 ns signal advances the counters 746, 745 and 744 (fig. 14Q) by controlling the output of ET gate 74711. The output signal 74612 is applied to terminal +1 of counter 747 and the carry-over output signal 74512 is applied to terminal +1 of counter 744. Output signals 74603, 74602, 74606 and 74607 of counter 746 are applied to the respective inputs of a register 741. The output signals 74503, 74502, 74506 and 74507 of counter 745 are also applied to the respective inputs of register 741. The output signals 74403 and 74402 of counter 744 are applied to the entries of a register 929. The registers 741 and 929 are three-state registers. These registers are validated by a selection signal 74808 which is applied to the terminals for validating the registers. The signal 74808 is generated by the AND gate 748 when the ISL system is in reset mode of the master. The inputs 53910 and 56108 of the AND gate 748 are at this time in state 0.

The output signals from registers 741 and 929 are signals 92915, 92912, 92916, 92909, 92905, 74105, 74106, 74119, 74102, 74109,74115, 74112 and 74116. These signals are applied to address line bits 5 to 17 of the doors OR 13701,13801,13901,14001, 14101,14201,14301,14401,14501,14601,14701,14801 and 14901, respectively (fig. 14F).

Signals 8-17 with addresses 14001, 14101, 14201, 14301, 14401, 14501,14601,14701,14801 and 14901 (fig. 14R) are applied to input 1 of multiplexers 313, 314 and 315. The output of these multiplexers, the channel address signals 0-9, are applied to the address terminals of a selective access memory 276. During the master reset sequence, the 1024 addresses of memory 276 are therefore consulted since terminal 1 is selected by signal 53910.

Similarly, signals 8-11 with addresses 14001,14101, 14201 and 14301 are applied to input 1 of a multiplexer 472. Signals 12-15 with addresses 14401, 14501,14601 and 14701 are applied to input 1 of a multiplexer 473 and the address signals 16 and 17 are applied to input 3 of the multiplexers 474 and 475, respectively. The multiplexers 474 and 475 receive at their selection input 1 a signal 48112 coming from the NAND gate 481. The signal 48112 is at state 1 at this time, because the input signals 24414, 47006 and 53910 are all at state 0.

The outputs of multiplexers 472, 473, 474 and 475, i.e. 0-9 memory address signals 47212, 47209, 47207,47204, 47312,47309,47307,47304,47409 and 47507 are applied to the address terminals of the memory translation memories 706 to 715 and to the activity bit memory 863.

Signals 14-17 with addresses 14601, 14701, 14801 and 14901 are applied to input 0 of a multiplexer 749 (fig. 14W). Central processor translation address signals 0-3 74912, 74909, 74907 and 74904 are applied to the address inputs of memories 754 and 757. Input 0 of multiplexer 749 is selected, because signal 92806 applied a level 0 at the selection input of the multiplexer 249 and because the signal 59012 applied to the input of the AND gate 928 is at state 0.

The master 47006 reset sequence signal is applied to the inputs of NAND gates 750 to 753. Since the ISL system is always in master reset mode, signal 47006 is in state 0. The output signals 75003, 75108, 75211 and 75306 are in state 1. These signals are applied to the data input terminal of the selective access memory 754. As this is positioned successively on the sixteen locations d address, bits

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0 are entered in each location since the signal is inverted at the input of memory 754.

The input for writing memory 754 is excited by a signal 76003, which is the output of the AND gate 760. The signal 73811 from the AND gate 638 (fig. 14V) is applied to an input of the NAND gate 760. An input from AND gate 638 is the impulse of 60 ns 32502 coming from the delay line. Signal 51105 and signal 47005 are applied to the inputs of a NAND gate 471 (fig. 14K). The signal 51105 authorizes the resetting of memory 754 during a sequence of resetting of the master. The resetting of memory 754 is however prohibited when the reset button is pressed on the control panel. These two signals are in state 1 to indicate a write operation in the memory. The output signal 47103 is applied to an input of an NI 639 door. The output signal 63908, in state 1, is applied to the input of the AND gate 638 (fig. 14V). The output signal 63811, which is in state 1, is applied to the input of the NAND gate 760 (fig. 14W), if the signal 5 with address 13701 is also in state 1. The output of NAND gate 760, that is to say the signal 76003, then goes to state 0 in order to authorize the write operation.

The input channel mask write signal is applied to the write authorization input of memory 276 (fig. 14R). The signal 63811 is applied to an input of a NAND gate 312. A signal 6 of address 13801 is applied to the other input of the NAND gate 312. The signal 63811 is in state 1 as described upper. If the address bit 6 is at state 1, the memory 276 executes the write operation. Signal 47006 is applied to an input of an AND gate 275. Since signal 47006 is in state 0 during the first reset sequence of the master, the output signal 27505 is in state 0. Bits 0 are therefore written in memory 276 at the addresses designated by the address bit 6.

Signal 68311 and signal 7 with address 13901 are applied to a NAND gate 859 (fig. 14S). The output signal 85906 is applied to the write authorization inputs of memories 706 to 715 and 863.

Signal 47006, which is in state 0, is applied to the AND gate 862. Signal 86208, which is in state 0, is applied to the write input of memory 863. Bits 0 are therefore written in all the positions of this memory.

Data signals 6-15 33901, 34001, 34101, 34201, 34301, 34401, 34501, 34601, 34701 and 34801 are applied to the data inputs of memories 706 to 715. As data signals 6-15 are normally at state 1, bits 1 are therefore registered in the 1024 addresses of these memories.

Resistor networks 648, 649 and 650 (fig. 14M) retain data signals 01-15 33401, 33501, 33601, 33701 and 33801 at level 1 during the reset cycle, no data being received from the communication line via receivers 232 to 238 (fig. 14B).

Signal 86108 is applied to OR gates 759, 737 and 730 (fig. 14Q). The output signals 65906, 73706 and 73003 are applied to the input of the register 929. The output signals 92912, 92915 and 92916 are applied to terminals 137, 138 and 139 (fig. 14F) wired in OR function. The output signals 13701, 13801 and 13901 are in state 1 in order to authorize the write operation. The memories with selective access are initialized during the operation setting to 0 of the master as described above.

We now refer to FIG. 14V. Signal 37406 is to be applied to the input of an inverter 327 whose output 32712 is applied to the input of another inverter 326. The output 32610 of the latter is also applied to the input of an inverter 327 The output 32712 of the inverter 327 is applied to a NAND gate 323. The other input of this gate is the end of pulse signal 37712.

The flip-flop 470 of fig. 14L remains in state 1 until the address 1024 of the various memories has been emptied as described above.

We now refer to FIG. 14Q. When the content of counters 746, 745 and 744 reaches 1024, the signal 74406 at the output of counter 744 is in state 1. The signal is applied to the input of an inverter 316 (fig. 14L). The output signal 31608 is applied to the reset input of the flip-flop 511 in order to reset the flip-flop to 0. The signal 31608 is also applied to the input of a NAND gate 540 (fig. 14N) . The output signal 54008, at state 1, is applied to an input of a NAND gate 582. In the 1024th cycle, when the end of pulse signal 37712 and the local restart request signal 58306 are at l state 1, the two signals are applied to the input of the NAND gate 582. The output signal of this gate then goes to state 0 which is applied to the reset input of the flip-flop 581. The signal 58109 which is applied to the input of the OR gate 469 in fig. 14L is then in state 0. As signal 46908 is applied to the reset input of flip-flop 470, this is set to 0. The sequence set to 0 for the master is thus completed.

When this sequence is completed, the flip-flop 584 of FIG. 14N is reset to 0 in order to allow remote requests to be received in the ISL system via the communication lines. Signals 74406, 47005 and 76208 are applied to the inputs of an AND / OR gate 286. The output signal 28608 is applied to an input of an OR gate 293 whose output 29308 is applied to the reset input of flip-flop 584. Signal 76208 is the output of inverter 762 of FIG. 14V and this signal is the inverse of signal 32610 which is applied to the input of the inverter 762.

The operation of the ISL unit in response to an output control instruction will be made with reference to FIG. 14A. Instructions are received from connector 105 in the form of line address signals 10503 to 10510.10512 to 10519.10521.10523 to 10525.10530 and 10532. Address signals 0-23 are applied to receivers 181 to 205 of fig. 14C. Signals 8-16 of address 18900,19010, 19103, 19214,19306, 19410, 19603, 19703 and 19810 (fig. 14J) are applied to comparators 302 to 310, respectively. The comparators 302 to 310 constitute the address comparator 99 of FIG. 8. These comparators also receive signals 10307, 10306,10314, 10315,10207,10206, 10214, 10215, 10107 and 10114, which are the outputs of switches 101, 102 and 103. The switches are set manually at a predetermined address. The output signals of comparators 302 to 310, namely the signals 30208, 30303, 30411, 30506, 30611, 30703, 30806, 30911 and 31008, are applied to the input of a NAND gate 439. The signal of output 43909 is applied to the CD input of a flip-flop 440.

Signal 24512 indicates that the information transfer is not a memory reference line information transfer. The signal is applied to the input of an AND gate 439. The signal 10444 is received on the connector 104 of FIG. 14A and is applied to the receiver 244 of FIG. 14B. The output signal 24414 is applied to the input of an inverter 245 whose output is applied to the input of the AND gate 439. A line data signal 21401 is received on the connector 105 and applied to the wired OR gate 214. The signal 21815 is applied to the receiver 218 whose output is applied to an inverter 215 (fig. 141). The output signal 21510 is applied to a control device 216. The output 21606 thereof is applied to the input of a delay line 358. The output signal 35811 having a delay of 60 ns is applied to the AND gate 360 in order to produce the signal 36008 which is applied to the clock input of the flip-flop 440 of FIG. 14J. This ensures that the line signals have reached a permanent state and can be sampled. Address signal 44006 goes to state 1 and signal 44005 goes to state 0.

The line address signals 18-23 20006, 20103, 20206, 20314, 20410 and 20510 are applied to the address selection terminals of a read-only memory 399 (fig. 14K). The active signal 10115 and the operational signal 53910 are also applied to the address selection terminals of the read-only memory 399. The active signal 10115 is the output of the switch 101 of FIG. 14J. Each ISL unit in the system can be active or passive. The active state allows the ISL unit to perform certain additional functions. Operational signal 53910, defined as data transfer mode if true and ISL configuration mode if false, is commanded

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by a data bit signal 1 33310 of FIG. 141. This signal will be described later.

Referring to fig. 14L, the line address signals 18-20 20006,20103,20206,20314 and 20410 are applied to the input of a NAND gate 131. If the address signals 18-22 are all at state 0, the output signal 13106 is in state 1 and is applied to an input of an AND gate 405. The signal 23 with address 20510 is applied to another input of the AND gate 405. The active signal 10105 and the address signal ISL 44006 are applied to the other inputs of gate 405. The output signal 40508 is the output control signal.

The function code signal 01 40508 is applied to an input of a NAND gate 394 which generates a function initialization signal 39408. The data bit signal 0 22203 is applied to the other input of gate 394 in order to d 'indicate that the output command carries out the initialization instruction of sub-instruction. The signal 39408 is applied to the input S of the flip-flop 531 and establishes the latter in state 1 in order to initiate the sequence set to 0 of the master as described above. The only difference is that the reset function of the master is launched from a local communication line instead of a sequence energized.

The signal 53109 (reset to 0 master memory) is applied to an input of the OR gate 438 (fig. 14H). The output signal 43808 which is in state 1 is applied to an input of a register 631. The signal 35809 obtained from the output 135 ns of the delay line 358 is applied to the clock input of the register 631. The output signal 63116 is thus brought to state 1. The signal 63116 is applied to an input of an NI 130 gate. The output signal is applied to the input S of the flip-flop 433 so as to generate an acceptance signal 43305 which is applied to the receivers 178 and 179 of FIG. 14C. The signal is transferred to the communication line in order to acknowledge receipt of the information from the transmitting source. The output command initialization instruction is always accepted.

The stop sub-instruction puts the ISL unit in configuration mode and the resumed sub-instruction puts the ISL unit in information transfer mode. Referring to fig. 14L, it can be seen that if the data signal 22203 is not in state 1, the output signal 39404 is in state 0 and the sequence described above is not executed. Instead, the ROM output 399 of FIG. 14K is used.

The output signals 39909 to 39912 from the read-only memory 399 are applied to the input terminals of a register 400. A sampling signal 36204 is applied to the clock input of the register 400. The memory 399 is the memory dead 102 of fig. 8.

The signal 35805 obtained at the output 90 ns from the delay line 358 is applied to an input of a NAND gate 361 (fig. 141). The ISL ready unit signal 44512 and the write line enable signal 64405 are applied to the other inputs of gate 361.

The address signal ISL 44006 is applied to an input of an ET 445 door (fig. 14K). This gate also receives signal 26012 indicating a data response to a read request. The second line half cycle signal 10412 is applied to the receiver 259 of FIG. 14B from connector 104 of fig. 14A. The output signal is signal 25914. The remote test signal 53914 is in state 1 since the instruction is not a test mode instruction.

Referring to fig. 14N, it is seen that the signal 36008 obtained at the output 60 ns of the delay line 360 is applied to the clock input of a D flip-flop 644. The file write validation signal 39607 is applied to the CD input of flip-flop 644. A multiplexer 396 selects the indication that the register, address file 103 or data file 92 of FIG. 8, in which the information is to be entered, is not full. In this case, the signal 58406 applied to an input of the multiplexer 396 indicates that the register request complete recovery is empty since the flip-flop 584 is not in state 1. The signals of selection of file 40903 and 41106 are applied to the inputs for selecting the multiplexer 396. At this time, the two selection signals are in state 0 and the input 0 of the multiplexer 396 is thus selected.

The second line half cycle signal 25914 is applied to an input of a NAND gate 565, to an AND gate 409 and to a NAND gate 478 (fig. 140). The signal 24102 is applied to the inputs of the AND gate 409 and the NAND gate 476. The signal 24414 is applied to the inputs of the NAND gates 476 and 565. The signal 18 of line address 20006 is applied to the input of NAND gate 478. Signals 47808, 56506 and 47603 are applied to the inputs of an NI gate 411 to generate the file write signal 41106. Output signal 40903 is the write file signal .

Since this signal is not a second line half cycle or a line memory cycle, signal 25914 is in state 0. The write selection signals 40903 and 41106 are then also in state 0 .

The signal 10410 (fig. 14B) is applied to the receiver 240 from the connector 104 of fig. 14A. The output signal 24006 is applied to the input of an inverter 241 which produces the signal 24102. The memory reference signal 10444 is applied to the receiver 244 from the connector 104 of FIG. 14A and generates signal 24414.

However, if the rocker 584 of FIG. 14N is in state 1, the ISL unit is occupied. The ISL unit then does not accept an instruction. The signal 64405 is therefore applied to the clock input of a D flip-flop 404 in FIG. 2 p.m. The signal 58406 applied to the CD input of the flip-flop is in state 0. The flip-flop 404 therefore remains in state 0. The function acceptance signal 40409 is in state 0 and applied to the inputs of an AND gate 401 and a NAND gate 421. The output signal 42103 is applied to an input of an AND gate 447. The comparison signal 31808 is applied to another input of the AND gate 447. As it here is not a comparison cycle, the signal 31808 is in state 1. The signal 58506 obtained at the output of the AND gate 585 of FIG. 14N is applied to an input of the ET 447 door. The input signals 40802 and 41008 are in state 1. Signal 40903 is applied to the input of an inverter 410 (fig. 140). The signal 41106 is applied to the input of an inverter 410 whose output is 41008.

A restart signal 56608 is applied to an input of the AND gate 585 in FIG. 14N. Referring to fig. 14K, signals 40712, 33006 and 44512 are applied to the inputs of an ET 442 gate. The ISL ready signal 44512 is in state 1. The data parity error signal 33006 is in state 1 since 'there is no parity error in the data. The restart signal 56608 is obtained at the output of the NI 566 gate in FIG. 14N. The signal 31704 is applied to the input of the NI 566 gate and this signal is in state 0 since the signal 44208 at the input of the NI gate 317 is in the state 1.

The signal 40712 (fig. 14K) is a decoding of the output of the read-only memory 399. The 4 output signals 39909 to 39912 are applied to an NI 406 gate. As long as one of these signals is in state 1 , the output signal 40606 is in state 0. The signal 40606 is applied to the input of an inverter 407 whose output is signal 40712 which is in state 1.

Referring to fig. 14H, we see that the signal 44706 is applied to an input of an OR gate 629. The output signal 62906 is applied to the input of the register 631 whose output 63102 is applied to an inverter 630. The output signal 63006 is applied to terminal S of a D flip-flop 453. The output signal 45301 is in state 1 and is applied to the control side of a control-receiver device 263 (fig. 14B). The output signal 26302 is applied to a wired OR gate 262 which is connected to the connector 104 in order to send a BSWAIT-00 signal over the line.

The signal 58406 is applied to the terminals CD and to the terminals R of the flip-flop 404 (fig. 14H). The signal 84405 is applied to the clock input of this flip-flop and establishes it at state 1 during the occurrence of the leading edge of the signal 84405. The flip-flop 404 is then at state 1 so as to signal an acceptance signal on the line as described above.

The selective access memories 161 to 166 (FIG. 140), which constitute the address file register 103 of FIG. 8, store line address signals 0-23. The random access memories 364, 177, 647, 365, 366 and 389, which constitute the file register of

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data 92 of fig. 8, store 0-15 data signals and line control signals.

The write selection signals 40903 and 41106 select one of the 4 locations in each memory and in the selected locations are stored the signals appearing at the inputs of the memories. The write line authorization signal 64406 is applied to the clock input of each memory in order to point the data to the input of each memory.

At the time when information is written in the memories, the flip-flop 644 and the flip-flop 584 of FIG. 14N are in state 1. This comes from the fact that flip-flop 581 is set to state 1 during the rise of signal 64405 during the duration of signal 36008. Flip-flop 584 is then put into state 1 by signal 35602 since signal 58109 is in state 1.

The signals 92306, 27108, 83006 and 58109 of the cycle generator 146 of FIG. 8 are applied to the inputs of AND / OR gate 388 (fig. 14V). Signal 92306 is in state 1 since the ISL unit does not transfer to the distant line. Signal 63006 is in state 1 since the sequence executed is not a reset sequence of the master. Furthermore, signal 27108 is in state 1 since the operation is not a line register operation and signal 58109 is in state 1.

The output signal 38808 is applied to the OR gate 608 whose output 60808 is applied to the CD input of the flip-flop 464. The output signal 60408 is applied to the clock input of the flip-flop 464. Signals 37606 , 17612, 57206 and 46406 are applied as described above to the inputs of AND gate 604. Signals 37606, 46406 and 57206 are in state 1 if the ISL unit is free. As the sign 38808 applied to the input of the OR gate 176 is in state 0, the output signal 17612 applied to the input of the AND gate 604 is in state 1. The flip-flops 464 and 441 are thus in state 1 in order to start an ISL cycle as described above.

Referring to fig. 140, it can be seen that signals 47005 and 46406 are applied to the inputs of an AND gate 369. These two signals are in state 0. When signal 46406 changes to state 1, the output signal 36903 in the register 121 of fig. 8 goes to state 1. Signal 36903 is applied to the validation input of registers 367 and 368 which make up register 121 of fig. 8. The register then produces the output signals 36702, 36705, 36706, 36709, 36712, 36715, 36716, 36719, 36802, 36805, 36806,36809,36812, 36815, 36816 and 36819. In addition, the register produces the signals 39102, 39105, 39106 and 39109. These signals are applied to wired OR doors 332, 334 to 348 (fig. 14F).

The file read selection signals 40211 and 40312 (fig. 140) select the location in the random access memory containing the information which must appear at the output of the memory. Signals 49014 and 90704 are applied to the inputs of an NI 402 gate, these signals being in state 1 during the request cycle for restarting local operation. Signals 49404,49014 and 48502 are applied to the inputs of an NI 403 door. The inputs are at level 1 since the ISL unit is not in one of the cycles specified by the signals applied to the NI 403 door. The output signal 40312 is in state 0.

The two write selection signals 40211 and 40312, which are in state 0, select the location 0 of the memory. Location 0 is the RRQ operation retry request register. When the file write selection signals 40903 and 41106 are in state 0 during the transfer on the communication line, the information is written in location 0 of the selective access memories.

Referring to fig. 141, it can be seen that the data signal 33401 is applied to an inverter 333. The output 33310 thereof is applied to the input of a register 539. The time signal 32610 and the signal 39702 are applied to a NAND gate 547. In fig. I4K, we see that signals 41810 and 58306 are in state 1 and applied to the inputs of the AND / OR gate 363. The output signal 36308 is applied to the validation input of a decoder 397 which constitutes the decoder of function code 106 in fig. 8. Like signal 36308

is in state 0, the decoder 397 is validated. Signals 20-23 of address 15301, 15401, 15501 and 15601 are applied to the input of decoder 397. In this case, the output control signal 39702 is selected since signal 21 of address 15401 is at state 1 and that the address signals 20, 22 and 23 are in state 1. In FIG. 141, it can be seen that when the time signal 32610 goes to state 0, the output signal 54713 applied to the clock input of register 539 switches the signal 53910 to state 0 if the data signal 33401 is in state 1. The ISL unit is then in the logical stop state. If signal 53910 was in state 1, the ISL unit would be in direct connection state.

Referring to fig. 14F, it can be seen that the signals 40006, 40003, 40004 and 40005 are applied to the wired OR functions 153 to 156. The signals 40003 to 40006 are the outputs of the register 400 of FIG. 14K. Register 400 is validated by signals 41811 and 60306 applied to these validation inputs. The signal 41811 is generated at the output of the register 418. The signal 44208 is applied to the input of the register 418 as described above.

Signals 64508 and 57205 are applied to the inputs of an AND gate 603. These two signals are in state 0 and will be described later. The output signal 60305 is applied to a second validation input of the register 400, so as to load there the output of the read-only memory 399. This memory is coded for the selection operation with the signal 40003 in state 1. The signal 40003 is applied to the wired OR junction 154 of FIG. 14F and the output signal 15401 is applied to the decoder 397 as described above.

Signal 17 of line address 19914 is applied to an input of register 418 if the signal 19914 is in state 1. The remote address signal 41807 is then selected as at the output of register 418 in order to indicate that a remote ISL unit is addressed. If signal 19914 is in state 0, local address signal 41806 is selected to indicate that a local ISL unit is addressed. The output command order is processed by both the local and remote ISL units regardless of the state of line address signal 17149.

The control signal 41815 produced at the output of the register 418 is in state 1 for the function code 01. The signal 41814 is applied to an AND gate 387. When this signal is in state 0, the output signal 38706 applied to the input of a NAND gate 545 goes to state 0. The signal 41802 is also applied to the input of the NAND gate 545. This signal will be described later but it will simply be noted that it is in state 0. The output signal 54513 is applied to an input of a NAND gate 906 (fig. 14U). The signal 58306 is applied to another input of the NAND gate 906. The two input signals 54513 and 58306 are in state 1. The output signal 90611 is. applied to an input of an OR 763 door. The output signal of this door changes to state 1 and is applied to the CJ input of a JK 923 flip-flop. The CK input of this door receives the signal 86011 which is in state 0 since the master reset cycle has not been completed.

The signal 76208 is applied to an inverter 761. The output signal 76108 is applied to the clock input of the flip-flop 923. This clock signal is applied 100 ns after the start of the ISL cycle. The flip-flop 923 at state 1 indicates that a transfer operation is in progress between the local ISL unit and the remote ISL unit. The scale remains in state 1 until the transfer is completed.

The signal 92305 is applied to the clock input of a D flip-flop 919, the latter then being set to state 1. The output signal 91909 is applied to the input of a NAND gate 920. The output signal 92008 is applied to the input of a delay line 917 producing a delay of 125 ns.

The signal 91703 which appears after a delay of 37.5 ns is applied to the input of an OR gate 918. The output signal 91808 is applied to the reset input of the flip-flop 919 which is thus reset to 0 after being at state 1 for 37.5 ns.

The transfer cycle signal 91908 is applied to an input of a NAND gate 897. The signal 86106 is applied to the other input of gate 897 and is in state 0 for this operation. 89701 remote sampling signal is used in the ISL unit

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remote to sample the data sent by the local ISL unit.

We now refer to FIG. 14Z which illustrates the interface control devices 115 and the remote address receivers 104 of FIG. 8. Signal 92306 is applied to the clock inputs of multiplexers / registers 832, 835, 836, 838, 840, 842 and 846. Signals 82610, 86404 and 87311 are applied to the input terminals of an OR gate 911 , these signals being in state 1. The output signal 91108 is applied to the selection inputs of the multiplexers / registers 832 and 835, these signals being in state 1. The input signals applied to the terminal entry 1 are therefore selected.

The signals 86404 and 87311 are applied to the inputs of an OR gate 912. The output signal 91203 is applied to the selection input of the multiplexer / register 836. As in this case, the signals 86404 and 87311 are in state 1 , input 1 of multiplexer / register 836 is selected.

The signals 43009 and 58306 are applied to the inputs of a NAND gate 910. The output signal 91003 is applied to the selection input of the multiplexer / register 840. As in this case, the two signals 43009 and 58306 are at state 0, input 1 of multiplexer / register 840 is selected.

The multiplexers / registers 838, 840 and 842 are wired so as to select input 1 under all conditions. Address signals 0-23 13201,13301,13401,13501,13601,13701,13801,13901, 14001,14101,14201,14301, 14401, 14501,14601, 14701,14801, 14901,15001,15101,15301, 15401, 15501 and 15601 are stored in the multiplexers / registers 832, 835, 836, 838,840,842 and 846.

We will now refer to FIG. 14AA which illustrates the interface control devices 139 and the remote data receivers 116 of FIG. 8. Signal 92306 is applied to the clock input of multiplexers / registers 849, 851, 853 and 855. Signal 92806 is applied to the selection inputs of registers 851 and 853. The selection inputs of registers 849 and 855 are wired to select inputs 1. The selection signal 92806 is the output of the AND gate 928 in fig. 14W. Signals 59012 and 92505 are applied to the inputs of gate 928. As these two input signals are at state 0 for this operation, it is input 1 of multiplexers / registers 851 and 853 which is selected.

Multiplexed data signals 0-15 78307, 78409, 78507, 78609,78707, 78809, 78907,79009, 79107,79209, 79307, 79409, 79509, 79607, 79709 and 79807 are applied to the inputs of multiplexers / registers 849, 851 , 853 and 855.

We now refer to FIG. 14T. The signals 78011 and 78208 are applied to a first selection input of the multiplexers 783 to 798 which constitutes the internal data multiplexer 129 of FIG. 8. Signals 42410 and 80108 are applied to an OR gate 781 which generates the selection signal 78111. Signals 82010 and 80108 are applied to the inputs of an OR gate 782 which generates the selection signal 78208. Like the door inputs 781 and 782 are in state 0, these are the inputs 0 of the multiplexers 783 to 798 which are selected. Data signals 2-15 33501, 33601, 33701, 33801, 33901, 34001, 34101, 34201, 34301, 34401, 34501, 34601, 34701 and 34801 are applied to input 0 of multiplexers 785 to 798, respectively. Signals 93012 and 93009 are applied to input 0 of multiplexers 783 and 784, respectively. Signals 93012 and 93009 are the outputs of a multiplexer 930. Data signals 0 and 1 of data 33201 and 33401 are applied to input 0 of multiplexer 930. Signal 82706 is applied to the selection input of multiplexer 930 and it is at state 0 for this operation. The validation signal 80108 is applied to the validation input of the multiplexers 783 to 788, this signal being in state 0 so as to validate the multiplexers 783 to 788. The multiplexers 789 to 798 are always validated.

At this time, the address and data information has been received by the local ISL unit through the communication line and is stored in the registers. The address and data signals are sent over the internal communication line to be routed to the remote ISL unit via the interface control devices 115 and 139 of FIG. 8.

We will refer for example to FIG. 14AA. The output of the register multiplexer 849 sends signals 84912 to 84915 to the input of a control device 848. The output signals 84803, 84805, 84807 and 84809 are applied to a set of termination resistors 651 (fig. 14AC) . At the output of this set of resistors 651, signals 65111 to 65114 are applied to the terminals of a connector 660 which constitutes the internal communication line. The outputs of the multiplexers 851, 853 and 855 (fig. 14AA) are sent to the connector 860 via the control devices 850, 852 and 854 (fig. 14AA) and the resistance sets 651, 652 and 653 (fig . 14AC).

The signal lines of connectors 660 and 663 transmit information to the remote ISL unit. The signal lines of connectors 661 and 662 receive information from the remote ISL unit.

Referring to fig. 14U, we can see that the signal 92305 is applied to the clock input of a register 813. The input signals 86404, 90002, 86712 and 90910 represent the 4 ISL cycles, the memory request the request to restart d operation, the memory response and the operation retry response, as described above. In the case of the RRQCYL local operation restart request cycle described here, the signal 90002 is in state 0. The output signal 81307 is then in state 0, this signal being applied to the input of a control device 814 (fig. 14AB) to be transmitted to the remote ISL unit.

We now refer to FIG. 14AB. Ground signal 67708 is applied to terminal F of a receiver-control device 733. This device 733 is always enabled if the cables between the local ISL unit and the remote ISL unit are connected to the respective ISL units. Signal 67708 is the output of an inverter 677 (fig. 14AC). A capacitor 667 and a resistor 668 are connected to the input of the inverter. A potential of 5 V is applied to the other terminal of the resistor 668 while the ground is connected to the other terminal of the capacitor 667.

In the remote ISL unit, a ground signal 66201 is applied to pin 1 of connector 662, via the cable, to pin 1 of connector 663 of the local ISL unit, this pin 1 being itself connected to ground. When the cables are connected, the ground present at pin 1 of the cable 663 appears at the input of the inverter 677 and changes the signal 67708 to state 1, which validates the receiver 733 (in the ISL unit remote). If the cable is disconnected between the 2 ISL units, the ground signal 66201 present at pin 1 of the connector 662 is brought to the high state by the resistor 668 and carries the ground signal 67708 to the state 0. The latter signal inhibits the outputs of the remote receiver 733 (fig. 14AB). Consequently, if the cables are connected, the remote sampling signal 73307 is applied to the clock input of a flip-flop JK 874 (fig. 14V) which is set to state 1 by the front edge of the sampling signal.

In the remote ISL unit, the output signal 87409 is applied to the input of an AND gate 799. The signal 62088 is applied to the other input of this gate. As signal 62008 is in state 1, the output signal 79911 is in state 1. Signal 79911 is applied to an input of an AND gate 612 (fig. 14AB). The signal 97708 is in state 1 since the cables are connected, and therefore the signal 81208 is in state 1. This signal is applied to the validation terminal of the receiver-control device 815. The input signal 66222 having been generated in the local ISL unit, the output signal 81509 is applied to the input of an inverter 816 which sends an output signal 81606 to an input of an AND / NI gate 578 (fig. 14V ).

Gate 578 also receives signals 93214 and 92306 which are in state 1.

The output signal 57808 is applied to an input of an AND gate 558. The other input of this gate receives the signal 87407 which is in state 0. The output signal 58803 is therefore in state 0 and this signal is applied to an input of an AND gate 571 which receives at its other input the comparison signal 29709 which is at state 0 since the cycle being executed is not a comparison cycle. The

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signal 57106 is applied to the input of an NI 176 gate whose output signal is at state 0 and is applied to an input of the AND gate 604. The ISL cycle is thus executed as described above. In the present case, however, it is the remote cycle flip-flop 572 which is set to state 1 instead of the local cycle flip-flop 464. In addition, since flip-flop 464 is not in the state 1, register 490 remains empty and cycle signals 58306, 59012, 48603 and 49303 remain in state 0. Instead, it is the remote cycle signal 90201 (fig. 14U) which is generated.

Signals 81509 and 57206 are applied to the input of a NAND gate 902. The output signal 90201 is the signal RRQCYR which designates the remote operation restart request cycle in the remote ISL unit.

If the process is not in information transfer mode, gate AND 573 in fig. 14V produces an output signal 57304 at state 1 and this signal is applied to an input of an ET 880 door (fig. 14AB). Ground signal 67708 is applied to the other input of this door. The output signal 88006 is applied to the validation terminal of the receiver 808 (fig. 14V). Signal 56108 is applied to the input of an inverter 876, the output signal 87602 of which is applied to an input of an AND gate 878 (fig. 14AB). Earth signal 66201 is applied to the other input of this door. The output signal 67803 is applied to the validation input of the control devices 882 and 884 (fig. 14Z). The command receivers 889, 890, 891, 892, 818 and 817 in FIG. 14AA and the command receiver 809 of fig. 14AB are validated in a similar manner. In addition, the command receivers 881 to 886 of FIG. 14Z are validated to receive information from the internal communication line.

The address and data signals and some control signals were transferred from the local ISL unit to the remote ISL unit and an ISL cycle was started in the remote ISL unit.

We will now refer to FIG. 14K. The remote signal 56108 is applied to the input of an AND / NI gate 363. The signal 93214 is applied to the other input of the gate 363. As described above, the decoder 397 which constitutes the function code decoder 106 of fig. 8, is validated. The output control signal 39702 is selected as above since the address signals 15301,15401,15501 and 15601 have been received on the internal communication line of the other ISL unit.

We now refer to FIG. 14V. The delay line 374 generates the end of cycle signal 37407 which is applied to the inverter 377. The output signal 37712 is applied to the NAND gate 323. The signal 32712 is also applied to the gate 323. The signal output 32306 is applied to the input of an OR gate 463 whose output signal 46306 is applied to an OR gate 291 which generates the signal set to remote 0 29111. This signal resets flip-flop 572 so that terminate the remote cycle portion of the output command instruction. The final completion of the instruction takes place in the local ISL unit. The transfer signal carried out 92206 is generated in the remote ISL unit by the signal CYC100 76208 and the remote cycle signal 57205 at the gate ET 922 is received in the local ISL unit via the receivers mentioned above.

In the local ISL unit, the signal 73303 is applied to the input of an NI 739 door (fig. I4U). The output signal 73913 is applied to the reset terminal 0 of the flip-flop 923, the latter thus being reset to 0. The flip-flop 923 was originally set to state 1 when the transfer of information has started between the local ISL unit and the remote ISL unit.

Signal 92306 is again applied to AND / NI gates 388 and 578 (fig. 14V) in order to authorize another ISL cycle in the local ISL unit, which allows it to accept another instruction from line.

The output interrupt control instruction loads the interrupt information into the ISL unit so that when an interrupt is initiated, the central processor can be interrupted at the designated level.

The flip-flop 581 (fig. 14N) is in state 1 as described above. The signal 64405 which sets this flip-flop to state 1, also loads the address, data and command information received on the line in the address and data files of FIG. 14Q, as previously described. Signal 58109 is applied to the input of register 490 (fig. 14V) as previously indicated.

In fig. 14K, the signals 41810 and 58306 applied to the gate 363 authorize the generation of the output signal 36308 which validates the decoder 397. As previously, the read only memory 399 is addressed and the information contained in the addressed location is stored in the register 400. The output of this is applied to the OR junctions wired in fig. 14F and applied to decoder 397. In this case, the output interrupt control signal 39710 is selected, this signal being applied to one input of an AND gate 551. Signal 57508 is applied to the other input of gate 551, this signal being in state 0. The output signal 55106 is applied to an input of a NAND gate 825 (fig. 14M). The time signal 32610 is applied to the other input of the NAND gate 825. The output signal 82504 is applied to the clock terminals of registers 819 and 857, of the interrupt channel register 132 and of the register interrupt level 134 of fig. 8.

Data signals 6-8 of data 33901, 34001 and 34101 are applied to entries in register 819 and data signals 10-15 of data 34301, 34401, 34501, 34601, 34701 and 34801 are applied to entries of register 857, which ends to this part of the instructional cycle. The local cycle flip-flop 464 (fig. 14V) is reset to state 0 as described previously.

If this instruction was launched by the local ISL unit, flip-flop 584 (fig. 14N), which indicates that the operation retry request cycle is complete, is reset to 0 as described above.

If the remote ISL unit has to process the command to interrupt the output, then in the local ISL unit the signal 19914 which is applied to the input of register 418 (fig. 14K), in the state 1, carries to state 1 the remote address signal 41807 and to state 0 the local address signal 41806. The output of AND gate 387, that is to say signal 38706, is at state 0 and carries to state 1 the output 54513 of the NAND gate 545. The signal 57508 appearing at the output of the AND gate 575 is thus brought to state 1. The output 55106 of the door ET 551 is also brought to state 1.

Referring to fig. 14M, signal 55106 in state 1 carries in state 0 the output 52504 of NAND gate 825, which prevents other information from being loaded in registers 819 and 857. In this case, l the local ISL unit transfers the information to the remote ISL unit. The signal 54513 in state 1 carries in state 0 the output 90611 of the NAND gate 906, which brings to state 1 the signal 76308. This last signal puts the flip-flop 923 in state 1 as described above, which has the effect of generating the information transfer cycle between the local ISL unit and the remote ISL unit.

The instruction to set the timers to 0 validates a certain number of timers in the local ISL unit. The signal 39717 is generated in state 0 by the decoder 397 (fig. 14K) and is applied to an input of an AND gate 553. As this is a local operation, the remote function signal 57508 applied to the other input of gate 553 is in state 0. The output signal 55311 is therefore in state 0 and is applied to the input of an inverter 554 at the output of which a signal 55404 appears in state 1. This signal is applied to the input of a NAND gate 280 (fig. 14X). The output signal from the delay line 325 is applied to the other input of the gate 280. The output signal 28008 is applied to the clock input of a register 914 which is part of the mode control register 535 of fig. 8. The output signals from register 914 allow a number of conditions. When one of these conditions lasts beyond a time limit, the rhythm output instruction is used to reset the rhythms to zero in order to prevent any new error.

The output signal 91407 is a signal for enabling the sequencer of the sequence controller. This rhythm is a one second rhythm that is used in conjunction with the software to determine if a device is not responding to a signal from the ISL unit. The

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output signal 91402 resets this timer to 0. Signal 91410 is the timer enable signal. The timeout validation signal checks whether a device has a hardware fault. The output signal 91415 is the reset enable interrupt signal which checks whether resources are non-existent. This interruption is detected during a memory write operation or after the time allocated to the memory has been exceeded.

During the sequence set to 0 by the master as well as during one of the above-mentioned rhythmic operations, the signal output at 0 55208 is at state 1 when the signal 28008 or the signal 47006 applied to the input of a door NI 552 is in state 0. This signal authorizes the resetting to 0 of all the timers in the ISL unit.

We now refer to FIG. 14Y. The data signal 3 33601 and the output signal at 0 55203 are applied to the input of a NAND gate 600. All the data signals 9-15 are at state 1 during the reset sequence of the master. The signal 60006 is applied to the reset input of a D flip-flop 599, which is the flip-flop for exceeding the time allowed for an operation restart. The operation of the flip-flop 599 will be described later.

Similarly, signal 55203 and data signal 0 33201 are applied to the inputs of a NAND gate 506. The output signal 50608 is applied to the reset terminal of a D flip-flop 0 to 0 reset this flip-flop to 0. Flip-flop 505, when it is at state 1, indicates that no response is received from the memory. This operation will be described later.

The signal 55203 and the data signal 1 are applied to the inputs of a NAND gate 460. The output signal 46011 is applied to the reset terminal of a D flip-flop 0 to reset this flip-flop to the state 0. The flip-flop 459, when it is in state 1, indicates that the time allowed for an input / output device has been exceeded.

Referring to fig. 14X, we see that signal 55203 and data signal 2 33501 are applied to the inputs of an AND gate 635. The output signal 63503 is applied to the reset terminal of counters 636 and 637 in order to set these counters to 0. These counters are part of the sequence controller timing control. The operation of this control device is described below.

The output address instruction, unlike the instructions described above, does not affect the remote ISL unit. Exit address instructions are issued only to the local ISL unit because all addresses are controlled by the local ISL unit. The output instruction loads an address into the local ISL unit. This address information contains a channel address and / or a memory address. The output address instruction selects one of the address locations.

The output address instructions select the signal 39706 produced at the output of the function code decoder 397 (fig. 14K). In fig. 14Q, which illustrates the selective access memory counter 118 and the selective access memory control register 108 of FIG. 8, it can be seen that signals 39706 and 32404 are applied to the input of a NAND gate 743. The output signal 74310 is applied to the clock input of register 758 and to the input of a inverter 742. The output signal 74212 from this inverter is applied to the terminal Gl of the counters 744, 745 and 746, thus authorizing the introduction of data into the counters. Register 758 is loaded with data signals 3-5 33601, 33701 and 33801 which are the write enable signals of the three selective access memories (central processor conversion memory, memory conversion memory and bit memory channel).

Counter 744 is loaded with data signals 6 and 7 of data 22901 and 34001. Counter 745 is loaded with data signals 8-11 of data 34101, 34201, 34301 and 34401. Counter 746 is loaded with signals 12-15 of data 34501, 34601, 34701 and 34801.

The output address instruction is completely executed when the counters 744, 745 and 746 are loaded with the addresses of the locations which must be read or modified and when the register 258 stores the write validation bits for the selection of address in random access memories.

The output data instruction is used in conjunction with the output address instruction. Thanks to the addressed locations and to the memories designated in the output address instruction, the data received from the communication line during this instruction are stored in the random access memories at the designated address.

The output signal 39715 from the decoder 397 is brought to state 0. As described previously, the signal 39715 and the remote function signal 57508, which are both in state 0, are applied to the input of the AND gate. 643. The output signal 64303, which is the write signal in selective access memory, is in state 0 and is applied to the input of the NI gate 639. The write enable signal 63908 is in state 1. In fig. 14V, it can be seen that the signal 63908 and the signal 32502 are applied to the inputs of the AND gate 638. The signal 63811 is thus brought to state 0.

Signals 53910 and 56108 are applied to the input of door ET 748 (fig. 14Q). The output signal 74808 is applied to the validation terminal of registers 741 and 929, which has the effect of making the address stored in the counters 744, 745 and 746 appear at the output of these registers. register 108 of fig. 8, namely the signals 74102, 74105, 74106, 74109, 74112, 74115, 74116, 74119, 92905, 92906.92909.92912.92915 and 92916 are applied to the OR junctions 137 to 149 of fig. 14F.

The output of register 758 (fig. 14Q) is applied to OR gates 730,737 and 759. The output signals 73003,73706 and 75906 determine the selective access memory in which the address stored in registers 741 and 929 is written. signal 73003 is the memory conversion write enable signal. Signal 73706 is the channel write authorization signal and signal 75906 is the central processor conversion write signal. It is therefore possible to write information in any combination of random access memories. Signals 73003, 73706 and 75906 are all stored in register 929.

Signals 75906, 73706 and 73703 appear on the address line in the ISL unit as address signals 13701, 13801 and 13901, respectively. Signal 13701 is applied to the input of NAND gate 760 (fig. 14W). The signal 63811 is applied to the other input of the gate 760 and the output signal 76003 is applied to the write validation terminal of the memories 757 and 754, that is to say the source central processor memories 131 and destination central processor 113 of fig. 8.

In fig. 14R, it can be seen that the signals 13801 and 63811 are applied to the inputs of the NAND gate 312. The output signal 31206 is applied to the write authorization terminal of the selective access memory 276, which is the memory of channel activity bit 142 of fig. 8.

Referring to fig. 14S, it can be seen that the signals 13901 and 63811 are applied to the inputs of the NAND gate 859. The output signal 85906 is applied to the write validation terminals of the memories 706 to 715 and 883, which are the memory 125 of fig. 8.

At the end of the instruction, the counters 744, 745 and 746 are activated by the signal 74711 which is applied to the +1 input of the counter 746. The signal 39715 applied to the input of the NI 908 gate is at state 0, so that the output signal 90812 is in state 0. As the signal 90002 is also in state 0, the output signal 74003 is in state 0. As the end signal pulse 37606 is at state 0, the output signal 74711 is at state 0 and activates counter 746 at the end of the ISL cycle when signal 97606 goes to state 1.

In fig. 14N, it can be seen that the flip-flop 584 is reset to 0 by the input signals 76208, 56803,47006 and 57611 in state 1.

For remote operation in response to the output mask data instruction, only the output mask address is issued via the local line so that if an output mask data instruction is to be sent to a remote line, the address will be sent on the remote line in the same way as described above on the address line and the data and

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other functions will come from the data file as described above.

For a write operation in the selective access memories of the remote ISL unit, the address and data information originating from the local ISL unit are sent to the remote ISL unit and the counter therein does not is not used to control the addresses of memories, the information for addressing always coming from the local ISL unit.

The input interrupt command is received from the internal communication line exactly as the output instructions, but the output signal 39909 at the output of the read-only memory 399 (fig. 14K.) Is in state 1. The signal 39910 is applied to the input of the register 400. The output signal 40005 is applied to the wired OR junction 156 of FIG. 14F. The signal 15601, at state 1, is applied to the input of the decoder 397. The output signal 39709 is at state 0. The signals 19914, 44208 and 44508 are applied to the inputs of register 418. The signals of output 41806,41810 and 41814 are in state 1. These signals are applied to the input of the door AND 387. The output signal 38706, in state 1, is applied to the input of the door NON- AND 545. The output signal 54513, at state 0, is applied to the input of the gate NI 613 whose output is brought to state 1.

The flip-flops 581 and 584 (fig. 14N) are once again set to state 1 and a local ISL cycle is launched as described above. Address and data information on the communication line is stored in the file registers of the local ISL unit.

The purpose of the instruction is to read the contents of the two registers 819 and 857 (fig. 14M). Register 819 contains the central processor channel address and register 857 contains a level at which the interrupt is controlled. The information extracted from the register 819, which constitutes the interrupt channel register 132 of FIG. 8, and the information extracted from the register 857, which constitutes the interrupt level register 134 of FIG. 8, are placed on the communication line.

Signals 81902, 81907, 81910, 81915, 85715, 85702, 85710, 85707, 85705 and 85712 are applied to input 3 of data multiplexers 789 to 798, respectively (fig. 14T). Ground signals are applied to the inputs 3 of the multiplexers 783 to 788. Signals 39709 and 42708 are applied to the inputs of an NI 801 gate. The signal 39709 is at state 0. The output signal 80108 is at state 1 and is applied to the inputs of the OR gates 781 and 782. The output signals 78111 and 78208, in state 1, are applied to the selection inputs 1 and 2, respectively, of the multiplexers 783 to 798, so as to select input 3 of these multiplexers.

Signals 78907,79009, 79107 and 79209 are applied to input 0 of the multiplexer 780 (fig. 14W), which constitutes the data multiplexer 137 of fig. 8. The output signals 78004, 78007, 78009 and 78012 are applied to input 1 of the multiplexer 526 (fig. 14G). The output signals 78609, 78307, 78507, 78409, 78809, 78707, 79307, 79509,79607,79709 and 79807 are applied to input 1 of registers 525, 527 and 528 (fig. 14G) which constitutes the multiplexer register of data 138 of fig. 8. The signal 52408 obtained at the output of the AND / NI gate 524 is applied, at state 1, to the selection input of registers 525, 526 and 527 so as to select the input 1. The signals 52408 and 42709 are in state 1 and are applied to the inputs of an AND 372 door. The output of this door goes to state 1 which is thus applied to the selection input of register 528.

NAND gate 465 (fig. 14G) receives signals 15202,61306 and 58306. Address signal 15202 indicates that the input instruction is being executed. The signal 46508 produced at the output of gate 465 is applied, at state 0, to the input of gate NI 378. The output 37806 thereof is at state 1.

Referring to fig. 14D, it can be seen that signals 76208 and 37806, at state 1, are applied to the inputs of an AND / NI gate 278. The output signal 27808 is applied to the clock inputs of registers 525 to 528 (fig. 14G). The output signals 52514, 52512, 52513, 52515, 52613, 52612, 52614, 52615, 52712, 52714, 52713, 52715, 52814, 52815, 52813 and 52812 are applied to the parity generators 521 and 522 which generate the parity signals 52109 and 52209.

The signals 27808 and 56406 are applied to the inputs of the OR gate 562. The output signal 56211 is applied to the input of an inverter 563 whose output 56308 is applied to the clock input of a demand flip-flop ISL 450. The signal 45009 and the busy line signal 20804 are applied to the inputs of a NAND gate 533. If the line is not busy, the output signal 53303 which is applied to the memory request toggle 534, puts it in state 1.

The signal 56211 is also applied to the clock terminal of the flip-flop 446. The output signal 44609 is then brought to state 1 and validates the line priority network by its application to the NAND gate 520. If all the entry conditions for gate 520 are satisfied, the output signal 52009 is applied to the set-up input of flip-flop 517, thus indicating that the ISL unit is collecting information from the line Communication.

The outputs of registers 525 to 528 and of the parity generators 521 and 522 are applied to the inputs of the control-receiver devices 219, 220, 222 to 238 (fig. 14B). The other inputs of the receivers receive the memory data channel signal which now transfers the information on the line.

The ISL cycle ends as described above by resetting flip-flop 584 (fig. 14N) when signals 76208, 56803,47006 and 57611 applied to the inputs of gate ET-NI286 are in state 1 and by reset to flip-flop 581 when signals 37712, 58306 and 54008 applied to the inputs of NAND gate 582 are in state 1.

The remote interrupt control instruction is similar to the local interrupt control instruction except that the signal 19914 applied to the input of register 418 (fig. 14K) is in state 1. The output signal 41806 is applied to state 0 at the input of the AND gate 387. The output signal 38706 is in state 0, which brings to state 1 the signal 45413, and to state 0 the signal 61306.

The signal 61306 applied to the input of the NAND gate 465 (fig. 14G) carries the signal 46508 to state 1, which has the effect of bringing to the state 0 the validation signal 37806. The signals 37806 and 76208 are applied to the entrance of the door ET / NI 278 (fig. 14D). Signal 37806, in state 0, carries to output state 1 the output signal 27808, which has the effect of blocking the clock input of registers 525 to 528.

The remote ISL unit generates an ISL cycle and returns the data to the local ISL unit as specified by the instructions.

As in remote ISL cycles, the decoder 397 (fig. 14K) generates the signal 39790 which in turn generates the remote request cycle in the remote ISL unit. However, the remote ISL unit returns the data to the local unit in the following way. We refer to fig. 14U. The signals 15301 and 90112 are applied to the inputs of a NAND gate 905. The output signal 90504 is applied in state 1 to the input of the AND gate 822. The signal 93214 is applied to the other input of gate 822. As it is in the remote ISL unit, signal 93214, at state 1, was generated by the local ISL unit and sent to the remote ISL unit to indicate that 'it was a remote function code.

The output signal 82208 is applied to the input of a NAND gate 924, The end of pulse signal 37606 is applied to the input of an inverter 800 whose output 80002 is applied to the other input of gate 924. The output signal 92408 goes to state 0 at the end of the remote cycle, thus setting flip-flop 923 to state 1. This flip-flop then launches the information transfer cycle between the remote ISL unit and the local ISL unit as described above.

The signal 82208 is applied to an input of an NI 909 door. The signal 59012 is applied to the other input of door 909 whose output 90910 is applied to an input of the register 813. The signal 92305 is applied to the register clock input 813. Signal 81314 is returned to the local ISL unit. The signal 81503 (fig. 14V) is generated and applied to an NI 269 gate whose output 26912 is applied to the input of the AND / NI 578 gate. The signal 27108 is applied

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qué at the other input of gate 578, which launches the remote cycle in the local ISL unit as described above.

The initial cycle in the local ISL unit is a remote input cycle. The cycle originating in the local ISL unit is sent to the remote ISL unit to initiate a response request cycle in the remote ISL unit. This cycle in the remote unit generates a response cycle in the local ISL unit. The local unit then launches a response cycle in order to send on the line the data received from the remote unit during the response cycle in the local unit.

In the local unit, the signal 81503 received from the remote ISL unit and the signal 57206 are applied to the inputs of a NAND gate 597 (fig. 14N). The output signal 59710 is applied to an input of an OR gate 592. The other input of this gate receives the signal 46108 at state 0. The output signal 59211, at state 1, indicates the cycle of distant response.

As previously described, the data line and the address line in the local ISL unit provide an image of the remote address and data receivers of the other ISL unit. Thus, in the case described, the data which is presented on the data line is the interrupt channel and the interrupt level coming from the remote ISL unit.

The data line carries the correct data during this remote cycle to the local ISL unit. This data is transmitted through the data multiplexers 783 to 798 of FIG. 14T, which constitute the data multiplexer 129 of FIG. 8. Unlike the local input interrupt command, the output of the function code decoder is not valid at this time since it is a response cycle.

Signals 29709 and 42708 are now in state 1 and applied to the input of the NI 801 door (fig. 14T). The selection signals 78111 and 78208 are therefore in state 0, which has the effect of selecting the input 0 of the multiplexers 789 to 798. There are thus selected the signals 6-15 of data 33901, 34001, 34101, 34201, 34301, 34401, 34501, 34601, 34701 and 34801, these signals representing interrupt channel and interrupt level information sent from the remote ISL unit to the local ISL unit.

All the cycles described so far are ISL cycles which validate the function code decoders. The remote operation retry response cycle does not validate any function code decoder. Referring to fig. 14K, it can be seen that the signal 36308 applied to the input of the decoder 397 is in state 1. Consequently, a remote function code is not generated for this cycle. Data and address information is sent over the line as described above.

Referring to fig. 14N, we see that flip-flop 584 is in state 0 and that flip-flop 581 is in state 0 during the original response request cycle as during an exit instruction or the initial entry instruction by the intermediate of door 582. During the response request cycle, flip-flop 581 is reset to 0 when the pulse ends. Flip-flop 584 is the function that keeps this path busy, and therefore resetting flip-flop 581 to 0 at this time does not affect operation since it cannot be reset to state 1 before signals 58405 and 58406 have returned to their normal state when the flip-flop 584 is not in state 1.

The register 418 (fig. 14K) is not reset to 0 by the signal 56011 produced by the OR gate 560. The register 418 is consequently set to 0 at the same time as the flip-flop 584 (fig. 14N), which releases all the control functions which were placed in register 418 when this instruction was launched.

The input mask data instruction basically reads the activity bit from memory 142 of FIG. 8. It reads the memory address translation and the memory activity bit 125 of FIG. 8. It reads the destination address translation from the central processor of the memory 131 of FIG. 8. The input data instruction is always preceded by an output address instruction except when contiguous locations are to be read. An input data instruction is followed by another input data instruction. But sometimes there is an exit address instruction which loads the address of the starting location to be read from the counter 118 in fig. 8. It is this counter which loads the command register 108, the output of which is used to address the selective access memories designated in the memories 142, 125 and 131 mentioned above. The address information is used to address the selective access memories and the data extracted from these memories are transferred over the data line to the ISL unit, local or remote, for which the instruction is intended. The complete cycle executed by a local input data instruction comprises a communication line cycle to present the instruction, then an internal ISL cycle which, in this case, is an operation retry request cycle, and finally another line of communication cycle. Thus, there is only one internal ISL cycle for a local input data instruction. The remote input data instruction requires three internal ISL cycles. The first cycle is a restart request cycle which sends the address of the location to be read from the random access memory to the remote ISL unit. During this cycle, the memory address is sent to the remote ISL unit together with the function code which was described above, in order to generate the second cycle, a restart request cycle, in the unit. ISL remote. These data in turn are collected in the memories of the remote ISL unit, analogous to the memories 142, 125 and 131 of FIG. 8. The data is then sent back to the local ISL unit where a third cycle is generated. After this cycle, the data is placed on the communication line to be transferred to the central processor that requested the data. Most of the logic operations performed by the instruction have been covered by the description of the input interrupt command instruction. The main difference is at the output of the function code decoder which selects the appropriate inputs of the multiplexers in order to direct the data to the data line so as to send the data to the selected communication line either from the local ISL unit, either from the remote ISL unit.

The flip-flops 584 and 581 (fig. 14N) are in state 1 as described above. Signal 58506 is in state 1 and is applied to the CJ input of flip-flop 581 and clock signal 66405 puts flip-flop 581 in state 1. Signal 58109 is applied to input CJ of flip-flop 584 which is thus set to state 1 when the clock signal 35602 drops. This prevents other instructions from being accepted by the ISL unit during the restart path.

As described above, the ISL unit generates an ISL cycle when it detects a request to restart an operation. The ISL cycle starts the time sequence in delay line 374 (fig. 14V) and establishes a local ISL cycle regardless of whether it is a local or remote instruction at this time. The local cycle generates, if the instruction is addressed to the local ISL unit, the time and data circuits to send the data to the communication line control device. The function code decoder 397 (fig. 14K) generates a signal 39714 for the instruction of input data. The input data function code on the communication line is a function code 10 and is applied to the read-only memory 399 at the same time as the configuration of suitable control bits. The output of the read-only memory 399 is a coded function code which is stored in the register 400. The output of this register, as described above, is presented on the address line during the local restart request cycle, and the function code at the input of the decoder 397 validates the input data function 39714. This function, if it is intended for the local ISL unit, attempts to read the data from the designated registers.

During data entry, the data multiplexers of fig. 14T collects all the appropriate data through the various registers. The signal 39714 is applied to the input of an inverter 820 whose output 82010 is applied to the input of an OR gate 782. The signal 78208 produced at the output of gate 782 is the selection signal 2 and is found in state 1. Selection signal 1

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of multiplexer 78111 is in state 0 since the two inputs of gate 781 are in state 0 since it is not an interrupt cycle. Consequently, it is the inputs 2 of the multiplexers 783, 784, 785 and 786 which are selected. The input data are the function signals 75411, 75409, 75407 and 75405 obtained at the output of the memory 754 of FIG. 14W.

The signals 74904, 74907, 74909 and 74912 obtained at the output of the multiplexer 749 (fig. 14W) are applied to the address selection terminals of the central processor destination memory 754.

The signals 59012 and 92505 are applied to the AND gate 928. As this is not a local response cycle, the output signal 62806 is in state 0 and is applied to the selection input of the multiplexer 749. The signals 14-17 with addresses 14601, 14701, 14801 and 14901 are therefore selected.

We now refer to FIG. 14Q. The output of the counters 744, 745 and 746 is applied to the inputs of the registers 741 and 929 which constitute the control register 108 of FIG. 8. As the operation is in ISL configuration mode and concerns a local operation, the signals 53910 and 56108 which are applied to the input of the AND gate 748 are at state 0. The output signal 74808 is at state 1 and validates registers 741 and 929. The selected outputs of these registers are reflected at the input address selection terminals of memory 754 (fig. 14W) as described previously. Counters 744, 745 and 746 were previously loaded from an output address instruction.

The channel mask memory 276 (fig. 14R), which stores the channel activity bit, has its address selection inputs selected by the multiplexers 313, 314 and 315. The signal 53911 is applied to the input for selecting multiplexers 313, 314 and 315. As the cycle described is in configuration mode, signal 53911 is in state 1, which has the effect of selecting input 1. These are signals 8-17 address 31509, 31504, 31512, 31507, 31412, 31409, 31404,31407,31304 and 31312.

The output 27607 of the memory 276 is applied to the input 2 of the multiplexer 787 (fig. 14T). The signal 86307 is applied to the input 2 of the multiplexer 788. This is the output of the memory 863 of FIG. 14S. The input address selection signals 0-9 47507, 47409, 47307,47312, 47309, 47304,47204, 47209, 47212 are generated as the outputs of the multiplexers 472 to 475 (fig. 14R). The input selection signals 1 and 2 48112 and 53911 are in state 1. As this is not a memory reference cycle and the ISL unit is not in transfer mode of data, the input signals 24414 and 53910 applied to gate 481 are in state 0. The output of this NAND gate is therefore in state 1. Consequently, signals 8-17 of address 14001 , 14101,14201,14301,14401, 14501,14601, 14701,14801 and 14901 are selected. The output signal 86307 from memory 863 (fig. 14S) is therefore selected. This is the memory activity bit. ''

Memory translation memories 706 to 715 have their output signals 70607, 70707, 70807, 70907, 71007, 71107, 71207, 71307, 71407 and 71507 which are applied to inputs 2 of data multiplexers 789 to 798, respectively (fig . 14T). The memories 706 to 715 are addressed by the signals addressing the memory 863 of FIG. 14S.

For a local input data instruction, the data received from the multiplexers 783 to 798 are transferred to the input 1 of the registers 525 to 528 (FIG. 14G) which are the line interface multiplexer registers 138 of FIG. 8.

As described above, the selection signal 52408 selects the signals at input 1 of registers 525 to 527 and the selection signal 37208 selects the signals at input 1 of register 528. The other operations executed for a data instruction d The local inputs are the same as those described above for the transfer of information on the communication line at the end of the local stimulus request cycle.

The execution of a remote input data instruction is identical to the operation described above for the input interrupt command. During the local restart request cycle, a transfer cycle is generated to send a remote sampling pulse to the remote ISL unit. This uses this signal to generate a distant cycle. This remote cycle is a remote stimulus request cycle as described above and the main differences lie in the fact that the data multiplexer and the memory for channel address translation and memory, instead of receiving their address a command counter as described above, the remote ISL unit receives its address from the remote address receivers 104 of FIG. 8.

Thus, the address information applied to the channel activity bit memory of FIG. 14R, to the memory translation memories of FIG. 14S and to the central processor translation memories of FIG. 14W always come from the address bits as described above, and the outputs of these memories supply the data multiplexer as for the local unit. But the output of the data multiplexer, instead of being applied to the data multiplexer registers of FIG. 14G, is this time applied to the local data control devices of FIG. 14AA. The multiplexer registers 849, 851, 853 and 855 receive the outputs of the multiplexers and this data is stored in these registers at the time of the complete transfer signal, which has been described previously. This signal, obtained at the output of door 924 of FIG. 14U, is the signal that appears at the end of the 100 ns delay in the remote cycle if the data is intended for the local ISL unit. The data must be sent back to the local ISL unit and, therefore, the four multiplexers receive the data which is sent back to the local ISL unit. The latter, as described above, receives a signal to generate a remote response cycle. This cycle has been described above and has the function of sending the data received from the remote ISL unit to the communication line register, then generating a communication line cycle and sending the data back to the central processor which has initially requested the data.

The ISL unit input state instruction is now described. This instruction is identical, with regard to the logic cycle and the sequencing, to the other input instructions of the ISL unit. Only the local retry request cycle is performed if the instruction is intended for the local ISL unit. If the instruction is intended for the remote ISL unit, 3 cycles are executed, the local dunning request cycle in the local ISL unit, the remote dunning request cycle in the remote ISL unit and the response cycle reminder in the local ISL unit. The only differences are as follows.

Signal 39711 is selected at the output of decoder 397 (fig. 14K). This signal is applied to the input of an inverter 424 whose output 42410 is in state 1 and applied to the input of the OR gate 781 (fig. 14T). The signal 78111 is then in state 1 and selects the input 1 of the multiplexers 783 to 798. The signal 78208 is in the state 0. Consequently, the signals at input 1 of the multiplexers are selected to be transferred on the communication line and then to the requesting central processor. These input signals applied to multiplexers 783 and 798 are summarized in Table 12. Bit 0 (signal 87203) is the operational bit, that is to say bit 0 which indicates whether the ISL unit is in data transfer or in configuration mode. Bit 1 (signal 89309) indicates whether there has been an interrupt requested by a remote ISL unit. This signal indicates both a timeout allocated to the sequence controller and a nonexistent resource error.

Instead of explaining all the individual status bits at this stage, we will complete the description of the data flow executed during the instruction and after that we will show that each of these individual status bits is shown in fig. 14T.

As indicated previously, the data at the output of the multiplexers 783 to 798 (fig. 14T) are applied to registers 848, 851, 853 and 855 (fig. 14AA) for the local ISL input state instruction. A communication line cycle is generated and the status information sent to the requesting central processor.

Remote input status instruction is the same as remote input data and interrupt command instructions

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entry. The information is sent on the line from the remote ISL unit to the local ISL unit from where it is sent on the communication line to the requesting central processor.

Here after are described the functions that the status bits execute in unit 133 of flg. 8. The first status bit is operational bit 87203 (fig. 14T). Signals 62806 and 53910 (fig. 141) are applied to the inputs of an ET 872 gate. Signal 62806 is in state 1 and indicates that the other ISL unit, remote or local, is in connection with the system and under pressure.

The signal 66243 is connected to the ISL interface line by the connector 662 in FIG. 14AB and is applied to an input of the control device 736 (fig. 14AB) and to a resistor 665 connected on the other hand to the potential + 5 V. Consequently, if any ISL unit is disconnected or not supplied, the signal 63243 is in state 1.

The output signal 63612 is applied to the input of an inverter 628 (fig. 14J). The output signal 62806 is applied to the input of an AND gate 872. The signal 53910 is in state 1 and the output signal 87203, in state 1, is applied to input 1 of the multiplexer 783 of fig. 14T.

The control device 913 (fig. 14 AB) receives a ground signal at its input. The output signal 91318 is applied to the connector 663 and then to the other ISL unit, so as to apply the ground signal to the two interconnected ISL units.

The second status bit is bit 89309 applied to input 1 of multiplexer 784 (fig. 14T). Signal 78409 is generated at the output of the multiplexer.

Referring to fig. 14X, it can be seen that the signal 87112, the signal 91616, the signal 91402 and the signal 91415 are applied to the inputs of an AND / NI gate 895. The output 89508 of this gate is in state 0 and indicates that it there was a remote interrupt or a timeout allocated in the remote unit, this signal being applied to the establishment input of a flip-flop D 893.

Signal 37712 and status signal 42410, in state 1, are applied to the inputs of a NAND gate 609 (fig. 14Y). The output signal 60906 is applied to the input of an OR gate 295. A signal set to 0 by the master 83006 is applied to the other input of the gate 295. The output signal 29506 is in state 0 and is applied to the reset input of flip-flop 893 (fig. 14X), thus resetting this flip-flop to 0 after the status bit has been read.

In fig. 14T, it can be seen that the input 1 of the multiplexer 785 is connected to ground, that is to say that a logic 0 is applied to this input. The signal 78507 is therefore in state 0. The signal 78609 is generated by the active signal 10115 applied to the multiplexer 786. The signal 10115 is the output signal of the hexadecimal rotary switch 101 of FIG. 14J, which indicates that the local ISL unit is active when the state is 1 or that the local unit is passive when its state is 0.

The signal 78707 produced at the output of the multiplexer 787 and the signal 78809 produced at the output of the multiplexer 788 are both at state 0 since the inputs 1 of these two multiplexers are at state 0.

Bit 6 of data is the signal 78907 produced at the output of the multiplexer 789. The latter receives at its input 1 the signal 91502. Referring to FIG. 14X, the signal 10435 coming from the connector 104 of FIG. 14A is applied to the input of a resistor 112 (fig. 14X). The other terminal of this resistor, at which the signal 11202 is present, is connected to a 0.01 capacitor (j, F 113 by which the signal 11202 is applied to the input of a Schmitt rocker inverter 261. The other terminal of the capacitor 113 is connected to ground. The output of the inverter 261 is applied to the input of an AND gate 634. The signal 91407 and the signal 63712 are applied to the other inputs of the gate. AND 634. The signal 91407 is in state 1 during the execution of the instruction described above. The signal 63712 prevents a timeout cycle allocated if the previous cycle has exceeded the time allocated to it. 63406 is applied to the validation terminal G2 and to the clock terminal of the counter 636. The output signal 63602 is applied to the validation and clock inputs of the counter 637. The output signal 63712 is applied to the input of an ET 634 gate as described above and at the input of an inverter 915. The signal d he output 91502 is applied to input 1 of the multiplexer 789. The sequencer controller is reset to 0 by signal 63503 to state 1 within approximately 1 s after the start of the operation of the counters 736 and 737, then signal 91502 is generated. The resetting of counters 736 and 737 to 0 has been described previously.

The status bit 7 is the signal 79009 produced by the multiplexer 790. It is connected to ground and is therefore in the 0 state.

The status bit 8 is the signal 79107 produced by the multiplexer 791. The signal 59905 is applied to input 1 of this multiplexer. The signal 59905 is brought to state 1 if, during an input / output instruction intended for a controller connected to the distant line, an acceptance signal 16001 or a negative acceptance signal 24901 is not received within a delay 120 ms after the start of the instruction, indicating to the central processor that initiated the instruction that there is a fault in a device. The generation of signal 59905 has been described previously.

The data bit 9 is the signal 79209 produced at the output of the multiplexer 792. The input 1 thereof receives the signal 45909 which is in state 1 when an input / output instruction sent to a controller on a line remote gave rise to a confirmation response and when the second line half cycle is not received within 250 ms. That is to say that the validation signal for the timers has been set to the true state as described above.

Data bit 10 is the signal 79307 produced at the output of multiplexer 793. Input 1 of this multiplexer receives signal 50509 which is in state 1 if a second line half cycle is not received in a delay of approximately 6 | is when the first line half cycle has been confirmed. The operation of the flip-flop 505 of FIG. 14Y has been described previously.

The data bit 11 is the signal 79409 produced at the output of the multiplexer 794 and the data bit 12 is the signal 79509 produced at the output of the multiplexer 795. These two signals are in state 0 since the inputs 1 of these multiplexers are connected to ground.

The data signal 13 is the signal 79607 produced at the output of the multiplexer 796. The terminal 1 of this multiplexer receives the signal 86905 which is in state 1 if, during a memory writing operation, the location addressed n does not exist in the system. Referring to fig. 141, we see that the signal 24814 is applied to the input of a register 413. The output signal 41307 is applied to the input of a NAND gate 544. The memory write signal 52306 and the memory request signal 51505 are also applied to the inputs of gate 544. The output signal 54408 is in state 0 and applied to the establishment input of a D flip-flop 869 (fig. 14T), which has the effect of putting this flip-flop to state 1 in order to indicate that the memory location addressed by the remote ISL unit does not exist.

Data bit 14 is the signal 79709 produced at the output of the multiplexer 797. The input 1 of this multiplexer receives the parity error signal 44409. This signal is in state 1 each time an instruction sent to the ISL unit contains incorrect parity. Referring to fig. 14B, we see that the data signals 0-15 are applied to the inputs of the parity generators 232 and 239. The odd parity signals 23206 and 23906 are applied to the inputs of an NI gate 221. The output signal 22108 is applied at the other input of OR gate 331. Signal 25403 indicates that the source has detected an incorrect parity before sending the data on the line. The signal 33108 is applied to the CD input of a D flip-flop 444 (fig. 14Y) which is thus set to state 1 at the time of occurrence of the clock signal 36204 if the incorrect parity has been detected.

The data bit 15 is the signal 79807 produced at the output of the multiplexer 798. This signal is at state 0 since the input 1 of this multiplexer is connected to ground.

The input identification instruction is different in its launching process from the other input instructions in the sense that it makes no difference as far as the ISL device is concerned,

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local or remote, who issued it. The cycle is the same. Only one cycle is indicated, a local cycle. The identification which is returned for an ISL unit is either a hexadecimal signal 2402 in the case where the local ISL unit and the remote unit are both connected and powered up and, if the remote ISL unit is not connected electrically, the identification signal returned is a hexadecimal number 2400.

The output of read-only memory 399 is applied to the input of an AND gate 419 (fig. 14K). The output signal 41906 is applied to the input of the register 418 whose output 41802 is applied to the input of a NAND gate 545. The signal 41802, in state 1, inhibits the output signal 54513 and prevents it from generating a distant cycle. Also, the decoder 397 generates the output signal 39716 which is applied to the selection inputs of the multiplexers 435 and 436 (fig. 14J) in order to select the identification function code 24 in hexadecimal.

Signals 42304 and 62806 are applied to the inputs of an AND gate 417. Signal 42304 is in state 1. Signal 62806 has been described previously as being in state 1 when the remote ISL unit is connected and under voltage. The output signal 41711, in state 1, gives a hexadecimal digit 2 for the last hexadecimal digit. Consequently, the identification code is the hexadecimal number 2400 for an operational local ISL unit and a hexadecimal number 2402 when the two ISL units, local and remote,

are operational.

Referring to fig. 14G, signal 42304, at state 1, is applied to the input of an AND / NI gate 524. Output signal 52408, at state 0, is applied to the input for selecting registers 525 , 526 and 527, so as to select the inputs 0 of these registers. The selection signal 52408 is applied to the input of an AND gate 372 which constitutes the data multiplexer register 138 of FIG. 8. The output signal 37208, at state 0, is applied to the selection input of the register 528 so as to select the output of the latter.

Signals 43504,43410 and 43507 applied to the entry of register 525 are at state 0 and input signal 43509 is at state 1. Signal 43512 applied to the entry of register 527 is at state 0 and the input signal 43604 is in state 1. Signals 43609,43612 and 43607 applied to the input of register 526 are in state 0. The output signal 52615 is in state 0 since its input terminal is grounded. Signals 52908 and 86606 are applied to the input of an OR gate 513. The two signals are at state 0 since they are associated with a function transfer cycle other than an identification function. The output signal 51303 which is applied to the input of the register 527 is in state 0.

The output of the OR gate 514, the signal 51406, is applied at state 0 to the entry of the register 527. The signal 53006 applied to the input of the gate 514 is at state 0. The output signals 52814 and 52815 are in state 0 since the respective inputs of register 528 are grounded, that is to say in state 0. The signal 41711 describes either a local ISL operation of a local ISL unit and a remote ISL operation, as described above.

The output signal 52812 is in state 0 since the input of register 528 is grounded during the restart request cycle. The signal 27808 is generated as described above in order to load the identification code into registers 735 to 738, thus generating a communication line cycle and sending the identification code to the central processor requesting the data. This is shown in fig. 8 on which the information present on the rotary switch 140 is sent directly to the register 138. This essentially completes the operation in configuration mode.

We now refer to FIG. 14K. The output signals 40003 to 40006 are applied to the wired OR junctions 153-156 in fig. 14F in order to transmit the signals 20-23 of address 15301, 15401, 15501 and 15601. The register 400 is validated by the signals 41811 and 60306 which are in state 0. The signal 41811 has been described previously.

The signals 64508 and 57205 are applied to an AND gate 603. These signals are in state 0 since the operation is not a remote cycle nor a transfer cycle. The output signal 60306 is applied to the validation input of register 400 and this signal is in state 0.

In information transfer mode, the ISL unit uses all of the configuration data that was loaded during configuration mode operation. The first cycles executed aim to establish a memory request path, which takes 4 cycles. The initial MRQCYL cycle follows the detection of the memory cycle by the ISL unit, then the MRQCYR cycle which takes place in the remote ISL unit is executed. At this time, if the instruction is a memory write instruction, the cycle stops. There are therefore only these two cycles if the data must be written to a memory connected to the remote communication line. But if a memory read operation is required, then the ISL unit remains in the busy state for the memory request path and waits for a memory response cycle. A local memory response cycle is then performed in the remote ISL unit, followed by a remote memory response cycle in the local unit which initiated the original instruction. The memory request cycle initiates the initial request instruction and then waits for a response from memory. This response comes through the remote ISL unit. The basic transfer therefore includes 2 cycles for a write operation and 4 cycles for a read operation. During the BSDCNN cycle, the ISL unit responds as an agent for the memory request that is presented to the communication line from a local device. Referring to fig. 140, the selection logic for a write operation in a file register is done via a NAND gate 476. This receives at its inputs the signal 24414 which is a signal generated by the line of communication, and a function signal 24102, which is another signal generated by the communication line. Signal 24102 indicates that there is no test or test instruction for a memory, while signal 24414 indicates that the instruction is a memory instruction.

The signal 24414 and the signal 24102, both in state 1, are applied to the input of a NAND gate 476. The output signal 47603 is applied to the input of an NI gate 411 whose output 41106 is at state 1. This output signal is applied to the input of the inverter 410 whose output 41008 is at state 0. Signal 25914, at state 0, is applied to the input of the AND gate 509. The output of the latter, at state 0, is applied to the input of the inverter 408 whose output 40802 is at state 1. Consequently, for a memory request , location 2 of the selective access memories of FIG. 140 is selected. Previously, location 0 was selected for configuration mode.

Signal 48706 is applied to the input of multiplexer 396 (fig. 14N). The selection signals 40903 and 41106 are applied to the selection inputs of the multiplexer 396 so as to select the input 2 thereof. The output signal 39607 is applied to the CD terminal of the flip-flop 644 and, when the clock signal 36008 is applied, the flip-flop 644 is set to state 1 and its output signal 64405 is applied to the clock input of a JK 483 flip-flop. The signals 54808, 40802 and 41106, in state 1, are applied to the input of an AND gate 489. The signal 54808 is obtained at the output of the AND gate 548 of fig. 141. The signal 86307, obtained at the output of the memory 863 of FIG. 14S, and signal 62606 are in state 1 since the operation is in operation transfer mode and not in test mode.

The output signal 48912 is applied to the CJ terminal of a flip-flop 483. The output signal 48305 is applied to the CD input of a flip-flop D 487. 135 ns after the start of the cycle, the signal 35712, which found applied to the clock input of the flip-flop, sets flip-flop 487 to state 1, and the output signal 48705 inhibits any new movement affecting this location of the data file. The output signal 48706 is applied to the setting input of flip-flop 487 in order to maintain the latter at state 1 when other signals 35712 are applied to the clock input.

Referring to fig. 14S, we see that the signals 70607 to 71507 obtained at the output of the translation memories 706 to 715 are applied

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ques at the inputs of registers 717 and 716. The clock inputs of these registers receive the signal 48305 and when this signal goes to state 1, the signals of the memories are loaded in the registers.

Signals 86307, 24414 and 41106, in state 1, are applied to the inputs of an ET 477 gate (fig. 14H). The output signal 47706 and the signal 46209 are applied to the inputs of an AND gate 484. The signal 64406 is applied to the clock input of a flip-flop JK 462. The output signal 46209 is in state 1 The signal 48408 is applied to the input of the register 631 which is activated by the signal 35809 135 ns after the start of the cycle. The output signal 63115 is applied to the input of the NI 130 gate. The output signal 13005, at state 0, is applied to the setting terminal of the D flip-flop 433 which is thus set to state 1. A confirmation signal is then sent to the communication line in order to complete the cycle.

At the start of the memory request operation for a read operation, the timer for a memory cycle is started. Referring to fig. 14Y, signal 48305 is applied to the clock input of a D flip-flop 617. As this is a write operation, signal 26610 is in state 0 and flip-flop 617 is not found not in state 1. For a read operation, the flip-flop 617 is in state 1 and the signal 61706 is applied to a negation input of a vibrator at a stroke of 6 us. Signal 48603, at state 1, is applied from a vibrator to a stroke 611.

The memory request cycle is started as follows. Signal 48306 is applied to an input of an NI 645 door (fig. 14V). The output signal 64508, in state 1, is applied to an input of an AND / NI gate 388. As the signal 92306 is in state 1, the output signal 38808 is in state 0 and sets the local cycle flip-flop 464 as well as the ISL 411 cycle flip-flop to state 1 as described above. Signal 46405 introduces signal 48305 into register 490. Signal 49002 goes to state 1 and signal 49003 goes to state 0. Signal 49002 is applied to the input of an AND gate 486 and, if the current cycle is not a memory response cycle, the signal 49014 is in state 1, which brings to state 1 the signal 48603 and to state 0 the signal 48502. The request cycle memory, like all cycles involved in operation in configuration mode, activates delay line 374 and the cycle continues as described above.

The logic for ending the memory request cycle for various states of the local device now follows with reference to FIG. 14N. In order to reset flip-flop 487 to 0, signal 48502, in the state

0, and the time signal 32610 are applied to the inputs of a NAND gate 482. The output signal 48201 applies a state 1 to the input of an AND / NI gate 488. The file write signal 36609 applies a state 1 to the other input of gate 488. The output signal 48808 applies a state 0 to the input of an OR gate 283. The output signal 28306 is then in state 0 and resets to 0 flip-flop 487. The other input of gate 283 receives signal 83006 (set to 0 by the master) in state 1. Flip-flop 487 is reset to 0 if the ISL unit performs a write operation of memory. Flip-flop 487 is not reset to 0 if the ISL unit performs a read operation.

The signal 48201 is applied to the input of the NI gate 282. The output signal 28204 is applied to the reset terminal 0 of the flip-flop 483 and this is thus reset to 0, which ends the cycle memory request only if it is a write operation. If on the contrary it is a read operation, the flip-flop remains in state 1. In order to transmit the information to the remote ISL unit, a JK flip-flop full transfer is put in the state

1. As described above, signal 86404 applies a state 0 to the input of an NI 763 door (fig. 14U). The output signal 76308 is applied to the input CJ of the flip-flop 923 which is set to state 1 when the clock signal 76108 drops loading all the data and address information into the control devices d address and local data to send the data to the remote ISL unit.

The data path is established as follows. The signals which have been written to location 2 of the file register are selected by the read selection signals 40312 and 40211. The memory response cycle signal 49014 and the restart response signal 40704 both apply a state 1 at the entrances to the NI 402 door (fig. 140). The read selection signal 1 40211 is applied to the read input 1 of the file. The memory request cycle signal 48502 applies a state 0 to the input of the NI gate 403. The read selection signal 40312 applies a state 1 to the read input 2 of the location 2 of the file and stores address, data, and control signals belonging to memory request cycles.

The input selection signals 78111 and 78208 are in state 0, which has the effect of selecting input 0 of the multiplexers 783 to 798 (fig. 14T). The selection signal 82706 is applied to the selection input of the multiplexer 930. As the selection signal 82706 is in state 0, it is the input 0 of the multiplexer 930 which is selected.

Referring to fig. 140, we see that the signals DFIL0-15 obtained at the output of the files 364,177, 647, 365, 366 and 389 are applied to the inputs of registers 367 and 368. The signals DFIX 0-15 obtained at the output of these registers are transferred on the data line.

The signal 16803 is applied to the validation input of files 162 and 161 and is generated at the output of the OR gate 168. The signal 58305 is applied to the input of a NAND gate 169. As it does not this is not a response request cycle, signal 58305 is in state 0; consequently, the output signal 16908 applied to the input of the OR gate 168 is in state 1. The signal 54906 is applied to the other input of the OR gate 168, this signal being in state 1 since it is not a free cycle. The output signal 16803 in state 1 prevents the output signals from files 161 and 162 from being selected.

Signal 48502 is applied to the input of an OR gate 167. As this is a memory request cycle, this signal is in state 0 and the output signal 16708 is in state 0. The signal 16708 is applied to the validation inputs of files 163, 164, 165 and 166, which authorizes the appearance of the output signals AFIL08-23. AFILO-7 output signals are not allowed.

Register 716 stores the memory translation address signals 0-7 which are obtained at the outputs of the translation memories 705 to 713 (fig. 14S). Register 717 stores the translation address signals 8-9 which are obtained at the outputs of memories 714 and 715. Consequently, during the memory request cycle, the signals ADXLMO-9 are applied to the inputs 0 of the multiplexers 832 , 835 and 836 (fig. 14Z). The registers 832, 835, 836, 838, 840, 842 and 846 are all controlled by the fallout of the complete transfer signal 92306. The selection signal 91108 is in state 0 since the signal 86404 applied to the door input OR 911 is in state 0, which has the effect of selecting the input 0 of the multiplexers 832 and 835. In a similar manner, the signal 91203 selects the input 0 of the multiplexer 836 since the signal 86404 applied to the input of OR gate 912 is at state 0. Signals 72001 to 72901 are selected by registers 832, 835 and 836 and applied to the inputs of control devices 833, 834 and 837 in the form of address signals LCAD0 -9 in order to be transferred to the communication line. The output signals 83612 and 83613 are applied to the inputs of the control devices 847 and 844 (fig. 14AB) respectively, to be transferred to the communication line.

The inputs for selecting the registers 838, 842 and 846 are in state 1, which has the effect of selecting the inputs 1 of these registers. The selection input of register 840 is also in state 1 since it is not a response request cycle and, therefore, the signal 58306 applied to an input of NAND gate 910 is at state 0.

Address signals 14201,14301,14401,14501,14601,14701, 14801,14901, 15001, 15101, 15301, 15401,15501 and 15601 are applied to entries 1 of registers 838, 840, 842 and 846. Also, the signal 36407 and file write signal 36609 are applied to inputs 1 of register 846. The output address signals

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LCAD 10-23 are applied to the inputs of control devices 837, 839, 841 and 843 in order to be transferred to the remote ISL unit via the interface line. The signals 84613 and 84615 are applied to the inputs of the control device 844 in order to be transferred to the interface line.

Register 813 (fig. 14U) is in state 1 when the full transfer signal 92305 rises. The memory request cycle signal 86404 applies a state 0 to the input of register 813. Output signals 81302 apply a state 0 to the input of the control device 814 (fig. 14AB). The output signal 81409 is applied to the input of the resistor network 655 (fig. 14AC). The output signal 65515 is applied to the connector 663 in order to transfer the signal to the remote ISL unit. The signal 66220 arrives in the remote ISL unit on the connector 662 and this signal is applied to the input of the receiver / control device 815 of FIG. 14AB. The output signal 81507 is applied to the input of the OR gate 269 in fig. 14V. The output signal 26912 applies a state 1 to the input of the AND / NI gate 578. Assuming that the complete line signal 27108 at state 1 at this time, the output signal 57808 is in the state 0. This signal is applied to the input of the AND gate 558. The output signal 55803 is applied to the input of the AND gate 571. The output signal 57106 is applied to the input of the NI gate 176 whose output 17612 is applied to the input of the AND gate 604. The output signal 60408 is applied to the clock terminal of the flip-flop 441 which is thus set to state 1. The remote cycle flip-flop 572 is also set to state 1.

Referring to fig. 14V, we see that the signals 81507 and 57206 are applied to the inputs of a NAND gate 865. The signal 86513 is in state 1. The signal 57205 applies a state 1 to the input of the OR gate 561 The output signal 56108 applies a state 1 to the control devices 881 to 886 (fig. 14Z), to the control devices 803 and 809 (fig. 14AB) and to the control devices 889 to 892 (fig. 14AA). Information from the local ISL unit is received in the remote ISL unit by these control devices.

Address and data information from the local ISL unit has been received by the remote ISL unit. The address information includes the first ten bits of the memory translator in the local ISL unit. The other address bits were received by the local ISL unit from the central processor and then sent to the remote ISL unit. The data information, the signals 33401 to 34801 are received from the local ISL unit by the remote ISL unit and transferred to the inputs 0 of the multiplexers 783 to 798 of FIG. 14T. The outputs of the OR gates 781 and 782, namely the signals 78711 and 78206, are in state 0 for this cycle. Data bits 1 and 2 are selected via input 0 of multiplexer 930.

The DTMX0-15 signals obtained at the output of the multiplexers 783 to 798 reflect the data transferred by the local ISL unit. Referring to fig. 14C, it can be seen that the address signals 8-11 received from the local ISL unit, namely the signals 14001, 14101, 14201 and 14301 are applied to the inputs 0 of the multiplexer 157. The signals 12, 13, 18 and 19 of address 14401, 14501, 15001 and 15101 are applied to inputs 0 of multiplexer 158. Signals 20-23 of address 15301, 15401, 15501 and 15601 are applied to inputs 0 of multiplexer 160. Signals 14-17 d address 14601, 14701, 14801 and 14901 are applied to input 1 of the multiplexer 731 of FIG. 14M. The output signals 73107, 73109, 73112 and 73104 are applied to the inputs 0 of the multiplexer 159. Since this is not an interrupt cycle, signal 42709 is in state 0, which validates the multiplexers 157 to 160 (fig. 14E), the outputs of these multiplexers reflecting the signals applied to their inputs. Inputs 0 are selected because it is not a second line half cycle and selection signal 37806 is in state 0. The outputs of multiplexers 157-160 are connected to the inputs of registers 508 and 509. Register 507 receives the address signals 0-7 directly from the address line and, since this is not an interrupt cycle, the reset signal to 0 42708 is located at state 1.

The DTMX0-15 signals obtained at the outputs of the multiplexers 783 to 798 (fig. 14T) are applied to the inputs 1 of the multiplexers 525, 527 and 528 of fig. 14G and at input 0 of the multiplexer 780 of FIG. 14W. In fig. 14G, it can be seen that the signal 86513 and the signal 39310 are applied to the inputs of the AND / NI gate 524. The output signal 52408 is in state 1 and selects the inputs 1 of the multiplexers 525, 526 and 527. The signal 37208 selects input 1 from register 528. The file write signal 80701 applies a state 1 to the input of the inverter 393 whose output 39310 is in state 0. The output signals from the multiplexer 780 of fig. 14W, namely the signals 78004, 78007,78009 and 78012 are applied to the input 1 of the register 526 of fig. 14G.

If the remote unit performs a. read operation and if the file write signal 80701 is in state 0, signal 39310 is in state 1. The output signal 52408 is in state 0, which has the effect of select the inputs 0 of registers 525, 526, 527 and 528. The selection signal 37208 is in state 0.

Referring to fig. 14J, it can be seen that the output signals of the rotary switches 101, 102 and 103 are reflected at the inputs 0 of the registers 525 to 528 of FIG. 14G.

The signal 51303 is generated at the output of the OR gate 513. The signal 86606 is applied to the input of the gate 513. The signal 80701 applies a state 0 to the input of an inverter 806. The output signal 80612 is applied to the input of an AND gate 868 whose other input receives the signal 86573 in state 1. The output signal 86606 is therefore in state 1 for a read operation and at the state 0 for a write operation which is reflected by the signal 51303 applied to the input of the register 527. Consequently, for a read operation, the signal 52615 is at state 0. The signal 52713 is at l state 1, signal 52715 is in state 0, signal 52814 is in state 0, signal 52815 is in state 0, signal 52812 is in state 0.

The clock signal 76208 and the signal MRQCYR (fig. 14D), at state 1, are applied to the inputs of the AND / NI gate 278. After a delay of 100 ns, the signal 27808 applies a state 0 to l input of the inverter 279 whose output 27908 therefore applies a state 1 to the clock inputs of registers 507, 508 and 509 (flg. 14E) and to registers 525 to 528 (fig. 14G). The signal 27908 also sets the D flip-flop 271 to state 1. We see in fig. 14V that signal 27108 applied to the input of the AND / NI gate 578 prevents the start of another remote ISL cycle.

If no central processor is connected to the remote line,

it is the ISL unit which generates the negative response on behalf of the nonexistent device.

There are two methods of generating the negative confirmation response (NAK response). The first method is executed if the ISL unit generates the response or if the ISL unit sees on the line a DCN signal which is not its own signal. The flip-flop D 268 (fig. 14Y) is in state 1. The signal 36008 is applied to the input of a flip-flop at a stroke 612. If this is not reset to 0 before 7 | is by the signal 21306, then a signal 61204 is applied to the flip-flop 268 to put the latter at state 1 if the communication signal 36008 is applied. In the communication line logic, a timeout function is provided on the line. If the cycle is assigned to a nonexistent device, there is no response. Within 5 us, the central processor connected to this line then responds in place of the nonexistent device by sending a negative confirmation signal. The line is then freed up to serve another transfer of information. The central processor connected to this line generates an internal loopback on this cycle and controls the progress of a subroutine.

It was said above what happens when everything is normal in the system and when the memory request cycle has been confirmed on the remote line. Various things can happen, however, if the memory request cycle is not confirmed, that is, when a negative confirmation or acceptance response is issued. Such a response can be caused either by a nonexistent device, or by a parity error, or by a faulty memory. The negative answer could be generated by the memory itself.

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same or by any timeout on the line at the CD input of flip-flop 268 which is still in state 1. In fig. 14H, we see that the signal 26806 is applied to the input of an OR gate 274. The output signal 27411, at state 0, puts the D flip-flop at state 1. The output signal 44909 is applied to the input of a transmitter-receiver device 247 (fig. 14B), which generates the signal 24901.

The second method of generating a negative response is explained with reference to FIG. 14Y. The signals 36008 and 51707 are applied to the inputs of a device at a stroke of 3 (is 100. The output signal 10012 is applied to the clock input of a D flip-flop 535. If the signal 36008 which is applied at the CD input of the flip-flop is in state 1 at the expiration of 3 us, flip-flop 535 is set to state 1. Fig. 14H shows that signal 53508, in state 0, is found applied to the other input of the OR gate 274 and the negative confirmation signal is then generated as described above The negative confirmation signal 24814 received from the remote ISL unit is applied to the entry of register 413 whose output 41307 is applied to an input of the NAND gate 544. Another input of this receives the signal 51505, which causes the generation of the nonexistent memory signal 54408. When it is at state 0, this signal indicates that the remote ISL unit has exceeded its time limit. Signal 54408 sets flip-flop 869 to state 1 (fig. 14T). Output signal 86905 is the status signal which indicates an error for nonexistent resource. The signal 54408 (fig. 14X) is applied to the input of an NI 824 door whose output 82406 is applied to the clock input of flip-flop D 823. The CD input of this flip-flop receives the signal 82106 This is generated as follows (see fig. 14M). The data signal 34301 is applied to the input of the register 857. This signal is in state 1 for an interrupt inhibition operation. The signal 85715 is applied to the inverter 856 whose output 85606 is applied to the input of a NAND gate 821. The signals 1-5 of level 85702, 85705, 85707, 85710 and 85712 are applied to the inputs of NAND gate 858. Signal 85806 is applied to the input of NAND gate 821. Signal 82106 is controlled by data signals 10-15 applied to register 857. If signal 82106 is at state 1, thus indicating that the interruption is not inhibited, flip-flop 823 (fig. 14X) is in state 1. The output signal 82309 is applied to a NAND gate 607 and the output of this one this is applied to the input S of a D flip-flop 427 which produces an interrupt cycle in the ISL unit which interrupts the communication line on which the non-existent resource was found.

The local ISL unit also has the option of interrupting the remote ISL unit. Referring to fig. 14AB, we see that the nonexistent memory signal 54408 is applied to the input of the transmitter 870. The signal 87018 produced by it is placed on the intercom line to be sent to the remote ISL unit where the signal 66137 is received in the receiver 916. The output signal 91616 is applied to the input of an inverter 871. The output signal 87112 is applied to an input of the AND / NI gate 895 (fig. 14X). The other input of this gate receives the signal 91415 which is in state 1 if the output timer instruction has been issued with data bit 6 in state 1. Signal 89508, in state 0, puts flip-flop 893 at state 1. This signal 89508 also controls the OR gate 824 so that it produces a level 1 signal which puts flip-flop 823 at state 1 as described above.

In the foregoing has been described the operation by which a write instruction has been sent to a remote memory. This was assumed to be either non-existent or non-operational so that the time interval of 3 us was found to have expired. The non-existent memory function in the remote ISL unit gave rise to the sending of an indication of non-existent memory to the remote ISL unit. Flip-flop 823 (interrupt to do) in the remote ISL unit and flip-flop 823 (interrupt to do) in the local ISL unit have been set to state 1. Data signals 10-15 have been read in. state 1 by the central processor in order to allow the interruption. It is possible for one ISL unit to inhibit the interruption and for the other ISL unit to allow the interruption.

A second normal read half response is the result of a successful read request, confirmed on the distant line. The DCN cycle, which is generated by the memory in response to the memory read request, is first sent to the ISL unit containing the ISL address. The address is placed on the pass line during the second memory response half cycle.

In fig. 14J, we see that the line address signals 8-16 applied to the EXCLUSIVE gates 302 to 310 are compared to the ISL address signals 8-13 and, if the compared signals are in equal states, then the gates 302 to 310 apply a state 1 to the inputs of the AND gate 439. As the operation executed is a memory read operation, the signal 24512 is in state 1 and the output signal 43909 is applied to the input CD of flip-flop 440. The time signal 36008 is applied to the clock input of this flip-flop and this is thus set to state 1.

Referring to fig. 140, signal 25914 and signal 18 with address 20006, at state 1, are applied to the input of NAND gate 478. The output signal 47808, at state 1, indicates that the second line half cycle occurs in response to a memory request. The output signal 47808, in state 0, is applied to the input of the NI gate 411, which authorizes the signal 2 for file write selection 41106. The signal 1 for file write selection 40903 is in state 1 since blocking signal 24102 is in state 1. Consequently, location 3 of the data and address files is selected.

Signals 40903,41106 and 44006 apply a state 1 to the inputs of an ET 500 gate (fig. 14N). The output signal 50008 is applied to the input of an AND gate 496. Since this is not a double extraction operation, the signal 21104 which is applied to the other input of the AND gate 496 is in state 1. The output signal 49611 is applied to the input CJ of a flip-flop JK 492 (memory response to be made). The write enable signal 24405 is applied to the clock input which sets flip-flop 492 to state 1 when the leading edge of the pulse occurs.

The output signal 49206 is applied to the input of the NI 351 door (fig. 14V). The output signal 35106 is applied to the register 490. The output signal 49206 is also applied to the input of the NI 645 gate whose output 64508 is applied to the input of the AND / NI 388 gate. The other input from this door receives the complete transfer signal 92306, at state 1. As described previously, this establishes the local cycle flip-flop 464 at state 1 as well as the ISL cycle flip-flop 441. The output signal 49015 is applied to the input of an AND gate 493. Since this is not a double cycle operation, the signal 35206 applied to the other input of the AND gate 493 is in state 1. The output signal 49303 is therefore at state 1. The purpose of the memory response cycle is to extract data from memory via the remote ISL unit and send it to the local ISL unit in order to present it at the source. who requested the data on the local communication line. Consequently, flip-flop 923 is set to state 1 in order to load the interface registers. The signal 49309 is applied to the input of an inverter 867 whose output 86712 is connected to the input of the NI gate 763. The output signal 76308 is applied to the input CJ of the flip-flop 923 and the latter is set to state 1 when signal 76108 drops. As described above, the interface registers are loaded and the data transferred to the local ISL unit via the internal communication line. Note that the address information is not important at this time as it will be replaced in the local ISL unit by the address of the source.

Fig. 14T shows that signal 80101 is in state 0 since the operation in progress is not an input interrupt control operation, nor an interrupt cycle operation. Signals 78111 and 78208 are in state 0 since it is not an input state operation, nor an input data operation. Consequently, the inputs 0 of the multiplexers 783 to 798 are selected.

The data information is stored in registers 367 and 368 (fig. 140). The control information is stored in register 391, the outputs of which are always validated. The ace

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Output of the AND gate 369 is at state 0 because it is a local cycle operation and not an operation set to 0 by the master. Signals 47005 and 46406 are in state 0. The output signals from registers 367 and 368 are then applied to the wired OR gates 332 to 348 of fig. 14F. The outputs of these doors then reflect the data stored in files 364-366, 177, 647 and 389 (fig. 140). As a result, the data conveyed by the multiplexers 783 to 798 of FIG. 14T are stored in registers 849, 851, 853 and 855 in fig. 14AA. The output signals from the transmitting devices 848, 850 and 852 are reflected on the receivers in the local ISL unit. The pointing signal from the remote ISL unit in this case causes the generation of a remote memory response cycle in the local ISL unit.

Signal 86712 is applied to the input of register 813 (fig. 14U). When signal 92305 is in state 1, the output signal 81310 is placed on the intercom line and transmitted to the local ISL unit as signal 81403 (fig. 14AB). The signal is received in the local ISL unit as signal 66219 and is then reflected at the output of the transmitter device 815 as signal 81505. This last signal is applied to the input of the NI 269 gate (fig. 14V). The output signal 26912 indicates a remote cycle in the local ISL unit by setting the flip-flop 441 and flip-flop 572 to 0.

Signals 81505 and 57206 apply states 0 to the inputs of NAND gate 499 in fig. 14N. The output signal 49901 applies a state 1 to the output of the OR gate 495 whose output 49511 is applied to the input of an inverter 494. The output of the latter is in state 0.

The signal 49404 produced at the output of the inverter 494 resets the memory timer 611 to 0 (fig. 14X), one of the timers 133 of fig. 8. As the signal 49404 is applied to the CD input of a D flip-flop 502, the signal 50509 remains at state 0 and the signal 50508 remains at state 1. Signal 49404 is applied to the input of the NI 378 door of fig. 14G. The output signal 37808 is applied to an input of the AND / NI gate 278 (fig. I4D). When the signal 76208 is in state 1 (at time 100 of the cycle), the clock signal 27808 is in state 0 and the clock signal 27908 is in state 1.

As described above about a remote ISL cycle with reference to FIG. 14T, the selection signals 78111 and 78208 are both in state 0, thus selecting the inputs 0 of the multiplexers 783 to 798. The data outputs of these multiplexers appear in FIG. 14G as input signals from registers 525 to 528. The clock signal 27808 is applied to registers 525 to 528, thereby loading the data into the registers. Signal 27908 also sets flip-flop 271 to state 1, thereby preventing any new transfer from the remote ISL unit from producing an ISL cycle in the local unit in order to gain access to the local communication line.

The address of the source requesting the data is stored in the random access data file memories 364-366, 177, 389 and 647 (fig. 140). In this case, location 2 is read. As this is a remote memory response cycle, the signals 49014 and 90704 at the input of the NAND gate 402 are in state 1, and the output signal 40211 (read selection signal signal) is in state 0. Signal 49404 is in state 0 at the input of the NAND gate 403 and the output signal 40312 (signal 2 for selection of output reading) is at state 1. The source address was originally entered in location 2 during the first half-cycle of memory request. During the second half-cycle, the source address is extracted from memories 364-366, 389 and 647 and placed on the address line through registers 367, 368 and 391 (fig. 140), the multiplexers 157 to 160 and registers 507 to 509 (fig. 14E) as described above for a remote cycle.

The full memory request cycle toggle 487 was set to state 1 during the first memory request half cycle to prevent any new line data from being written to the memory location. The flip-flop 487 (fig. 14N) is reset to 0 since the signals 76208, 49511 and 39006, which are in state 1,

are applied to the input of the AND / NI gate 488. The output signal 48808 applies a state 0 to the input of the OR gate 283 whose output

28306 resets flip-flop 487 to 0. Signal 39006 is in state 1 since it is not a double memory cycle. A line cycle is then generated, which sends the data to the requesting source and ends the read cycle. The resetting of flip-flop 487 enables a new memory request cycle to be executed.

If the first reading half-cycle gives rise to a negative confirmation response, the local monostable flip-flop of 6 us 611 establishes at state 1 the time-out flip-flop 502. As the first half-cycle has already been requested and as the requester waits for a second half-response, a second half-cycle is generated, but with the indicators of incorrect parity and of reading of uncorrectable memory at state 1. This indicates to the requesting device that it must use the data received during the second half cycle and, in some cases, try again ^

When flip-flop 502 is set to state 1, a number of things happen. Signals 50209 and 43705 are applied to the input of an AND gate 501. As the ISL unit concerned is free, signal 43705 is in state 1. The output signal 50108 is applied to the input of clock of a D flip-flop 505 and this flip-flop is set to state 1. The output signal 50509, as described above, is the status bit which indicates that the time allocated to the memory has been exceeded. The signals 50209 and 50509 are applied in state 1 to the inputs of the NAND gate 503 whose output 50306 is applied to the input of the OR gate 620. Consequently, the time generator signal 62008 is located state 0. The signal 50306 is inverted by the device 504, the output 50408 of which is applied to the input of the OR gate 495 (fig. 14N). The output signal 59511 generates a local ISL cycle. This cycle is a second half-response from remote memory.

In fig. 14V, it can be seen that the signal 62008 is applied to the input of an AND gate 799. This prevents the full receiver flip-flop from putting the signal 79911 in state 1 so as to prevent the validation of the receiver 815 of FIG. 14AB. The initiation of remote ISL cycles is thus prevented. The signal 62008 is applied at state 0 to an OR gate 412 whose output 41206 is connected to the input of the NI gate 176. The output signal 17612 starts the sequence which puts the local cycle flip-flop at state 1 464 and the ISL 441 cycle flip-flop. Signal 41206 applied to the NI 608 gate puts the. output signal 10808 at state 1, which brings to state 1 the input of flip-flop 464. This ensures that flip-flop 464 is set to state 1, so as to prevent flip-flop 572 from find state 1.

Signal 46405 is applied to the clock input of register 490. However, signal 41206 is applied to state 1 at the input of OR gate 287. The output signal 28708 resets register 490 to 0 , thus taking precedence over clock signal 46405. Consequently, none of the local cycle functions is valid.

Even if a negative confirmation response had been received from memory, it would still be necessary to respond to the source. However, in order to indicate to the source that the data received by the source is not valid, the ISL unit generates an incorrect parity state.

Referring to fig. 14G, we see that the signal 62008 is applied to the input of an inverter 621. The output signal 62112 applies a state 1 to the input of the OR gate 349. The data parity error signal 34911 applies a state 1 at the input of a register 523. When the clock signal 27908 changes to state 1, the signal 52302 is applied to the inputs of the parity generators 521 and 522, thus generating an even parity signal. The output signal 34911 is applied to the input of an OR gate 392 whose output is connected to the input of the register 523. The output signal 52309 is applied to the transmitter 254 of FIG. 14B which then transmits it on the communication line as signal 10338 which indicates an uncorrectable error. The signal 49404 applied to the input of the NI 378 gate generates the validation signal of second line half cycle 37806 which is applied to the input of the AND / NI gate 278. This also receives the signal 76208 which generates clock signal 27808 for entering data and address into communication line registers as during the memory response cycle

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normal remote, which gives rise to a communication line request.

The operation restart request path is used for reading input / output request memory with test and lock, interrupt and a single input / output load function. Receiving an instruction to restart operation from the local communication line can cause the ISL unit to generate up to four cycles. The initial cycle is the local retry request cycle which transfers information from the local ISL unit to the remote ISL unit. The remote dunning request cycle then generates a remote pass line cycle. In the case of an exit instruction or an interrupt, this completes the execution of an instruction. As the stimulus path is used for instructions which require an actual response from the remote communication line, the local ISL unit responds on behalf of the remote intercom line with a line standby signal 26201 (fig. 14B). Then the actual response is obtained from the remote line and sent to the local ISL unit from where it is sent to the requesting source during a comparison cycle. In the case of a read instruction, once the first request half-cycle is generated on the remote communication line, the local ISL unit waits for the second remote response half-cycle as for a request memory reading.

As described for the memory request cycle, the selective access memories are addressed during the time DCN which initiated the remote response request cycle. If this instruction is a memory read instruction, a test and lock instruction or an input / output load instruction, it requires the translation of the data extracted from memories 706 to 715, which must be loaded in registers 718 and 719 These registers are synchronized with the signal 73806 obtained at the output of the inverter 738. The input signal 28106 is generated at the output of the AND / NI gate 281 (fig. 141). The inputs are signals 53910 and 58405. Consequently, the clock pulse is generated during data transfer mode when the flip-flop requests complete restart 584 (fig. 14N) is in state 1. This points to the data at the entry of registers 718 and 719.

The data path is described below with reference to FIG. 14R. The inputs 1 of the multiplexers 474 and 475 are selected since the memory reference signal 24414 is at state 0 at the input of the NAND gate 481. As it is a data transfer mode, the signal 53911 is in state 0 and consequently it is the input 0 of the multiplexers 472 and 473 which are selected. The most significant data bits 0 and 1 and the most significant address bits 0 to 7 are thus selected. Multiplexers 472 to 475 produce signals which are applied to the address inputs of memories 863 and 706. to 715 of fig. 14S.

The channel mask address signals are selected by the multiplexers 313, 314 and 315. The inputs 0 of these multiplexers are selected. Line address signals 8 to 17 are applied to terminal 0. Memory 276 is addressed with these signals and channel mask bit signal 27607 is applied to state 1 at the input of an AND gate 546. As it is not a test mode function, the signal 62203 is in state 1. The operational signal 53910 and the signal 48112 are applied to the inputs of an AND gate 550. As it is of an operational function, the two signals 53910 and 48112 are in state 1 and the output signal 55011 is also in state 1. The output signal 54608 is applied in state 1 to the input of OR gate 317 (fig. 14N). The output signal 31704 is applied in state 0 to the NI 566 gate, which brings the output signal 56608 to state 1.

As described above, the file selection signals 40802 and 41008 are applied in state 1 at the input of the AND gate 585. The signal 56608 is also applied in state 1 at the input of the gate 585. The flip-flop 581 is thus set to state 1 during the rise of the write validation signal 64405.

The file write selection signals 41106 and 40903 (fig. 140) are in state 0 since it is not a second half

line cycle, nor of a memory reference cycle. Signals 25914 and 24414 are in state 0. Signals 56506 and 47808 are also in state 0. Therefore, location 0 of the data and address files, 92 and 103 in fig. 8, is selected and when the write validation signal 64408 is applied, the information present on the local communication line is written to the memories with selective access.

The flip-flop 584 is set to state 1 by the signal 35602.135 ns after the start of the communication line cycle. Signal 58405 is applied to the clock input of a D flip-flop 615 (fig. 14Y). The signal 41811 is applied to the CD input of the flip-flop 615 which is set to state 1 when the clock signal 58405 rises. The output signal 61505 is applied to an input of the AND gate 614. The timer enable signal 91410 is in state 1 since it had not been set to state 1 with data bit 7 during the output timer instruction. The line rhythm signal 26102 produces 60 cycle pulses. The output signal 61412 is applied to the validation input G2 and to the input +1 of a counter 619 which has 60 cycle pulses. This has been described previously. This counter is used to detect the appearance of a malfunction in the remote ISL unit. If this decoder was not used, the local communication line would remain in standby mode.

As described above, signal 58109 generates a remote response request cycle which takes the contents of the data and address lines and when the transfer is complete, the complete transfer signal 92305 points to the data and the address information in the transmitters of the local ISL unit. The data is then routed to the multiplexers 783 to 798 of FIG. 14T as described.

The basic flow of information is described first in the following, then will be described the differences compared to this basic flow for the operations of reading of memory and loading input / output.

Referring to fig. 14U, the local restart request cycle signal 90002 is applied to the register 813. The output signal 81307 is transmitted as described above to the remote ISL unit. In it, signal 81606 is applied to the input of the AND / NI 578 gate (fig. 14V). The signals 57410 and 27108 are applied to the gate 578 and are at this time in state 1. The output signal 57808 is therefore in state 0. The delay line 374 is put into operation and the clock signals are engendered. The AND / NI gate 278 (fig. 14B) receives the remote function signal 57410, the cycle signal 100 76208, the operational signal 53910 and the remote restart request cycle signal 90201 are in state 1 for the remote cycle, this which generates signals 27808 and 27908. These signals start the synchronization of the remote communication line cycle and, as described above, during this cycle, the remote ISL unit addresses the designated device on the address line.

Gate ET 447 (fig. 14H) receives signals 42103, 58506 and 31808, all in state l. The output signal 44706 is applied to the input of the OR gate 629 whose output is connected to the input of the register 631. The output signal 63102 is applied to the input of an inverter 630 whose output 63006 is connected to the establishment input of flip-flop 452 so as to put this flip-flop in state 1. The signal 45309 is applied to the transceiver device 263 and places the signal 26201 on the local communication line. The local ISL continues to generate a wait response in this manner until a comparison cycle is initiated.

The confirmation signal 17803 received from the remote communication line, the negative confirmation signal 24814 or a standby signal 26303 are loaded into the register 413 (fig. 141). The output signals 41303 and 41306 are applied to an OR gate 415 the output of which is connected to the input of an AND / NI gate 570. For the duration of the signal 51515 which has been stored in the register 515, when the request has been placed on the remote communication line, it is in state 1. The output signal 57008 is applied to the input of an OR gate 270, so that is located at 5

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generated a signal 27006 which sets the solid line flip-flop 271 to state 0 (fig. 14G).

The remote response signal 57008 is applied to the input of the transmitting device 894 of FIG. 14AB. The output signal 89409 is applied to the set of resistors 658 of FIG. 14AC. The signal 65802 is applied to the connector 663 in order to be transmitted on the intercommunication line. The signal 66237 is received in the local ISL unit at the input of the transmitting device 733 (fig. 14AB). The output signal 73305 is applied to the clock input of the register 768 of FIG. 14P which stores the signals 73614 and 736Î6 which were generated on the distant communication line.

Signals 73614 and 73616 are applied to the inputs of a NAND gate 579. The output signal 57913 is applied to register 568. If neither a confirmation response nor a negative confirmation response has been received, then c is the wait response that is stored in register 568.

We now refer to FIG. 141. During the remote communication line cycle, the register 577 receives the remote confirmation signal, the register 577 receives the confirmation signal 17803 and the negative confirmation signal 24814. The register 413 also stores the signal 17803 and the signal 24814 The output of register 577, that is to say signals 57710 and 57707, are applied to the input of a transmitting device 913 (fig. 14AB). This transmits the signals 91312 and 91314 to the local ISL unit where they are applied to the inputs of a transmitting device 736 as signals 66241 and 66242. The output signals 73614 and 73616 are applied to the inputs of the gate NI 579 ( fig. 14P). If these two signals are in state 0, the output signal 57913 is in state 1 which is the regenerated standby response. The three remote response signals 57913, 73614 and 73616 are stored in register 568 when the remote response signal 73305 is received and changes to state 1 at input C of register 568. The response signal must be sent to the source requester on the local communication line and this is why a comparison cycle is generated, using the line comparator 93 of FIG. 8. The remote sampling signal 89610, the signal 55604 and the full receiver signal 87407 are applied to the inputs of an AND gate 543. As the three signals are at state 1 at this time, the output signal 54312 is in state 1, indicating that there is no cycle in progress in the local ISL unit.

The output signal 54312 is applied to the input of an AND gate 311 which also receives the no cycle signal 54312, the remote test signal 53914 and the comparison validation signal 30108, all these signals being in state 1. As the valid remote response signal 56803 applied to the input of an NI gate 301 is at state 0, the signal 30108 is at state 1. The signal 31106 is applied to the clock input of a flip-flop D 297 which is thus put in state 1. The output signal 29709 is applied to the input of an AND gate 299. The signals 41008,40802 and 43705 are all in state 1 also at the inputs of the AND gate 299. Signals 41008 and 40802, at state 1, indicate that the location requesting restart in the data file is selected. The output signal 29908 is applied to the CD input of a D flip-flop 318 which is thus put in the state 1 60 ns after the start of the DCN cycle by the signal 36008 and 60 ns after the state 1 of scale 437.

During the comparison cycle, the local ISL unit reads the information stored in the data and address files (fig. 140) and compares this information in the comparators 380 to 398 of fig. 14P, which constitutes the line comparator 93 of FIG. 8, with the information received from the intercom line. Line address signals 0-23 are applied to input B of comparators 384 to 386 and address signals 0-23 are applied to input A of these comparators. Data signals 0-15 are applied to inputs B and signals 0-15 are applied to inputs A.

The output signals 38009, 38109, 38209,38309, 38409,38509 and 38609 are applied to the input of the wired OR gate 379 which is terminated in a resistor 115 of 330 ß, this resistor being on the other hand connected to the potential + 5 V. If the information received from the intercom line is the same as that which is stored in the files of the ISL unit, the output signal 37901 is in state 1. If the two information does not are not the same, signal 37901 is in state 0, indicating that this information does not come from the source which started the original cycle or that this information comes from a cycle different from that which was originally started .

Signals 37901 and 31808 apply states 1 to the inputs of an AND gate 273. The output signal 27308 is applied to an inverter 272 whose output 27204 applies a state 0 to the input of an AND gate 542. If the two input signals are equal, the output signal 54212 is in state 0.

In fig. 14H, we see that the comparison signal, at state 1, is applied to the input of an ET 170 gate. This gate also receives signals 56807 and 59906 which are at state 1. The signal from output 17012 is applied to register 631 and stored in it when signal 35809 (135 ns) occurs. The output signal 63112 is applied to the input of an NI gate 130 whose output, at state 0, establishes flip-flop 433 at state 1. This generates an ACK confirmation signal as described above.

In the case of a negative NAK confirmation, signal 56815 is in state 1 at the input of NAND gate 171, as well as signals 17208 and 27308. The output signal 17112 is then in state 0 at the input of the OR gate 526 and the signal 53806 is in state 1 at the input of the register 631. The output 63105 is applied to the clock input of a flip-flop D 449 which is set to state 1. Signal 44909 is sent on the communication line as described above. In the case where the ISL unit has stored a wait response, signal 56810 is applied to the input of an AND / NI gate 174 which also receives signals 27308 and 59906 which are at this time in state 1 The output signal 17408 is applied to the input of an inverter 175 whose output 17506 is applied to the input of the register 631. The output 63109 of the register is connected to the clock input of the flip-flop 453 and this is thus placed in state 1. A waiting signal is thus placed on the communication line.

If the compared signals are not equal and the signal 37901 (fig. 14P) is in state 0, the signal 27308 is in state 0 and the signal 27204 is in state 1, which has to bring signal 54212 to state 1.

At the entrance of the ET / NI gate 174 (fig. 14H), the signals 54212, 53903 and 31910 are at this time at state 1. Consequently, the output signal 17408 is at state 0. This has the effect of putting flip-flop 453 to state 1 as described above and the waiting signal is placed on the communication line.

If the operation is a restart operation following a negative confirmation response or an interrupted central processor address operation, signals 53902 and 32008 are in state 1 at the input of an AND gate / NI 541. As the signal 54212 applies a state 1 to another input of this gate 541, the output signal 54106 is in state 1 at the input of the gate NI 538. The output of this one is applied to the input of register 631. The output signal 63105 puts flip-flop 449 at state 1, thus applying an indication signal to the communication line.

The end of the local dunning request cycle for a write instruction proceeds as follows. In the case of an ACK confirmation response from the remote unit, signal 56807 (fig. 14H) is in state 1. As described above, this signal carries signal 17012 in state 1, which causes the confirmation signal to be sent to the requesting source on the intercom line. The signal 17012 is in state 1 as well as the write signal 36609 (fig. 14N). The AND / OR gate 286 has its output signal 28608 in state 0 and the output 29308 of the OR gate 293 is therefore also in state 0. The flip-flop JK 584 is reset to 0, interrupting the circuit dunning request to serve another instruction.

In the case of a confirmation response for a read instruction, the signal 17012 is applied to a door input

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AND 732 which also receives the file write signal 80504 (fig. 14AB). The 73203 output signal is sent to the remote ISL unit. The signal 73309 received in the remote unit (fig. 14N) puts the flip-flop 593 in state 1, which allows the second half-cycle to be sent to the local unit.

The operation also ends during a read or write instruction by the appearance of a negative confirmation response NAK. In this case, the output signal 17112 (fig. 14H) is in state 0 at the input of the OR gate 536. The output signal 53603 is applied to the input of the OR gate 293 (fig . 14N), which has the effect of resetting the flip-flop 584 to 0 as described above.

During the comparison cycle, the waiting signal 17508 is applied to the input of register 631 (fig. 14H). The output signal 63109 is applied to the clock input of a D flip-flop 632 (fig. 14N). The output signal 63209 is applied to the other input of the NAND gate 559. The output signal 55906 sets flip-flop 581 to state 1, so that another restart request cycle is initiated as described upper.

The operation retry request cycle is repeated until a confirmation or negative confirmation response is sent to the source.

The effect of issuing a wait response is to restart the instruction to maintain flip-flop 584 (fig. 14N) in state 1 at this time. Referring to fig. 14Y, it can be seen that the signal 58406 is at state 0, which validates the counter 619 which is part of the unit of rhythm and state logic 133 of FIG. 8. Signal 61412 applies 60 Hz pulses to inputs +1 and G2 of the counter. If the wait response remains for more than 120 ms, then signal 61907 is brought to state 1, which has the effect of putting flip-flop 599 to state 1. Signal 61608 is in state 1 since the confirmation signal has not been received. Signal 59906 (fig. 14H) is in state 0 at the input of gate ET 170. The output of this gate is therefore in state 0, which inhibits the confirmation response.

Similarly, the signal 59906 is applied to the input of an OR gate 172. The output signal 17208 is in state 0 at the input of the NAND gate 171. The output signal 17112, in state 1, inhibits the negative confirmation signal. Signal 59906 at the input of AND / OR gate 174 inhibits a wait response and, therefore, there is no response at all. This causes the line cycle time in the local ISL unit to be exceeded and the local central processor is informed that there is no resource for the channel number. Even if the ISL unit is configured for this address, the decision to exceed the time limit is taken and the software then has to investigate why the device is not operational at this time or why the ISL unit was initially configured incorrectly to generate such an error that resulted in a negative response for the dunning request cycle. In fig. 14G, it can be seen that signal 39310 was in state 1 as if it were a read request. The output signal 52408 was in state 0, thus selecting the address inputs of registers 525 to 528. Also, the data signal 51303 was in state 0 since there was no cycle d 'interrupt or memory read request cycle. Signal 51303 is received as address bit 18 at state 0 when the response cycle is received from the external device. This brings the signal 47808 to the output of door 478 (fig. 140) in state 1.

When the second line half cycle is received, signal 25914 is in state 1. Line blocking is not established and therefore signal 24102 is in state 1, as well as signal 1 of file write selection 40903. Signals 47603, 56506 and 47808 are in state 1, so that file write select signal 41106 is in state 0. Consequently, the information is written in location 1, which is the location for the response response of the address and data files of fig. 140, which correspond to the file registers 92 and 103 of FIG. 8.

In fig. 14N, we see that the signals 41008,40903 and 44006 apply states 1 to the inputs of the AND gate 598. The output signal 59808 is applied to state 1 at the input CJ of a flip-flop JK 595. The signal Write line validation 64405 is applied to the clock input of this flip-flop, so that it is set to state 1. When the local ISL unit sends an ACK confirmation signal to the remote ISL unit, flip-flop 593 is set to state 1 since the clock signal 73309 is brought to state 1 as described above. Signals 59509 and 59305 are applied to a NAND gate 587 whose output 58703 is applied to an inverter 588.

We now refer to FIG. 14V which illustrates the cycle generator 146 of FIG. 8. The signal 58703 is applied to the input of the NI 645 gate whose output 64508 is applied to an input of the AND / NI gate 388. The other input of this gate receives the signal 92306 at state 1 The output signal 38808, at state 0, generates the local cycle and the ISL cycle by setting the flip-flops 464 and 441 to state 1 as described above. The signal 58810 is pointed at the input of the register 490 whose output 49007 is applied to an input of the AND gate 590, which has the effect of generating the local stimulus response cycle signal 59012. At this time, the ISL cycle generates the time signals which appear at the output of the delay line 374 as described above. The data path is identical to that established for the memory response cycle. As in any remote cycle, the data is sent to the local ISL unit when the complete transfer latch 923 of FIG. 14U is in state 1. The signal 59012 is applied to the input of the NI 909 gate whose output 90910 is applied to the input of the register 813. The output 81315 is the signal generated by stimulus response operation which is transmitted to the local ISL unit. The signal 66221 is received by the device 815 of FIG. 14AB. The output signal 81503 initiates the remote cycle in the local ISL unit as described previously, the data path is identical to that which is established for the remote memory response cycle as described above.

In the local ISL unit, flip-flop 584 is reset to 0 as follows (see fig. 14N). The signals 59211 and 76208 are applied to the inputs of the AND / OR gate 286. The output of this is applied at state 0 to an input of the OR gate 293. The output signal 29308 resets flip-flop 584 to 0 .

In the remote ISL unit, the local retry response cycle is executed at this time. The flip-flop 595 and the flip-flop 593 are reset to 0 (fig. 14N). The signals 59012 and 32712 are applied to the inputs of a NAND gate 596 whose output 59603 applies a state 0 to the input of an OR gate 294. The output signal 29411 sets flip-flops 593 and 595 to 0.

For a read instruction, flip-flop 616 (fig. 14Y) in the local ISL unit is in state 1 since an ACK confirmation signal is received, which brings signal 56807 to state 1. The signal 27308 is also in state 1 after a comparison cycle having revealed an identity. Signal 61608 applies a state 0 to the CD input of flip-flop 599, which prevents the flip-flop from being set to 0. Counter 619 is reset to 0 when signal 58406 is in state 1. During a read operation, after receipt of the request confirmation, the ISL unit waits for approximately 240 ms. The signal 61912 produced at the output of the counter 619 is applied to the input of an inverter 618 whose output 61808 is applied to the clock input of the flip-flop D 456. This flip-flop is thus set to the state 1. The output signal 45605 is applied to state 1 at the input of the AND gate 455.

When the ISL unit becomes free as described above, the signal 43705 is applied to state 1 at the other input of the AND gate 455. The output signal 45511 then sets flip-flop 459 to state 1. The output signal 45909 is the input / output timer status bit.

Signals 45909 and 45606 are applied to the inputs of a NAND gate 457. The output signal 45711 is applied to the input of an inverter 458. Signal 45811 is applied to the input of an OR gate 620 whose output 62008, at state 0, is the timeout signal of the unit 133 of FIG. 8. The function of this

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signal is to simulate a parity error as described above.

Referring to fig. 14N, it can be seen that the signal 46108 is applied to the input of the OR gate 592 which generates a replacement remote stimulus response cycle signal.

The sequence described in the foregoing is generated by means of the counter 619 in FIG. 14Y. The normal termination of the instruction resets this counter to 0 when the flip-flop 615 (request for restarting completed) is set to state 0. This occurs under the command of signal 29308. At the input of AND gate 614, signal 61505, at state 0, inhibits time pulses of 60 Hz 26102.

The signal 59211 (remote stimulus response) and the end of pulse signal 37712 are applied to the inputs of the AND gate 594. The output signal 59406 is applied to the input of the NI gate 432 whose output 43201 resets the rocker 456 to 0. This flip-flop is not reset to 0 before an instruction set to 0 output has been issued in order to reset the sequencer bit to 0.

The input / output load instruction requires two cycles. The first cycle, a local operation restart request cycle takes place in the local ISL unit and the second cycle, remote operation restart request cycle, takes place in the remote ISL unit. This instruction is unique in that the memory address data is part of both the address and data fields. The input / output load instruction has two parts. The first part is the output register portion. Address signals 0-7 represent the memory address used by the controller during an operation. Address signals 8-23 are data signals 0-15. The second portion of the instruction is the same as any other input / output instruction.

As described above, during a DCN cycle the memory translation memories 706 to 715 (FIG. 14S), which correspond to the memory address translation memory 125 of FIG. 8, see their content loaded in the memory reference registers 716 and 717 which correspond to the memory reference register 126 of FIG. 8. During the loading of a normal input / output instruction in the data file, this instruction must be an operation retry path instruction. We will see that the memory translation bits are loaded into registers 718 and 719, which correspond to register 127 of FIG. 8, instead of being in registers 716 and 717. Signal 73806 executes this selection. Referring to fig. 141, it can be seen that the signals 53910 and 58405 are applied in state 1 to the inputs of an AND / OR gate 281. The output signal 28106 is applied to the inverter 738 of FIG. 14S. The output thereof is connected to the clock inputs of registers 718 and 719 so as to point to the input of these registers the data coming from memories 706 to 715. During the local operation restart request cycle which follows the loading of the data and address memories of FIG. 140, signal 48603 is in state 0 at the validation terminals of registers 718 and 719, which validates the outputs of registers 718 and 719.

Also, during the local operation restart request cycle, the address signals 18, 19, 21 and 22 and the signal 64706 are applied to the inputs of the NAND gate 829 (fig. 14L). When all these inputs are in state 0, the output signal 82906 is in state 1 and the output of AND gate 828 applies a state 1 to an input of AND gate 827. The other inputs of this gate receive two address signals, namely signal 20 with address 15301 and signal 23 with address 15601. If these two signals are in state 1, the output signal 82706 is in state 1 at the input of the inverter 826 whose output 82610 is therefore in state 0 and indicates that a hexadecimal number 9 is indicated by the signals 20 to 23 with address 15301, 15401, 15501 and 15601.

Referring to fig. 14R which illustrates the memory address multiplexer 100 of FIG. 8, it can be seen that the memory reference signal 24414, the signal set to 0 by the master 47006 and the operational signal 53910 are applied to the inputs of a NAND gate 481. As the signal 24414 is at state 0 , the selection input of the multiplexers 474 and 475 are in state 1. The selection signal 53911 is in state 0, so that the inputs 1 of the multiplexers 474 and 475 are selected. Consequently, the line data signals 0-1 18905 and 19010 are selected as signals 8-9 with addresses 47507 and 47409. The line address signals 0-7 are applied to input 0 of the multiplexers 472 and 473, these signals being selected as signals 0-7 with address 47212,47209,47207, 47204, 42312, 47309, 47307 and 47304.

In fig. 14S, it can be seen that the address signals 0-9 are applied to the address selection inputs of the memory address translation memories 706 to 715. The data signals 6-15 of data 33901 to 34801 have been entered in the memories 706 to 715 at the address designated during configuration mode. The output signals 70607 to 71507 are applied to the inputs of registers 718 and 719.

Referring to fig. 14T, it can be seen that the signal 82706 is applied to the selection input of the multiplexer 930, thus selecting the address translation signals 8-9 72801 and 72901.

In fig. 14Z, we see that the signal 82610 was applied at state 0 to the input of the OR gate 911. The output 91108 of this is applied to the selection inputs of registers 832 and 835, thus selecting the inputs 0 The address translation signals 0-7 72001 to 72701 are the remaining eight bits of the address translation memories. The rest of the cycle is the same as any other input / output instruction cycle. Data is transferred to the remote ISL unit and normal data and address paths are established to present information on the remote communication line.

The only route remaining to be established during the local operation retry request cycle is the route for executing memory test instructions. The purpose of such an instruction is to check a bit on the memory card connected to the communication line. This bit must be checked before it is determined whether the instruction can be executed or not. Even if the system is configured to read each memory location, we know whether the lock bit is at state 1 or not. The correct response is generated and returned in a similar fashion to that of an input / output output instruction. Since this is a memory instruction, it requires the memory address translation path to properly address the memory and write the information to the correct locations in the file.

For file write selection logic, the test instruction has a unique function on the communication line. This function is a memory reference and line lock instruction. This instruction is not a second line half cycle. The signal 25914 is in state 0, the signal 24102 is in state 0 and the signal 24414 is in state 1. In this way, the location 0 of the file is selected for the information path.

In fig. 141, it can be seen that the signals 62606 and 86307 are applied to the inputs of an AND gate 548. The signal 86307 is the memory activity bit extracted from the memory 863 of FIG. 14S which corresponds to the memory 125 of FIG. 8. Signal 62606 is the test operation signal. The output signal 54308 is applied to an input of a NAND gate 480 (fig. 14N). The signal 24414 applies a state 1 to the other input of the gate 480. The output signal 48011 is applied to an input of the gate NI 566 whose output 56608 is applied to an input of the gate AND 585. The signals 40802 and 41008 are at state 1. The output signal 58506 conditions the flip-flop 581 at state 1 when the clock signal 64405 goes to state 0, which has the effect of initiating the cycle of request for recovery of local operation for the test instruction. As in previous operation retry request cycles, the memory address translation data shared in the memories 125 of FIG. 8 should be loaded into registers 718 and 719 as described above. The test instruction must transfer the data to the local registers in fig. 14Z in the same way as for an input / output load instruction.

As this is a local operation restart request cycle, signals 58306 and 64706 (fig. 14Z) are in state 1 at the inputs of the NI 873 gate. The output signal 87311 therefore applies

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a state 0 at an input of the OR gate 911 whose output 91108 is at state 0. This same state 0 is found at the selection inputs of registers 832 and 835, which has the effect of selecting the translation signals d 72001 to 72701. The signal 87311 is applied to an input of the OR gate 912, thus selecting the address translation signals 72801 and 72901 as well as the memory reference signal 64706 and the file byte 38910. The part data from this instruction travels along the normal data path to the register transmitters and driver. The other address bits come from the normal address line. During the following remote cycle in the remote ISL unit, some special control lines must be in state 1 on the remote line.

Referring to fig. 14G, it can be seen that the file locking signal 80401, which was generated in the local ISL unit, is applied in state 1 to an input of an OR gate 466. The output signal 46603 is applied to the input of an AND gate 443. Since this is not a test mode, the other input of gate 443 receives the signal 53906 in state 1. The output signal 44311 therefore applies a state 1 at the entry of register 523. The line lock function is a key for reading the test bit in memory. The bit is checked with the blocked line. The bit is checked and if it was previously set to 1 in memory and cannot be used at this time, a negative confirmation response NAK is launched, which ends the instruction. The response is sent to the local ISL unit for use by the software. If the bit has not been set to state 1, then it is set to state 1 at this time and an ACK confirmation response is sent to the local ISL unit and the specific operational instruction can be executed.

There are various types of test instructions during which certain things are done, which do not affect the operation of the ISL unit. There is a case in which if the test instruction receives a wait response because the memory is busy serving another information transfer or because the memory is in the refresh cycle. The waiting response signal 26303 obtained from a remote cycle is loaded into register 413 (fig. 141) as described previously. The output signal 41310 is applied to the input of the NAND gate 328 (fig. 14D). Signals 52305 and 51515 apply states 1 to the inputs of the AND gate 602 and the output signal 60203 is applied to an input of an OR gate 633. The output signal 63303 is applied to the other input of the NI gate 328. The output signal 32806 is applied to the clock input of the D flip-flop 564. The output signal 56406 is applied to the input of the OR gate 562, which has the effect of initiating a request cycle of communication line.

The interrupt signal which is sent from a controller to a central processor on the remote line controls the establishment of the local operation restart path as follows. The interrupt instruction is a normal input / output output instruction. It is an instruction which crosses the ISL unit and which requires special attention in that the interrupt request can be initiated by a device having a higher priority level than the one which already uses the route of restart of operation in the ISL unit. Therefore, if the route is busy, the information must be processed before the interruption is made. Therefore, the interrupt request must be detected and a response must be made after 135 ns in the cycle when the confirmation, negative confirmation or wait signal is sent on the line.

Referring to fig. 14M, we see that the line address signals 8-12 are applied to an input of a NAND gate 277. The address signal 13 is applied to an inverter 195 whose output 19504 is applied to an input from AND gate 321 which also receives signal 27705. Since this is not a memory reference instruction, signal 24414 is in state 1. If bits 8-13 of address are in state 0, the output of gate 321 is in state 1. Signal 32106 is applied to one input of AND gate 320, the other input of this gate receiving the channel mask signal 54608. This last signal comes from the AND gate 546 of FIG. 14R. An input of this door 546 receives at state 1 the signal 27607 obtained at the output of the memory 276. The output signal 32008 is applied to the CD input of a flip-flop D 430 which is put in the state 1 when signal 58405 rises at time 135 ns of the cycle. This flip-flop at state 1 indicates that the interrupt request is accepted by the ISL unit. If, at this moment, the signal 54212 (fig. 14H) is in state 1, this state 1 would be applied to an input of the AND gate 422 whose other input receives the signal 32008. The output signal 42203 is applied to the input of register 631. Signals 54212 and 32008 are also applied to the inputs of AND / NI gate 541 whose output signal 54106 is applied to an input of NI gate 538. The output signal 53806 is applied to the entry of register 631, which gives rise, as described above, to the emission of a negative confirmation response NAK on the communication line. The signal 63119 is applied to the input of an inverter 537 whose output 53702 applies a state 0 to the input S of the flip-flop D 429 (fig. 14X), this flip-flop thus being set to state 1. The output signal 42905 is applied to an input of the AND gate 395, the other input of which receives the signal 58406. When the path becomes free, the signal 58406 is set to state 1. The output signal 39503 is applied at the input of a monostable rocker 451 and the output 45113 thereof is applied to the input of a receiver excitation device 258 (fig. 14B) which applies a signal 10406 of 30 ns on the line of communication, thus indicating to the source device, that is to say the requesting device which has received the negative confirmation response, that it has to restart the interrupt request to this ISL unit now that the path is no longer busy. If the path for the interrupt request is not busy, the response sent to the source device is a wait response as described above. This signal indicates to the source device that it has to continue sending its request until it receives a different response. In the meantime, the interrupt request is processed in the remote ISL unit.

In fig. 14M, it can be seen that the central processor interrupt signal 32106 and the line write signal 26510 are applied to the inputs of an NI 640 door. The output signal 64013 is applied to the input of an inverter 641 whose output 64104 is applied as a file write signal, to the input of memory 366 of FIG. 140.

In fig. 14W, the destination address multiplexer 749 has its input 0 selected. Consequently, the signals 14-17 of address 14601 to 14901 are selected. The central processor channel address signals 74912, 74909, 74907 and 74904 are applied to the address selection inputs of memory 754. This stores the translation address for the central processor, which was previously loaded by a configuration instruction when the ISL unit was in configuration mode. The output signals 75411.75409, 75407 and 75405 are applied to terminal 0 of the register 840. The signals 43008 and 58306 are applied in state 1 to the inputs of the NAND gate 910. The output signal 91003, at state 0, selects input 0 of register 840. The output signals 84015, 84014, 84013 and 84012 are applied to the inputs of excitation devices 839 and 841 which constitute the interface devices 115 of FIG. 8, from which these signals are sent to the remote ISL unit. These signals represent the address of the central processor that originally loaded the ISL unit.

Signal 91003 is applied to an input of a NAND gate 904 (fig. 14M). The other input of gate 904 receives signal 2 of data 33501. Signals 0.1 and 3-5 of data 33401 to 33801, on the other hand, are applied to the inputs of a NAND gate 903. The bits 0-5 of data on line 117 of fig. 8 are in state 0 in order to indicate that a central processor interrupts another central processor.

The output signals 90305 and 90413 apply states 1 to inputs of an AND gate 755. Another input of this gate receives the signal 58306. The output signal 75506 applies a state 1 to an input of an OR gate 927 whose output signal 92711 is applied to the input of register 845 (fig. 14AA). The output signal 84505 is applied to the input of the excitation device 844 (fig. 14AB). The output signal 84407 is applied to the interface line and is received

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at the input of the excitation device 803 in the remote ISL unit as signal 66244. The output signal 80303 is applied to the wired OR gate 926 of FIG. 14AA.

The output signal 92601 is applied to the CD input of a flip-flop D 925 (fig. 14W). During the remote restart request cycle in the remote ISL unit, signal 90201 is at state 1 at the input of AND gate 899. At time 100 of the cycle, signal 76208 goes to state 1 and is applied to the other input of door 899. The output signal 89911 is applied to the clock input of a flip-flop D 925 which is thus set to state 1 until the request cycle for next remote raise. The function of the flip-flop 925 has been described previously.

The data signals 6-9 of data 33901 to 34201 are applied to the inputs 1 of the multiplexer 756 which constitutes the source address register 136 of FIG. 8. These inputs are selected because the signal 53910 which is applied to the selection input of the multiplexer 756 is in state 1. The output signals 75604, 75607, 75609 and 75612 are applied to the address inputs of the memory 757 which stores the translation information to select the appropriate central processor source address. This memory corresponds to the memory 113 of FIG. 8.

The signal 92601 which is applied in state 1 to the selection inputs of the multiplexer 780, which constitutes the data multiplexer 137 of FIG. 8, selects source address translation signals 75705, 75707, 75709 and 75711.

Signals 90201 and 39310 are applied to the inputs of the ET / NI 524 door (fig. 14G). As the file write signal 80701 was in state 1, as described above, the output signal 39310 is in state 0. The signal 52408 at the output of gate 524 therefore selects input 1 of register 526, which constitutes the multiplexer / data register 138 of FIG. 8, so that the data signals 6-9 78007, 78004, 78009 and 78012 are selected. The output signals of the multiplexer 526 as well as the outputs of the other multiplexers in the cycle are found on the communication line, which ends the execution of the interrupt instruction.

The address registers 507 to 509 of FIG. 14E, which constitute the address multiplexer register 111 of FIG. 8, store the address as it was sent by the local ISL unit. As for the data multiplex signals, they are applied to the inputs 1 of the registers 525, 527 and 528 of FIG. 14G. During a write operation, as described above, the data signals 6-9 are applied to the inputs 1 of the register 526. During a read operation, the inputs 0 of the registers 525, 526 and 527 select the address of channel of this ISL unit. These are the signals from the hexadecimal rotary switches 101 to 104 of FIG. 14J. As described above, the signal 51303 is in state 1 for a read operation and in state 0 for a write operation.

In fig. 14D, it can be seen that the signals 57410, 76208, 53910 and 90201 are applied in state 1 to the inputs of the AND / NI gate 278, which has the effect of generating the clock signals 27808 and 27908. The signal 27908 points the address signals 0-31 in registers 507, 508 and 509 in fig. 14E, the signals 0-15 of data in registers 525 to 528. The signal 27908 also sets flip-flop 271 to state 1, thus inhibiting any other remote ISL unit.

The output and input interrupt control commands passing through the ISL unit are detected so that a special translation of the address of the central processor can be performed. The architecture performing the detection of an input / output interrupt command with which the function codes 02 and 03 are associated respectively is illustrated in FIG. 14M. The AND gate 811 detects signals 18-21 of address at state 0 during the interrupt command instruction. Signal 64706 is in state 0 since it is not a memory reference cycle. The output signal 81101 is applied in state 1 to an input of the AND gate 810. The signal 53910 is in state 1 and if the signal 22 with address 15501 is in state 1, the output signal 81012 is in state 1 for the hexadecimal function code 02 and 03. The output signal 81012 is applied to an input of the OR gate 927 which generates the translation signal 92711 sent to the remote ISL unit at the same time as the data and address information during the local retry request cycle. This process has been described above. For an exit interrupt instruction, the local retry request cycle is identical to the cycle of any other exit instruction and the address and data information travels along the same paths. The only difference is that the translation signal 92711 is sent to the remote ISL unit. In this, during the execution of the remote retry request cycle, the data follows a slightly different path for data signals 6-9 33901 to 34201.

Referring to fig. 14W, it can be seen that the output signals of the multiplexer 756, that is to say the signals 0-3 of source address of central processor 75604, 75607, 75609 and 75612 are applied to address the memory 757 which stores the data translation. As described above, the output signals from memory 757 are selected by the multiplexer 780 because the signal 92601 is in state 1. The output signals 78004, 78007, 78009 and 78012 are applied to the inputs 1 of the multiplexer 526 of fig. 14G. At the output of this multiplexer is obtained the information containing the translated central processor address which allows the controller to know which central processor should be interrupted. If this central processor is configured in the ISL unit, this unit acts as an agent for this interrupt when it is launched. For an input interrupt control instruction, the local restart request cycle is selected in the local ISL unit, this cycle being followed by the remote restart request cycle in the remote ISL unit.

As described above for the remote dunning request cycle in the remote ISL unit, the flip-flop 925 in FIG. 14W is in state 1, thus generating the signal 92505 which is applied to the input of the gate ET 928. During the remote stimulus request cycle, the first half of the request is transmitted on the communication line as described above. When the controller sends the second half-response, this remote ISL unit generates the local stimulus response cycle. The output signal 92806 is in state 1, thus selecting the input 1 of the multiplexer 749. The flip-flop 925 remains in state 1 until a remote restart request cycle is generated without the signal 92601 is at state 1. But this cannot happen before there has been a response in the case of an input instruction. The output signals of the multiplexer 749 address the memory 754, the contents of which contain the reverse translation of the memory 757 so that the original data obtained during the execution of the command to interrupt the output is sent to the central processor.

Signal 92306 in fig. 14AA selects inputs 1 of registers 851 and 853. Register 851 selects signals 0-1 of central processor destination 75411 and 75409 which are applied to the outputs of data signals 6 and 7, respectively signals 85114 and 85113. Register 853 selects signals 2-3 of central processor destination 75407 and 75405 which are applied to the outputs of data signals 8 and 9, respectively signals 85312 and 85313. Registers 851 and 853 also receive signals 5,4, 10 at their inputs -11 of data 78707, 78807, 79307 and 79409. The outputs of registers 851 and 853 are applied to excitation devices which return the signals to the local ISL unit with the rest of the data sent by the source central processor when the exit interrupt command instruction has been issued. As a result, the device requesting the input interrupt receives the data during the resulting communication line cycle.

The memory system can be configured to send two second half responses (two words of data) for a single memory request to increase transfer capacity. The first word is sent with the double extraction signal 10404 in state 0 during a first second communication line half-cycle. About 300 ns later, a second second half-cycle is started with signal 10404 in state 1.

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Referring to fig. 14N, it can be seen that the signals 40903, 41106 apply states 1 to the AND gate 500 which also receives the signal 44006 to the state 1. The output signal 50008 is applied to an input of the NAND gate 373 whose another input receives the double extraction signal 21006. The write line validation signal 64405 applies a state 1 to another input of gate 373. The output signal 37308 is then in state 0 and sets the flip-flop D

352 at state 1.

The output signal 35206 applies a state 0 to the input of the NI 351 door (fig. 14V). The output signal 35106 is applied to the input of the register 490 whose output signals 49014 and 49015 define the memory response cycle. The signals 35205 and 35308 are applied to the inputs of the AND / NI gate 388. As the signal 35308 is at state 1 at this time, the output signal 38808 at state 0 causes the state 1 of the flip-flops 464 and 441 as described previously, which has the effect of generating the ISL and local cycles.

In fig. 14N, it can be seen that signals 32502 and 49015 apply states 1 to the inputs of the AND gate 354. The output signal 35411 is applied to the clock input of a D flip-flop 353 which is thus set to state 1 during the rise of signal 35411 since the signal 35205 applied to the terminal CD of this rocker is in state 1. The setting in state 1 of rocker 353 causes the setting of rocker 352 if 0 the complete transfer signal 64602 is in state 0, which is the normal case. The signal 35308 is applied to the clock inputs of registers 367, 368 and 391 (fig. 140), so that the output signals from memories 364, 365, 366, 177, 647 and 389 are stored as described above. The data is entered into registers 367, 368 and 391 for the first memory response cycle, which frees the memory response location in memories 364 to 366,177,647 and 389 for the second memory response cycle.

During the first local memory response cycle, signals 49303 and 37712 are applied in state 1 to the inputs of NAND gate 375 (fig. 14N). The output signal 37511 is applied at state 0 to the input of the OR gate 350, the output signal 35007 of which is applied to the reset terminal 0 of the flip-flop 353, the latter being thus reset to 0 at the end of the first response cycle. During the second memory response cycle, the output signal 50008 is always in state 1 and it is applied to an input of the AND gate 496 which receives at its other input the signal 21104 in state 1. The output signal 49611 is then in state 1 and puts the flip-flop 492 in state 1 when the write validation signal 64405 drops.

As can be seen in fig. 14V, signal 49206 applies a 0 state to NI gate 351, which produces another memory response cycle as described above. The output signal 35411 is then brought back to state 1, but since the flip-flop 352 is in state 0, the signal 35205 is in state 0. The flip-flop 353 is therefore not in the state 1. The circulation of data and address signals in the ISL unit is identical to that which is carried out during the first memory response cycle.

During this first response cycle, the data was stored in registers 367, 368 and 391. The clock signal 35308 was brought to state 0 at the end of this cycle. During the second cycle, the registers are loaded with the data obtained when the scale

353 is in state 1 and when signal 35308 is in state 1.

The ISL unit may cause interrupts on its own account in some cases if the interrupt level register is loaded with non-zero information and when the correct central processor address is loaded in the channel registers. The interrupt channel register 819 and the interrupt level register 857 contain the data which is used by the ISL unit to generate the interrupts. Interrupt cycles are generated by the ISL unit and are not interrupts that pass through the ISL unit.

If an error for nonexistent memory has been detected or if the time limit allocated to the sequence controller in the remote ISL has been exceeded and the interrupt authorization function has been activated

in state 1 for the nonexistent memory or the sequencer of the sequence controller, then the output of the gate ET / NI 895 (fig. 14X) is brought to state 0. Likewise, if an error for nonexistent memory or a timeout allocated to the sequence controller is detected in the local ISL unit, then the output of the NI 824 gate is brought to state 1, which puts flip-flop 823 at state 1. The signal inhibition 82106 is in state 1 as described above. The flip-flop 823 is set to state 1 and the output signal 82309 is applied to the input of the AND gate 607. When the ISL unit becomes free, the signal 43705 is in state 1 while the output signal 60708 is in state 0, which puts flip-flop 427 in state 1. Signals 43108 and 42504 are in state 1. Signal 42708 is applied in state 0 to door entrance OR 412 (fig. 14V). The output signal from this door applies a state 0 to gate 287, the output signal 28708 of which at state 0 maintains register 490 at state 0. Signal 41206 is applied to gate NI 608 and the output 60808 of this door is applied to the CD input of the flip-flop 464. The signal 41206 is also applied to the NI gate 176 whose output 17612 is applied to the AND gate 604. The rise of the output signal 60408 puts the flip-flops 464 and 441 at state 1, thus generating the local and ISL cycles and the time signals at the output of the delay line 374. It will again be noted that no particular local cycle is generated since the register 490 is maintained at state 0.

Signals 42709 and 76208 apply states 1 to the inputs of AND / NI gate 278 (fig. 14D). The output signal 27808 generates a communication line cycle and transmits data and address information over the line. Signal 42708 is applied at state 0 to the selection input of multiplexer 731 (fig. 14M), thus selecting inputs 0. The output signals 73107, 73109, 73112 and 73104 represent the central processor channel number to interrupt; these signals are applied to the input of the multiplexer 159 of FIG. 14E. The inputs 0 of the multiplexer 159 are selected since it is not a second line half-cycle, the signal 37806 being in state 0. The multiplexers 157, 158 and 190 are not validated and their outputs are at state 0 since the validation signal 42709 is at state 1. Signal 42708 is also applied to state 0 at the reset terminal at 0 of register 507, thus setting bits 0-8 d address in state 0. The other address bits are in state 0 except bits 14 to 17 which are the only bits set to state 1 at the inputs of registers 508 and 509.

In fig. 14T, it can be seen that the signal 42708 is also applied to the NI gate 801. As this signal is at state 0, the output signal 80108 is at state 1, thus selecting the inputs 3 of the multiplexers 783 to 798. Data signals 0-5 are in state 0. Data signals 6-9 indicate interrupt channel signals 6-9. Data signals 10-15 indicate interrupt level signals 0-5, i.e., these signals indicate the level at which the ISL unit should interrupt the central processor.

In fig. 14G, it can be seen that the signal 42709 applies a state 1 to the input of the AND / NI gate 524. The output signal 52408, at state 0, selects the inputs 0 of the registers 525, 526 and 527. However, input 1 of register 528 is selected since signal 42709 is in state 1 at the input of AND gate 372. Consequently, register 528 selects signals 12-14 of data 79607, 79509, 97909 and 79809.

The register 527 selects the data signals 10-11 51303 and 51406. The signals 42709 and 79307 are applied to the input of the AND gate 529. As the signal 42709 is in state 1 and as the signal 86606, applied to OR gate 513 is at state 0, signal 51406 reflects the state of data signal 79307. Similarly, signals 42709 and 79409 are applied to the input of AND gate 530. The output signal thereof is applied to the OR gate 514 whose output 51406 reflects the state of the data signal 11 79409.

Referring to fig. 14J, we see that signals 10307 and 39716 are applied to NAND gate 437. Signal 10307 reflects the state of channel address signal 8 since signal 39716 is at this time at state 0.

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The rotary switches 101, 102 and 103, which correspond to the rotary switch 140 of FIG. 8, have their only output signals 9-16 applied to the inputs 1 of the multiplexers 435 and 436. The output signals 1-8 of these switches are applied to the inputs 0 of the data registers 525 to 527 of FIG. 14G.

The information presented on the communication line when the communication line cycle is generated therefore gives the address of the central processor to be interrupted and the channel address of the ISL unit as well as the level at which the interruption of the processor. central must take place.

In fig. 14G, it can be seen that the signals 42709 and 80701 are applied to the inputs of the OR gate 454. The write signal 45411 is applied to the input of the register 523 whose output 52306 is sent on the communication line in order to indicate that the interruption concerns a writing cycle.

The ISL unit receives from the central processor either a confirmation response or a negative confirmation response. In the case of a negative confirmation response, the central processor sends the signal 10406 on the line and in this case the interrupt request must be regenerated. The negative response signal 24814 is applied to the input of the register 413 (fig. 141) at the end of the signal 51608. The output signal 41307 is applied to the clock input of the flip-flop D 431 (fig. 14X), which has the effect of putting this flip-flop in state 1. This flip-flop thus inhibits any other interruption originating from the ISL unit until the signal 10406 is received from the central processor on the local communication line . The signal 10406 is the resumption signal of the interrupt function that the central processor generates when it can accept an interrupt. When the signal 10406 is generated, all the devices which have previously recorded an interruption (following a negative confirmation signal) regenerate their requests for interruption. The signal 10406 is received by the receiver excitation device 258 of FIG. 14B. The output signal 25806 is applied to the NI 428 gate (fig. 14X) whose output 42801 is at state 1 and therefore puts the flip-flop 431 at state 0.

If a confirmation response is received, the signal 41302 is applied to the input of the NI gate 426. The output signal 42610 returns flip-flop 823 to state 0. However, flip-flop 623 remains in state 1. Consequently, signals 43705, 43108, 42504 and 82309 are applied in state 1 to the inputs of the AND gate 607. The output signal 60708 puts the flip-flop 427 in state 1, which has the effect of starting the interrupt cycle as described above. The sequence continues until a confirmation response is received. The signal set to 0 by the master 44806 applied to the input of the NI 426 door returns flip-flop 823 to state 0.

It remains to describe various logical functions. Referring to fig. 14H, it can be seen that signals 44512, 33108 and 21710 are applied in state 1 to the inputs of a NAND gate 555. These signals indicate that during an ISL instruction, a data parity error has been detected. The output signal 55508 is applied at state 0 to an input of the OR gate 536. The output signal 53603 is applied to the input of another OR gate 293 (fig. 14N), which has the effect reset flip-flop 584 to 0 by means of signal 29308. Signal 55508 is also applied to the input of NI gate 538 (fig. 14H), which has the effect of producing the negative confirmation signal as described above .

Signals 44006 and 25914 are applied to the input of AND gate 606. The output signal 60606 generates a confirmation signal indicating that during the second line half cycle, the ISL address has been detected.

We now refer to FIG. 14J. The signals 93212 and 10114 are applied to the inputs of a NAND gate 610. The output signal 61010, in state 1, authorizes a function to reset the master launched on the local line bound for the ISL unit distant. The signal 61010 is applied to the input of the receiver excitation device 242 of FIG. 14B for transmission over the communication line.

In fig. 14Y, the D flip-flop 601 in state 1 returns the flip-flop 584 of FIG. 14N at state 0. The flip-flop 601 is set to state 1 when an error occurs by exceeding the time allowed. The signal 17208 is applied to the inverter 173 whose output 17310 is applied to the CD input of the flip-flop 601 so as to set the latter to state 1 when the signal 27204 rises.

An inverter 557 in fig. 14P receives signal 87407. When this signal is at state 0, it indicates that a remote sampling pulse has been received and that a remote cycle must be carried out. The output signal 55712 is applied to an input of the NAND gate 285 whose other input receives the signal 21510. When this signal is at state 1, it indicates that it is not a line cycle. The output signal 28503 is applied to an input of the OR gate 296, another input of which receives the signal 29803. When the latter signal is at state 0, it indicates that the comparison cycle has ended. The output signal 29608, at state 0, returns flip-flop 297 to state 0. Signals 32712 and 27308 are applied to the inputs of NAND gate 300. At time 135 ns in the comparison cycle when this comparison has detected an equality, the output signal 30011 is brought to state 0 and applied to the input of the OR gate 298. The other input of this gate receives the signal 83006 which is the signal set to 0 by the master ISL. The output signal 29803, in state 0, indicates the end of the comparison cycle.

In fig. 14G, it can be seen that the signal 86513 and the signal 44311 are applied to an AND gate 642. The output signal 64206 is applied to another input of an OR gate 452 whose other input receives the signal 37806. The signal of output 45206 is applied to the input of register 515 and output 51507 thereof generates the second line half-cycle signal 10402 which is sent over the communication line. During the write instruction, signal 51507 indicates that the memory must reset the test bit to 0.

The test mode and test mode cycle of the ISL unit will now be described. There are two cases of test mode: the memory loop and the input / output loop. The memory loop uses the configuration of selective access memories. The normal cycle is basically controlled by the configuration loaded in the local ISL unit and in the remote ISL unit. The ISL unit is configured so that it responds to addresses launched on the line. The remote ISL unit receives the address of the local ISL unit and returns this address to the latter. This is why, in the case of the memory loop, the memory cycles associated with a memory loop instruction are identical to those which have been described previously for the information transfer mode of the ISL unit. The test mode bits if they are in state 1 allow the memory cycle to be carried out in the ISL unit. When it receives a memory request, the local ISL unit generates a local memory request cycle which causes the generation of a remote memory request cycle in the remote ISL unit. As the latter is configured to accept the address which has been sent on the communication line, it in turn generates a local memory request cycle as if it had received this address from an outdoor unit. In the local ISL unit, a cycle of remote memory request is then generated. In short, the local line cycle generates a cycle going from the local ISL unit to the remote ISL unit and back to the local ISL unit. A write operation or a read operation can be generated. For a write operation, the data is written to the memory location which has been addressed by the local ISL unit. The original address is only valid for the local ISL unit. This address is then translated by the local ISL unit into an address which is not valid on the remote communication line. The remote ISL unit replies to this address and translates it back into an address usable on the local line. If the memory request cycle involved is a data request, the local memory sends this data to the local ISL unit. This response generates a local memory response cycle in the local ISL unit, a cycle which is confirmed as described above, then the remote memory response cycle is generated in the remote ISL unit and the latter sends the address. ISL on the communication line. The remote ISL unit receives the address and generates the local memory response cycle which in turn generates the remote memory response cycle in the unit

5

10

15

20

25

30

35

40

45

50

55

60

65

640,645

48

ISL local and sends the data back to the central processor that requested the data. Data was requested from memory, sent to the local ISL unit, then sent by the local ISL unit to the remote ISL unit, then returned to the local ISL unit to generate eight cycles and establishment of all normal data and address paths. This completes the memory loop.

The establishment of the input / output loop is done in a similar manner except that the operation restart path is used and that the test mode bits must be set to state 1. The test mode bit must be set to state 1 in the local ISL unit and in the remote ISL unit, io the remote test mode bit must be set to state 1. Unlike the memory loop, the mode bit d The remote test should not be set to state 1, but it can be to avoid another transfer of data from the remote communication line to reach the ISL unit. The remote test mode bit inhibits all responses except the ISL unit's own response. For normal input / output instruction, the channel address and function code are used to address a memory location in the local ISL unit after the request has been transferred from the local unit to the remote unit and returned to the local ISL unit. The location address of 20

memory is used for both a read operation and a write operation. For a read operation, the requested data travels to the local ISL unit via the operation retry path, is sent to the remote ISL unit, and then returned to the local ISL unit as for a memory loop. However, an operation retry request cycle is used. A local dunning request cycle is first treated as a normal input / output instruction. This request is transferred to the remote ISL unit in which the remote dunning request cycle is generated. This results in a communication line cycle 30 for a channel address which is not present on the remote line, but is configured in the channel activity bit memory of the remote ISL unit. The remote ISL unit generates a wait response and a local operation restart request cycle. The wait response generates a response which is sent to the local ISL 3s unit, which then attempts to restart the same instruction as described above for a normal input / output instruction. The local operation request request cycle generated by the remote ISL unit gives rise to the generation of a remote operation request request cycle in the local ISL unit. This cycle replaced on the local line 40 modifies the channel request instruction into a memory reference instruction. The memory reference signal is brought to state 1 so that the data accompanying this instruction are actually sent to a memory if it is a write operation and, if it is of a read request, the memory 45 supplies the data. In the case of a write operation, the data is written to a location that the central processor can read by generating a comparison instruction in order to check whether the data received is the same as that which has been sent. As this instruction is confirmed by memory, the so confirmation signal is returned to the remote ISL unit via the remote response signal as described above. By initiating the operation retry request cycle from the local ISL unit, the instruction receives a confirmation response which is returned to the local central processor which requested the read or write cycle 55. The confirmation signal sent from the local memory to the local ISL unit is then sent to the remote ISL unit and then returned to the local ISL unit. Data is sent from the local ISL unit to the remote ISL unit, and then returned to the local ISL unit. The cycle essentially takes place as a 60 memory request cycle except that it uses the operation retry path and the channel address and function code as the memory location. The data uses all channel data paths. During the input / output loop, the data bit 10 is in state 0 and therefore for a read operation, the address bit 18 is in state 0 for the memory response cycle. The response from memory is loaded into the restart response location and generates a local operation restart response cycle. This cycle is confirmed because it is a second line half cycle and it generates a remote operation stimulus response cycle in the remote ISL unit which, in turn, generates the stimulus response cycle. of local operation as for a memory response. This cycle is again confirmed and generates a remote operation restart response cycle in the remote ISL unit. This last cycle sends the data to the central processor which has requested it and this ends the execution of the input / output loop instruction.

To see the doors which control the specific test functions, refer to fig. 14G. The signal 53906 is applied at state 0 to the AND gate 443. This inhibits the locking signal 44311 and thus invalidates the function. As described above, this signal controls certain functions when launching instructions concerning the memory. The signal 53907 is applied to the AND gate 627. The output signal 62708 is applied to the OR gate 625 and the output signal 62508 is applied to the input of the register 523. The output 52305 of the register is sent on the line so to indicate that it is a line memory cycle. The gate 627 receives the signal 53914. In the local ISL unit, this signal is in state 1 and in the remote ISL unit, it is in state 0, thus blocking the memory reference in the ISL unit distant. This allows an input / output instruction to be changed to a memory reference instruction. The signal 90201 allows a memory reference during the execution of a remote operation restart cycle when the signal 90101 is in state 1.

In fig. 14R, it can be seen that the signal 53915 at the input of gate 622 is at state 0 in the local ISL unit and at state 1 in the remote ISL unit. The other input of gate 622 receives the signal 51707 which is in state 1 when the remote ISL unit does not generate a communication line cycle. When the remote ISL unit receives a request for an operation restart path from an external source, the gate 622 produces a signal at state 0. This signal is applied to the gate 546 whose output 54608 is brought to l state 0, thereby inhibiting the remote ISL unit.

Signal 62203 is applied at state 0 to an input of AND gate 626 (fig. 141). The output signal 62606, in state 0, inhibits the output of the AND gate 548, which inhibits the detection of a bit of memory activity. An external source is thus prevented from initiating a memory request cycle.

During an input / output loop mode, the signal 90201 is applied to state 1 at an input of the NAND gate 623 (fig. 14P). Signal 56802, which is in state 1 when the remote response is detected from the remote ISL unit, is applied to another input of gate 623. Signal 53907 is applied to the last input of gate 623 The output signal 62308, at state 0, puts flip-flop 297 at state 1. When the ISL unit becomes free, signal 29908 is brought to state 1, thus conditioning the setting to state 1 of the flip-flop 318 during the rise of the clock signal 36008. A comparison cycle is thus launched, which sends on the local line the remote response received by the local ISL unit. The signal 53914 is applied to state 0 at the input of the AND gate 445 (fig. 14K). The output signal 44512, in state 0, inhibits the ISL unit connected to one or the other communication line and prevents it from responding to an instruction.

49

640,645

Table 1

Types of line transfer cycles and file usage

Register

Register

Type of reserve entry cycle

mnemonic mnemonic

Memory read request

MRQ

MRS

Memory write request

MRQ

-

Memory read response

MRS

-

I / O output request

RRQ

I / O input request

RRQ

R RS

Interruption

RRQ

I / O input response

RRS

Memory reading, test and posi

tction

RRQ

R RS

Memory reading, blocking

zero

MRQ

MRS

Memory writing, blocking

zero

MRQ

-

Table 2A

Signals

Keyboard control

Surgery

Number

Primary

Secondary

BSWRIT

BSSHBC

BSMREF

cycles

T

F

T

Memory writing

1

CPU + eu

SAME

F T

F T

T F

Reading response memory

1 1

CPU + eu MEM

MEM CPU + eu

T

F

T

Memory writing

1

CPU + eu

SAME

F T

P

T

F F

I / O reading and response

1 1

CPU

had had

CPU

T

F

F

I / O address output

1

CPU

had

T

F

F

IOLD data output

1

CPU

had

T

F

F

Interruption

1

had

CPU

Table 2B

Address lines

Data lines

0 23 Address

0 15 Data

0 23 Address

0 7 8 17 18 23 Number Usage secondary variable channel

0 9 10 15 Number Primary variable channel usage

0 15 Data

640,645

50

Table 2B (continued)

Address lines

Data lines

0 23 Multiplet address

0 7 8 15 Data Data

0 7 8 17 18 23 Secondary channel number

0 7 8 17 18 23 Number Usage secondary variable channel

0 9 10 15 Number Primary variable channel usage

0 15 Data

0 7 8 17 18 23 Address Number Channel module code 'secondary function

0 15 Address

0 7 8 17 18 23 Number Code func-secondary channel tion

0 15 Data

0 7 8 17 18 23 MBZ number secondary channel

0 9 10 15 Number Primary source channel level

Table 3

Communications line operations

Type of operation

Source

Destination

Number of cycles

Instruction search

CPU

Memory

2

Search operand

CPU

Memory

2

Operand memorization

CPU

Memory

1

Memory reading

Controller

Memory

2

Memory writing

Controller

Memory

1

I / O output order

CPU

Controller

1

I / O entry order

CPU

Controller

2

Interruption

Controller

CPU

1

CPU = Central processor.

Table 4

Communication line interface signals

Signal type

Lines

Function

Memonic

Synchronization

1

Line request

BSREQT-

1

Data cycle now

BSDCNN-

1

Confirmation

BSACKR—

1

Negative confirmation

BSNAKR—

1

Waiting

BSWAIT—

Information

16

Data

BSDT00— to

BSDT15-

51 640 645

Table 4 (continued)

Signal type

Lines

Function

Memonic

24

Address

BSAD00— to

BSAD23 -

Order information

1 1 1 1 1 1

Memory reference Multiplet Line write

Second half of the line cycle Blocking

Double extraction

BSMREF-BSBYTE— BSWRIT— BSSHBC-BSLOCK— BSDBPL-

State / Error

1 1 1 1 1 1 1

Memory error (red) Memory error (yellow) Left data parity Right data parity Address parity (bits 0-7) Logic test Output Logic test Input

BSREDD-

BSYELO-

BSDP00—

BSDP08 -

BSAP00—

BSQLTO—

BSQLTI—

Interruption of mobilization

1 1 1 1 1 1 1 1 1 1

Mobilization interruption network Mobilization interruption network

BSAUOK +

BSBUOK +

BSCUOK +

BSDUOK +

BSEUOK +

BSFUOK +

BSGUOK +

BSHUOK +

BSIUOK +

BSMYOK +

Various

1 1 1 1

Primary (master) at zero Power supply EN Interruption resumption Clock 50-60 Hz

BSMCLR— BSPWON + BSRINT— BSTIMR—

Table 5 ISL unit interface signals

Type

Function

Number of lines

Local code

Remote callsign

Address

24

LCAD00 + to

LCAD23 +

RMAD00 + to

RMAD23 +

Data

16

LDAT00 + to

LDAT15 +

RMDT00 + to

RMDT15 +

Repairable memory error (yellow)

Byte transfer

Line writing

Memory reference

Blocking

Double primary extraction at zero Interruption recovery

1 1 1 1 1 1 1 1

LCYELO +

LCBYTE +

LCWRIT +

LCMREF +

LCLOCK +

LCDBLE +

BSMCLR—

BSRINT +

RMYELO +

FILBYT +

FILWRT +

FIMREF +

FILOCK +

FILDBG +

BSMCLR—

BSRINT +

ISL

Remote sampling Transfer performed Generate memory request Generate memory response

1 1 1 1

RMTSTB + XFRDUN + GENMRQ - GENMRS -

RMTSTB + XFRDUN + GENMRQ— GENMRS-

640,645

52

Table 5 (continued)

Type

Function

Number

Call sign

Remote local area code

Generate request to reopen an operation

ration

1

GENRRQ—

GENRRQ-

Generate response to revive op

ration

1

GENRRS—

GENRRS-

Remote line acknowledgment

1

RMACKR +

RMACKR +

Line negative acknowledgment

distant

1

RMNAKR +

RMNAKR +

Response raise

1

RMRESP +

RMRESP +

Confirmed response

1

ANSWAK +

ANSWAK +

Translate channel number

1

XLATOR—

XLATOR—

Remote function

1

FMTFUN +

RMTFUN +

ISL at zero

1

MYMCLR—

MYMCLR—

Connected in pair

1

TWINCN—

TWINCN—

Address parity error

1

LCAPER +

LCAPER +

Parity error given

1

LCDPER +

LCDPER +

Nonexistent memory

1

NOXMEN—

NOXMEM—

Exceeding the time allotted to the

Remote sequence controller

1

WTIMOT +

WTIMOT +

Exceeding the time limit

for an answer

1

RMTOUT—

RMTOUT—

Table 6 on next page

Table 7 IOLD instruction format

I. Address line 7 8 17 18

23

Address bits 0 to 7

MBZ

Destination channel number

HR = 09

2. Data line 0 15

Address bits 8 to 23

3. Address line

17 18

23

Destination channel number

FC = OD

Table 8 Line-ISL input / output instructions

Type

Function code

Instruction

I / O output

01

Command word

03

Interrupt command

27

Rhythm mask reset /

interruption

OB

Address mask output

11

Data mask output

I / O input

02 10 18 26

Interrupt command Data mask input Status word

Device identification

4. Data line 0 15

Range

53

640,645

Table 6

WORD NO. DEC

WORD NO. SAME

E 5 <

UT

AOS DFÏÏ

. E

WORD NO DEC

WORD NO. SAME

5

3IT. = OS 0FÏÏIF

WORD NO. DEC

WORD NO. SAME

BIT POS SOTIE

WORD NO. DEC

WORD NO. SAME

BIT

POS EXIT

WORD NO-DEC

WORD NO. SAME

BIT. POS 50RT1F

3

2

1

0

3

2

1

0

3

2

1

0

3

2

1

0

32

1

0

0

0

52

34

103

67

1

1

1

1

154

9A

205

CU

1

53

35

104

G8

155

98

206

THIS

2

2

54

36

105

69

156

9C.

207

CF

3

3

55

, 37

106

6A

157

90

208

DO

4

4

56

38

107

6B

158

9E

209

or

5

5

57

39

108

6C

159

9F

210

D2

6

6

58

3A

109

6D

160

AO

211

03

7

7

59

3B

110

6E

161

Al

212

D4

8

8

60

3C

111

6F

162

A2

213

05

9

9

61

30

112

70

163

A3

214

06

10

AT

62

3E

113

71

164

A4

215

D7

11

B

63

3F

114

72

165

AT 5

216

D8

H

1

0

12

VS

64

40

115

73

166

A6

1

1

1

0

217

D9

13

D

65

41

0

0

0

1

116

74

167

A7

1

1

1

1

218

DA

14

E

66

42

1

0

0

0

117

75

168

AT 8

219

DB

15

F

67

43

1

0

at

1

118

76

169

A9

220

DC

16

10

68

44

119

77

170

AA

221

00

17

11

69

45

120

78

171

AB

222

OF

18

12

70

46

121

79

172

AA

223

DF

19

13

71

47

122

7A

173

AD

224-

FO

20

14

72

48

123

78

174

AE

225

F1

21

IS

73

49

124

7C

175

AF

226

E2

22

Ifa

74

4A

125

7D

178

RO

227

F3

23

17

75

4B

0

1

p

1

126

7E

177

C1

223

F4

24

10

1

0

1

vs

75

4C

127

7F

178

VS?

229

F5

25

19

77

40

128

80

179

RI

230

Ffi

1

1

not

26

1A

78

4E

129

81

180

B4

231

F7

1

1

i

27

1B

79

4F

130

82

181

B5

232

Ffl

28

1 C

8p

50

1

1

D

0

131

83

182

B6

233

E9

29

1D

81

51

1

1

0

1

132

84

B3

B7

234

EA

30

1E

82

52

133

85

184

B8

235

EB

31

1F

83

53

134

86

185

B9

236

EC

32

20

84

54

135

87

186

BA

237

ED

33

21

85

55

136

88

W

BB

238

EE

34

22

85

56 '

137

89

188

BC

239

FF

35

23

87

57

138

8A

189

Comics

240

F0

36

88

58

1

0

1

0

139

8B

190

BE

241

FI

37

25

89

59

140

8C

191

BF

242

F?

38

26

1

1

1

0

90

5A

141

8D

192

C0

243

F3

39

27

1

1

1

1

91

5B

142

8E

193

THIS

D

0

P

1

244

F4

40

28

92

5C

143

8F

194

C2

245

F5

41

29

93

5D

144

90

195

C3

246

F6

42

2A

94

5E

145

91

196

C4

247

F7

43

2B

95

5F

146

92

197

C5

248

F8

44

2C

96

60

147

93

198

C6

249

F9

45

2D

97

61

148

94

199

C7

250

FA

46

2E

S8

62

149

S5

200

C8

251

FB

47

2 F

99

63

150

96

201

C9

252

FC

48

30

100

64

151

97

202

IT

253

FD

49

31

101

65

152

98

1

0

1

0

203

CB

254

FE

50

32

102

66

1

1

1

0

153

99

204

CC

255

FF

51

33

640,645

54

Table 9 Active status switch, (passive

Order

Active

Passive

Reserved

In connection

Stop

Test

Denomination

01

x

x x

x x

Command word

03

x

x

x x

Ri x interrupt command

x x

x x

x

Resetting rhythm / interrupt mask

OB

x

x

x x

Address mask output

11

X

x

x x

Mask output data

02

X

x

x x

Interrupt command

10

X

x

x x

Input mask data

18

X

x x

x x

x

Status word

26

X

x x

x x

x

Device identification

Table 10

Table 12 ISL status bits

BitO

Bit 1

Bit 2

Bit 3

Bit 4

1

X

X

X

X

Initialize

0

1

X

X

X

Stop

0

0

X

X

X

Reprise

0

X

X

X

1

NAK / relaunch

0

X

1

X

X

Reference references not memory as memory reference

0

X

X

1

X

Remote ISL unit only responds to its own line cycles

Table 11

Bit 0 = 1

Memory stop timer reset to zero

Bit 1 = 1

I / O stop timer reset

Bit 2 = 2

Reset status bit and con timer

sequence monitor

Bit 3 = 1

Reset rhythm timer restart

Bit 4 = 0

Sequence controller block timer

local and interruptions

Bit 4 = 1

Controller controller rhythm validation

local sequence and interruptions

Bit 5 = 0

Interruption of control rhythm interruptions

their distant sequence

Bit 5 = 1

Validation of con timer interruptions

local sequence governor

Bit 6 = 0

Blocking remote interrupts

Bit 6 = 1

Validation of remote interrupts

Bit 7 = 0

Disabling I / O timers and stopping

relaunch

Bit 7 = 1

I / O rhythm validation and restart stop

Bit 8-15

RFU

Bit

Identification

Definition

0

In direct connection

The two ISL units

are operational

under pressure

1

Remote interrupt

This bit is a status bit

compound representative

three dis status bits

aunts and subject to

two mask bits.

This bit is true if:

rhythm mask

of controller

remote quence to

state 1 (code bit 5

function 27)

AND

rhythm time

room controller

remote quence

exceeded (status bit 6

remote)

OR

remote error mask

at state 1 (bit 6 of

function code 27)

AND

remote resource no

existing (bit 13

remote status)

3

Active switch

The local unit is in

active state

6

Cunt rhythmor

This condition is

se trôleur

subject to mask

local quence:

cunt rhythm

time exceeded

sequence monitor

local (bit 4 of code

function 27)

8

Restart stop

The stop rhythm

restart of operation a

expired

55

640,645

Table 12 (continued) ÎSL status bits

Bit

Identification

Definition

9

Input / output stop

I / O stop timer has expired

10

Stop reading memory

Memory read stop timer has expired

13

Nonexistent resource

The ISL unit received a NAK signal from memory for one of its unblocked memory operations

14

Line parity

The ISL unit has detected an incorrect parity for a transfer intended for it

2

4

5 7

11

12 15

RFU

Table 13

Cross-reference table between the functional blocks of fig. 8 and the diagrams of fig. 14

Figure

Headline

Reference number in fig. 8

14A

Communication line interface

14B

Data and control transceivers

90/141

14C

Address and control transceivers

98/123

14D

Communication line control

14E

Multiplexer and line address register

111

14F

Data line and address

105/117

14G

Multiplexer and data register

138

2 p.m.

Line response control logic

141

Mode control register (539)

Remote response logic

135

I4J

Hexadecimal rotary switch and address comparator

140/99

14K

Read-only memory and function code decoder

102/106

14L

Master reset generator

94

Figure

Headline

Reference number in fig. 8

14M

Channel and In Level Registers

132/134

terruption

Address multiplexer for bits 14-17

112

14N

Full file and cycle command

140

Data and address files

103/92

File File Transmitter

121

data (367-368)

14P

Line comparison

93

14Q

Select access memory counter

108/118

tif and command

14R

Channel address and memory

100/101

Memory of channel masks

142

(276)

14S

Address translation memories

125

memory

Memory reference register and

126/127

input / output change

14T

Internal data multiplexer

129

14U

Transfer cycle logic

14V

Cycle generator

146

14W

Professional destination address register

114/131

central stopper and work memory

duction

Proces source address register

136/113

central sister and translation memory

tion

Data multiplexer (780)

137

14X

Sequence controller rhythm

133

and interrupt command

14Y

Memory status and input rhythm /

133

exit

14Z

Excitation device / receivers

104/115

intercommu line address

notification

14AA

Excitation device / receptors

116/139

intercommunicating line data

cation

14AB

Excitation device / receptors

ISL command

14 AC

Line connectors and terminators

intercommunication

Table 14

Generic name

Model

Drawing board

Reference number

T ransmitter-receiver

26S10 * 1

14B

263

Pro ROM

5603A * 2

14K

399

grammable

Toggle switch

7414

14X

261

Hexadecimal schmitt

Decoders / demulti

74154

14K

397

4/16 line plexer

4-bit type D registers

74173

14K

400

5

10

15

20

25

30

35

40

45

50

55

60

65

640,645

Table 14 (continued)

Generic name

Model

Drawing board

Reference number

Type D hexadec scales

74174

14G

515

cimal

Mono multivibrators

74221

14Y

611

stable double

Type D octal scales

74273

14G

523

Positive NAND gate

74H21

14V

583

4 double entrances with

manifold outputs

open

NAND AND positi doors

74LS00

14R

622

ves 2 quadru inputs

ples

NI positive doors

74LS02

14N

482

2 quadruple inputs

Hexadecimal inverters

74LS04

140

408

Gate AND positive

74LS08

2 p.m.

606

2 quadruple inputs

Positive NAND gate

74LS10

14G

465

3 triple entries

Type D quadru scales

74LS175

14P

568

ples

Reversible counters

74LS193

14X

636

synchronous (binary

with zero setting)

NAND AND positi doors

74LS20

14X

607

ves 4 double inputs

Positive AND gates

74LS21

14X

634

4 double entrances

Selectors / multiplexers

74LS258

14D

436

quadruple data

2-input multiplexers

74LS298

14G

526

quadruples with

memory

Reversing doors AND /

74LS51

141

570

OR

4x4 register files

74LS670

140

365

Type D double scales

74LS74

14N

487

edge-triggered

positive with establish

prior and setting

to zero

NAND AND positi doors

74S00

140

476

ves 2 quadru inputs

ples

NI positive doors

74S02

14D

292

2 quadruple inputs

Hexadecimal inverters

74S04

14B

241

Positive AND gates

74S08

140

409

2 quadruple inputs

NAND AND positi doors

74S10

140

411

ves 2 triple entries

J-K double die scales

74S112

14D

534

interlocked by front

negative with establish

prior and setting

to zero

Positive AND gates

74S11

14D

256

3 triple entries

Generic name

Model

Drawing board

Reference number

NAND AND positi doors

74S133

14D

520

ves 13 entries

Line exciters

74S140

141

216

50 ohms with function

NAND AND positive

4 double entrances

Selectors / multiplexers

74S153

14N

396

double data

4 lines / 1 line

Selectors / multiplexers

74S157

14E

159

2/1 line data

quadruple (outputs

data without inverting

if we)

Type D qua scales

74S175

14K

418

druples

NAND AND positi doors

74S20

14V

645

ves 4 double inputs

NI positive doors

74S260

2 p.m.

130

5 double entrances

Positive OR gates

74S32

14G

513

2 quadruple inputs

Type D octal scales

74S373

140

367

Doors AND / OR / NO

74S51

141

281

Doors AND / OR / NO 4-

74S64

14D

278

2-3-2 entries

Type D double scales

74S74

2 p.m.

433

edge-triggered

positive with establish

prior and

reset

OU-exclusive doors

74S86

14L

251

2 quadruple inputs

Parity generator

86S62 * 3

14B

232

Selective access memory

93425A * 4

14R

276

1024 addresses

Comparator

93S47 * 5

14P

384

Delay line 125 ns

DLY125T * 6

14V

374

Delay line 150 ns

DLY150T * 6

141

358

Delay line 200 ns

DLY200T * 6

14L

467

Delay line 40 ns

DLY6040 * 6

14D

255

Manufacturers:

* 1 - Advanced Micro Devices, Sunnyvale, California. * 2 - Intersil, Sunnyvale, California.

* 3 - Signetics, Sunnyvale, California.

* 4 - Fairchild, Mountain View, California.

* 5 - Fairchild, Mountain View, California.

* Honeywell

Specially manufactured for use in the intersystem linkage unit. These devices are described in the following publications, available to the public:

1. Document No. 11040109, Rev. AT.

2. Specification No. 60067122, Rev. AT.

3. Specification No. 04550072, Rev. vs.

4. Specification No. 04550075, Rev. vs.

5. Specification No. 04550079, Rev. B.

6. Specification No. 04550081, Rev. B.

56

5

10

15

20

25

30

35

40

45

50

55

60

65

57

640,645

Table 15

1

Address (24 lines)

2

Data (16 lines)

3

Byte

4

Unrepairable memory error (red)

5

Repairable memory error (yellow)

6

Memory reference

7

Negative acknowledgment

8

Waiting

9

Acknowledgment of receipt

10

Line request

11

Data cycle now

12

Interruption resumption

13

Primary memory empty

14

Writing

15

Blocking

16

Second line half cycle

17

Parity given (right multiplet)

18

Parity given (left byte)

19

Connected voltage

20

Logic test out

21

Logic test in

22

Double extraction

23

Link interruption (10 lines)

24

Address parity

25

Time synchronization

Table 16

Legend fig. 11

1

Address (24 lines)

2

Data (16 lines)

3

Repairable memory error (yellow)

4

Byte transfer

5

Line writing

6

Memory reference

7

Blocking

8

Double extraction

9

Primary memory at zero

10

Interruption resumed

11

Remote sampling

12

Transfer completed

13

Generate memory request

14

Generate memory response

15

Generate request to restart operation

16

Generate response to restart operation

17

Remote line confirmation

18

Remote line negative confirmation

19

Response to restart operation

20

Response confirmation

21

Convert channel number

22

Remote function

23

ISL at zero

24

Connected address parity

25

Address parity error

26

Parity error given

27

Nonexistent memory

28

Remote controller - time exceeded

29

Dead remote unit - time exceeded

R

74 sheets of drawings

Claims (9)

640,645 2 1. Data transfer unit allowing, using a second identical but distant unit, information transfer between bidirectional buses, one local, the other remote, to which are coupled processing devices. data, these units operating to establish a serial transfer channel and each transfer of information being accompanied by address information identifying at least the proper destination of the information and, in the case of information transfer requiring a response, also by address information identifying the device using the requested information, characterized in that, to be transparent to information transfers between the local bus (12) and the remote bus (21) to which the transfer unit of remote data (ISL-11) is linked and to allow bidirectional information transfers between buses, it includes: a) acquisition means comprising a first unidirectional interface of the local bus (90, 91, 96, 98) and several registers (92, 103) which are connected to it and which define storage locations allocated for the information received from the bus local, these locations being ordered according to a priority principle, the acquisition means entering the information asynchronously on the local bus (12) during a first operating cycle, known as the acquisition cycle, b) information detection means (100,101,125,142) for detecting, in the interface of the local bus, information addressed to the data transfer unit or to a device coupled to the remote bus (21) and thus allowing the acquisition means to acquire this information, the detection means operating during the acquisition cycle, c) address translation means (100,113,114,125,131, 136) coupled to the registers, which selectively convert address information stored in the registers into address information relating to the remote bus (21), the conversion being performed during the acquisition cycle, d) a first unidirectional interface for the remote transfer unit (105,115,117, 121,126,127,129,139) which, during a following cycle, the acquisition cycle transmits the stored information and any corresponding translated address information to the remote transfer unit, e) a second unidirectional interface for the transfer unit (105,116,117) for receiving information from a device coupled to the remote bus (21) through the remote data transfer unit (11), in response to a request for this information made beforehand by a device coupled to the local bus (12), f) a second unidirectional local bus interface (111, 123, 138, 141) for transferring this response information to the local bus (12) together with address information relating to the device coupled to the local bus, having formulated the request, and g) a logic control device, electrically connected with the first and second unidirectional interfaces of the local bus, the information detection means, the address translation means, and the first and second unidirectional interfaces for the remote data transfer unit, reacting, by means of acquisition, to the detection of first control signals on the local bus to form the configuration of the detection means and of the translation means and to the detection of second signal command on the local bus to perform a two-way transfer of information from and to the local bus. 2. Data transfer unit according to claim 1, characterized in that the registers comprise a data file register (92) and an address file register (103), each having several common allocated storage locations and each being coupled to the logic controller, such that, in order of priority, a first of the locations allocated in each register stores information relating to a memory response, a second of the locations allocated in each register stores information relating to a memory request, a third of the locations allocated in each of the registers stores information relating to a response from a non-storage device and a fourth of the allocated locations stores information relating to a request from a non-memorizing device. 3. Data transfer unit according to one of claims 1 or 2, characterized in that it includes a busy bit location associated with each storage location and coupled to the logic controller, the state of this bit defining to the logic controller whether the respective storage location is occupied or free. 4. Data transfer unit according to one of the preceding claims, characterized in that it is arranged so that, when transfers to be made through the unit are identified, the information detection means (100,101,142,145 ) send signals to the logic controller which identify first and second half cycles relating to the transfer of information and that a comparator (93), which is coupled to the logic controller, the second interface for the remote data transfer unit and the registers, compares information received by the second interface for the remote data transfer unit with information received from the local bus and stored in the registers during a previous operating cycle, the comparator allowing the second interface of the local bus to transfer the information contained in the second interface for the remote data transfer unit to the local bus. 5. Data transfer unit according to claims 2 and 4, characterized in that the information detection means comprise a channel address decoder (142) and a memory address decoder (125), the decoder of channel addresses responsive only to address information that does not relate to memory so as to compel the logic controller to treat the acquired information as a non-memory transfer and the decoder d memory addresses responsive only to memory address information so as to compel the logic controller to treat the acquired information as a memory transfer. 6. Data transfer unit according to one of the preceding claims, characterized in that the address translation means comprise: a) a selective access memory (RAM, 125) for translating address information received from the local bus into memory addresses for the remote bus, b) a destination central processor (CPU) address translation selective access memory (RAM, 131) for selectively converting local central processor (CPU) address information appearing on address lines into addresses for central processors (CPU) coupled to the remote bus, and for selectively converting address information of remote central processor (CPU) appearing on address lines into addresses of central processors (CPU) coupled to the local bus , and c) a source central processor address (CPU) selective access memory (RAM, 113) for selectively converting central processor (CPU) address information appearing on data lines into remote central processor (CPU) addresses for storage in the remote transfer unit and for selectively converting remote central processor (CPU) address information provided on the data lines to cent processor addresses local ral (CPU) for storage in the local transfer unit. 7. Data transfer unit according to one of the preceding claims, characterized in that the logic control device comprises: a) state control means reacting to storage means in the unit and to acquisition means for placing the unit in one of the following logical states: 5 10 15 20 25 30 35 40 45 50 55 60 65 3 640,645 i) online, ii) erasure, iii) stop, the acquisition means comprising decoding means (94) reacting to information appearing at the interface of the local bus so as to generate stop and reset signals, the reset signal erasing the memory registers in the transfer unit, b) cycle generating means (146) reacting to the information detection means and to the state control means for selectively generating internal synchronization signals, asynchronous with respect to the rhythm of the cycles of the local bus, so as to control the passage of information through the transfer unit, c) a synchronization and state logic device (133) reacting to the state of storage means for detecting and bypassing dead ends for the passage of information and indicating such situations, and d) means for interrupting (132, 134) reacting to the synchronization and state logic apparatus, to the state of the storage means and to the acquisition means to identify the appearance of external interruptions. 8. Data transfer unit according to claims 6 and 7, characterized in that it comprises operating code decoding means (102, 106) reacting to the acquisition means, to the cycle generator means and to the logic control apparatus, for communicating to the state control means, the synchronization and state logic apparatus and the interrupting means an order chosen from among several internal orders, and reconfiguration means (108, 118 ) coupled to the address translation selective access memories (RAM), to the logic control device, to the acquisition means and to the operating code decoding means to reconfigure the information stored in the translation means d address when the first control signals appear. 9. Data transfer unit according to claims 5 and 8, characterized in that the channel address decoder comprises a selective access memory (RAM) for masking channels (142) and in that the reconfiguration means ( 108, 118) are coupled to the channel masking selective access memory (RAM) so as to reconfigure the information stored in it when the first control signals appear.