KR0153017B1 - Rink process system of the full electronic switching system having memory and line inter-facing unit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common processor of an all-electronic exchange having a memory and line matching function. In particular, the electronic and electronic device having a memory and line matching function can increase operation, maintenance, and cost efficiency by reducing hardware and improving functions of the system. It relates to a common processor of the exchange.

The BPIB-E provided in the present invention includes a central processing unit, a B-bus port, a PIO circuit, a USART circuit, a DMA circuit, a buffer, an SIO circuit, a bus selection and a hardware signal monitoring circuit, a CTC, It consists of clock generator, self test circuit, and line matching circuit. It combines the functions of two boards into one board by hardware change and simplification, chip change, etc. The exchange system can be simplified, has a wide range of replacements and high reliability when the existing memory is discontinued. In addition, the power supply board can be replaced with a low-cost board by simplifying the board, which has a favorable effect on the price.

Description

Link Processing System of Electronic Switching System with Memory and Line Matching

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common processor of an all-electronic exchange having a memory and line matching function. In particular, the electronic and electronic device having a memory and line matching function can increase operation and maintenance and cost efficiency by reducing hardware and improving functions of the system. It relates to a common processor of the exchange.

An electronic switchboard is a device that is responsible for the voice connection between a specific telephone subscriber and a plurality of general subscribers. The electronic switchboard is a system that handles switching to processor control and data services inside the device by an electronic switching method when a subscriber selects another subscriber. Say. In addition, the electronic switch is divided into a number of levels according to the operation of the electronic switch processor, in particular, the T-level is a higher level of the processor that controls the switch, and controls the lower processor, the equivalent level processor and related information It has the function of controlling low level circuit and collecting low level information about input information.B-level and D-level refer to the block and device level among the processors that control the exchange. Level) to control lower level blocks and devices, collect information, and report to higher levels. In addition, the link level, which is a level to which the link processor belongs, refers to a processor level in charge of a protocol for exchanging information with another exchange.

The processor board (CPB-B) part and the line matching board (MLIB-B: Memory and Line Interface Board-B) part having a line matching function are separated from each other. Hereinafter, a common processor board portion and a memory board portion of a conventional all-electronic exchanger will be described with reference to the accompanying drawings.

FIG. 1 is a detailed block diagram of CPB-B of the conventional all-electronic exchanger, and FIG. 2 is a detailed block diagram of MLIB-B of the conventional all-electronic exchanger.

Referring to FIG. 1, the CPB-B of the electronic switchboard includes an 8-bit main processor 11 for controlling the operation of the entire system, a buffer 12 for transmitting external data to the main processor 11, and A B-bus port 13 for input / output of a signal of a B-bus, a serial input / output (SIO) circuit 14 for inputting and outputting data in series with the B-bus port 13, Direct memory access (DMA) circuit 15 connected to the SIO circuit 14 and the main processor 11 to allow the memory to directly input and output without passing through the CPU, and a hardware monitor to monitor the hardware. A parallel input / output circuit (PIO) 17 connected to the hardware monitor 16 to input and output data in parallel, and an alarm driver connected to the PIO circuit 17 to generate an alarm; 18, the PIO circuit 17 is connected to the priority Universal Synchronous Asynchronous Receive (USART) with non-maskable interrupt (NMI) generator 19 to generate an interrupt, and serial synchronous signaling method, and connected to a man machine port to transmit and receive serial data between circuits in a certain format. and a counter timer (CTC: Counter Timer Circuit) 21 which exchanges data with the circuit 20 and the USART circuit 20 and operates as a counter or a timer according to the output signal of the USART 20. A clock generator 22 generating a clock to match the registers of the main processor 11, the PIO circuit 17, and the DMA circuit 15, and a buffer for stabilizing signals of the main processor 11 ( 23) and a decoder 24 for coding the input and output ports which are peripheral circuits.

CPB-B of the all-electronic exchange configured as described above has a function of controlling system by the complex operation of each component and has a role of controlling the T-level and B, D-level processors of the all-electronic exchange. . The main processor 11 of the CPB-B provides a memory refresh signal to access a dynamic RAM (DRAM) of a memory board through a 16-bit address line, and provides peripheral circuits of input / output devices and off boards. I / O port can be controlled.

Referring to FIG. 2, the MLIB-B of the all-electronic exchange includes a buffer 31 for receiving and stabilizing data, a buffer 32 for receiving and stabilizing an address, and a decoder 33 for decoding and outputting a control signal. ), A memory 34 having various kinds of information, a memory control circuit 35 that receives data from the buffer 32 and the decoder 33 and controls the memory 34, and the buffer 31. A buffer 36 for receiving the output of the data and transmitting the data to the memory 34, a self-test circuit 37 for testing a function with the electronic switch itself, the self-test circuit 37, and the buffer 31 Buffer 38 for receiving and stabilizing the output of the circuit, and a line matching circuit 39 for matching the lines by receiving the output of the self test circuit 37 and the buffer 32.

The MLIB-B of the all-electronic exchange configured as described above provides a memory of the B-level processor among the processor groups of the all-electronic exchange, and the line matching circuit 39 is controlled by the CPB-B to serve the subscriber line matching. . In addition, the self test circuit 37 tests the exchange itself to confirm whether the subscriber matching function is normal.

The conventional CPB-B, which is constructed and operated as described above, is designed to be used in all processors of an electronic switch, and includes a large number of unnecessary functions in the B-level processor. In the memory part, the control logic is complicated and reliable. There is a disadvantage in that it is low, and since 1-bit DRAM is becoming obsolete, countermeasures are required.

Therefore, in order to compensate for the above disadvantages, in the present invention, the processor board, the memory, and the line matching part of the conventional board are integrated into one board by changing and simplifying circuits, removing unnecessary functions, and changing chips. The hardware monitor circuit part of the processor part is ASIC by digitalization, and the memory is used as SRAM (Static RAM) to improve the circuit simplification and reliability.

1 is a detailed block diagram of the CPB-B of the conventional all-electronic exchanger,

2 is a detailed block diagram of the MLIB-B of the conventional all-electron exchanger,

3 is a detailed block diagram of a BPIB-E according to an embodiment of the present invention,

4 is a detailed block diagram of a bus selection and hardware signal monitoring circuit according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

41: central processing unit 42: B-bus port

43: SIO circuit 44: USART circuit

45: DMA circuit 46: memory

47: buffer 48: PIO circuit

49: N10 ASIC (Bus Select and Hardware Signal Monitoring Circuit) Circuit

50: CTC 51: Clock Generator

52: buffer 53: self test circuit

54: line matching circuit 61: data selection circuit

62: H / W monitor circuit 63: WDT monitor circuit

64: S / W reset generation circuit 65: clock generation circuit

66: Tx data composition circuit

In order to achieve the above object, the present invention provides a link processing system of an all-electronic exchange having a memory and line matching function.

The link processing system (BPIB-E) of an electronic switching system having a memory and line matching function provided by the present invention includes a central processing unit for controlling the operation of the entire system, and a B-bus port for input / output of B-bus data. And a USART having a serial input / output circuit for inputting / outputting data in series with the B-bus port, and a serial synchronization signal method, connected to a man machine port, for transmitting / receiving serial data between circuits in a predetermined format. A circuit, a direct memory access circuit connected to the serial input / output circuit and the central processing unit and allowing a memory to directly input and output without passing through the central processing unit, a memory having information necessary for various operations of the electronic switchgear, and A buffer for processing data transferred between the central processing unit and the memory, and an output scene of the memory A parallel input / output circuit for inputting and outputting the signal in parallel, a bus selection and hardware signal monitoring circuit for receiving and processing the output of the parallel input / output circuit as an input, and outputting the data, according to an output signal of the USART circuit. A counter timer circuit that operates as a counter or a timer, a clock generator that generates a clock to synchronize the central processing unit, the parallel input / output circuit, the direct memory access circuit, and the counter timer circuit, and an output of the USART circuit. A buffer for stabilizing and outputting a buffer, a self-test circuit that receives the output of the buffer, and tests the performance of the exchanger, and a line-matching function that receives the output of the self-test circuit and the output of the central processing unit input through the buffer. It consists of a line matching circuit.

Hereinafter, the BPIB-E provided by the present invention will be described with reference to the accompanying drawings.

3 is a detailed block diagram of a BPIB-E according to an embodiment of the present invention, and FIG. 4 is a detailed block diagram of a bus selection and hardware signal monitoring circuit according to an embodiment of the present invention.

Referring to FIG. 3, the DPIB-E includes a central processing unit (CPU) 41 for controlling the operation of the entire system, a B-bus port 42 for inputting and outputting B-bus data, and the like. A serial input / output (SIO) circuit 43 for inputting and outputting data in series with the B-bus port 42, and using a serial synchronization signal method and connected to a man machine port to schedule serial data between circuits; USART circuit 44 having a function for transmitting / receiving by type, and a direct memory access circuit (DMA) connected to the SIO circuit 43 and the CPU 41 to allow the memory to directly input and output without passing through the CPU. Direct Memory Access (45), a memory (SRAM) 46 having information necessary for various operations of the electronic switchboard, and data transferred between the CPU 41 and the memory 46. Input and output the buffer 47 and the output signal of the memory 46 in parallel Parallel input / output (PIO) circuit 48 and a bus selection and hardware signal monitoring circuit 49 for receiving the output of the PIO circuit 48 as an input and monitoring various states of hardware and outputting results. And a counter timer circuit (CTC) 50 which exchanges data with the USART circuit 44 and operates as a counter or a timer according to the output signal of the USART circuit 44, and generates a clock. A buffer for stabilizing and outputting the output of the clock generator 51 and the USART circuit 44 to synchronize the CPU 41, the PIO circuit 48, the DMA circuit 45, and the CTC 50. A self test circuit 53 for receiving the output of the buffer 52 and testing the performance of the exchanger, and a central processing unit input through the output of the self test circuit 53 and the buffer 47. To a line matching circuit 54 that receives line output and functions as a line matching function. It is composed.

In particular, the bus selection and hardware signal monitoring circuit 49 includes a data selection circuit 61 for selecting data input from the outside, a hardware (H / W: hardware) monitor circuit 62 for monitoring hardware, and an exchanger. Watch dog timer (WDT) monitor circuit 63 for monitoring the operation state of the software and a software reset generation circuit for generating a software (S / W: Software) reset by receiving the output of the PIO circuit 48 64, a clock generation circuit for generating a clock and the hardware signal monitoring circuit 49, a clock generation circuit 65 for synchronizing therein, and a serial connected to the clock generation circuit 65 and transmitted to the bus; Tx data driving circuit 66 for driving data (Tx data).

The signal monitoring circuit 49 receives the data signal A / B, the assert signal A / B, the block, and the FRame Synchronism (FRS) signal from the data selection circuit 61. And Px assertion and block signals are output to select a bus that operates normally among the redundant buses, and the H / W monitor circuit 62 selects signals such as assert signals (A / B), blocks, FRS, and the like. When a fault occurs, a fault signal is generated and notified to a processor. The WDT monitor circuit 63 receives a WDT signal and monitors an RTC signal generated at a cycle of 50 ms.

In addition, the S / W reset generation circuit 64 generates a reset signal when receiving the output of the PIO to reset the H / W to S / W. The clock generation circuit 65 selects the bus and The clock used for each block inside the hardware monitoring circuit 49 is generated. Finally, the Tx data driving circuit 66 receives the signals of the Tx assert and the Tx data and creates a condition for transmitting data to the bus. .

The BPIB-E of the present invention configured as described above controls the B-level processor of the electronic switchboard and controls the memory function capable of storing operational data and data related to bus communication and the subscriber board to match subscriber lines. Line matching function. In addition, the 32K byte memory composed of SRAM enables the storage of information data necessary for exchanging various system information and matching subscriber lines.

In addition, the hardware monitor circuit 62 monitors the B-bus signal and RTC (Real Time Clock) to generate alarms and NMIs in the event of a failure and to protect the system by blocking the bus matching circuit. The self test circuit 53 has a function of allowing the CPU to monitor whether the control signal for controlling the line matching circuit 54 is normally operated and the normal operation state of the line matching circuit 54.

As described above, the BPIB-E of the present invention integrates a function consisting of two boards into a single board by hardware change and simplification, chip change, and the like. When the existing memory is discontinued, there is a wide range of replacement and high reliability. In addition, the power supply board can be replaced with a low-cost board due to the simplification of the board.

Claims (2)

A processor and line matching board of an electronic switching system operating under the control of a central processing unit, comprising: a B-bus port circuit responsible for input / output of B-bus data, and a serial input / output for inputting and outputting data in series with the B-bus port. USART that uses a circuit and serial synchronization signal method, and is connected to a man machine port to use a certain method for inter-circuit serial data, and is connected to a man machine port to transmit / receive serial data between circuits by a certain format. (Universal Synchronous Asynchronous Receive and Transmit) circuit, a direct memory access circuit connected to the serial input / output circuit and the central processing unit and allowing the memory to directly input and output without passing through the central processing unit, and information necessary for various operations of the electronic switchboard. And a memory circuit having a transmission between the central processing unit and the memory. Is a buffer circuit for processing data, a parallel input / output circuit for inputting and outputting the output signal of the memory in parallel, a bus selection and hardware signal monitoring circuit for receiving and processing the output of the parallel input / output circuit as an input, and the USART A counter timer circuit that exchanges data with a circuit and operates as a counter or a timer according to an output signal of the USART circuit, and generates a clock to generate the central processing unit, the parallel input / output circuit, the direct memory access circuit, and the counter timer circuit. A clock generator circuit for synchronizing the signals, a buffer circuit for stabilizing data transmitted between the CPU and the memory, and for stabilizing and outputting a signal received from the USART circuit; A self test circuit for testing performance, and the self test And a line matching circuit configured to receive the output of the circuit and the output of the central processing unit input through the buffer to perform a line matching function. 2. The bus selection and hardware signal monitoring circuit of claim 1, wherein the bus selection and hardware signal monitoring circuit includes a data selection circuit for selecting data input from the outside, a hardware monitor circuit for monitoring hardware, and a watchdog operation for monitoring an operating state of an exchange. A watchdog monitor circuit, a software reset generation circuit that receives the output of the parallel input / output circuit, and generates a software reset, a clock generation circuit that generates a clock to synchronize the inside of the monitor circuit, and the clock generation circuit And a Tx data driving circuit configured to drive serial data (Tx data) connected to the bus to drive the serial data (Tx data).