KR930006032B1 - The implementation of level 3 in ccs no.7 mtp on tdx-1 - Google Patents

Abstract

The message input/output board realizes level 3 signal network function and interfaces level 2 signal network function and user parts. The message input/output board includes buffers (4,5,6) for buffering signals transmitted through VME bus (1), a reset signal generator (3) for generating reset signal to reset devices in the board, a bus error detector (14) for monitoring operating state of an MPU to detect bus errors, a decoder (16) for generating device selection signal so that an MPU controlls devices, a serial communication controller (DSUCC,18) for transmitting and for receiving message exclusively, a signal loop controller (19) for looping signal to be transmitted to the external back to indentify the error position when error occurs and a state control register (22) for controlling operating state of the board.

Description

Message input / output board for level 3 function of common line signaling system

1 is an overall configuration diagram of a message delivery unit to which the present invention is applied.

2 is a schematic block diagram of a message input / output dedicated board according to the present invention.

3 is a detailed view of a DP-RAM access control unit according to the present invention.

4a and b are detailed views of an interrupt controller according to the present invention;

5 is a detailed view of a B-bus connection control unit according to the present invention.

6 is a detailed view of a signal loop control unit according to the present invention.

7 is a detailed view of a bus error recognition part according to the present invention.

* Explanation of symbols for main parts of the drawings

1: VME bus 2: Internal bus

3: reset circuit 4: address buffer

5: data signal buffer 6: dual port RAM

7: control signal buffer 8: dual port RAM access control unit

9: Interrupt control unit 10: Interrupt recognition unit

11: microprocessor 12: programmable ROM

13: static RAM 14: bus error recognition and generation unit

15: Clock generator and division unit 16: Address decoder

17: DMAC 18: DUSCC

19: signal loop control unit 20: MFP

21: status recognition register 22: status control register

23: B-bus connection control unit 31: switch

32: 8-bit comparator 33: ROM

34: PAL 35,41: PAL

42,46: flip-flop circuit 43: 8-bit register

44: selection switch 51a, 51b: redundant bus interface stage

52: selector 53: DUSCC

54: clock monitoring circuit 55: synchronization signal monitoring circuit

56: counter 57a, 57b: AND gate

58: flip-flop 59: bus occupancy time monitoring circuit

71: OR gate 72: AND gate

73: multivibrator

The present invention implements a signal network function (level 3) of the message transfer part (MTP) function of the common line signaling method (CSS No. 7), and a connection function and a user part (UP: User) with a level 2 function. It is about message input / output board for communication with Part.

Integrate various services to realize comprehensive information and communication networks that will play the most important role in the future information society. It is in the stage of development.

An object of the present invention is to implement a manganese protocol by the common line signaling method by adding a message transfer function to the domestic TDX-1 ("registered trademark") series already installed and operated at the main point as described above. In this regard, the present invention provides a message input / output dedicated board to secure the technology and to provide the conditions for providing the various services using the same, as well as the independence of the communication technology for the common line signaling method.

In order to achieve the above object, the present invention provides a message input / output dedicated board of a message transfer unit of an electronic switch, comprising: a buffer means connected to a VME bus for stably providing various signals, and a dual port RAM connected to the buffer means. MPU connected to the DP RAM via an internal bus, buffer means, DP RAM, and DP RAM access control means connected to an internal bus, each device on board connected to the VME bus and powered on and requesting a reset. Reset means for maintaining synchronous operation, an interrupt control means connected to the VME bus and an internal bus, encoding the required interrupt connected to the MPU to the MPU, recognizing the interrupt at the MPU, and then responding with a response signal. Interrupt acknowledgment means for sending to interrupt generating element, connected to the MPU and monitoring the operation state of the MPU to cause a bus error due to an operation error Bus error recognition and generation means for recognizing and informing the MPU to restore the system to normal, PROM and SRAM connected to the internal bus, clock generation and division means for providing a clock signal to each element in the board, and connected to the internal bus. Decoding means for generating a selection signal so that the MPU can control each element on the board, DMA control means connected to the internal bus, the internal bus and DMA control means connected to the independent function of sending and receiving Signal loop control means connected between the serial communication control means (DSUCC), the serial communication control means and the STG bus to block the signal transmitted from the outside in the board when the error occurs, and to loop back the internal to check the error position MFP connected to the internal bus, connected to the internal bus and the MFP to check the operating state of the board A status control register is connected to the internal bus and the MFP to control the operating state of the board in an appropriate state. The serial communication control means, the MFP, the status recognition register and the status control register are connected to the B-bus. Characterized in that consisting of the B-bus connection control means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, the role of the present invention in the overall configuration of the message delivery unit will be described with reference to FIG. 1, and the function of the message input / output dedicated board will be described in FIG.

The message input / output dedicated board interprets the message transmitted through the VME bus from the level 3 function processing unit and transmits it to the user unit (B-bus) or delivers it to each signal terminal performing the level 2 function (STG bus). . The B-bus is a communication channel between processors in the TDX-1 series electronic switch, which is commercially available, and the B-bus connection function of the message input / output board can be connected without changing the existing B-bus. The message from the signal terminal coming through the STG bus and the pure message from the user part are delivered to the level 3 function processing unit via DP-RAM (Dual Port-RAM).

Looking at the functional block configuration of the signal terminal board through Figure 2 as follows.

In the figure, 1 is a VME bus, 2 is an internal bus, 3 is a reset circuit, 4 is an address buffer, 5 is a data signal buffer, 6 is a dual-port RAM (DP-RAM), 7 is a control signal buffer, 8 is a dual Port RAM (DP-RAM) access control unit, 9 is interrupt control unit, 10 is interrupt recognition unit, 11 is microprocessor (MPU), 12 is programmable ROM (PROM), 13 is static RAM (SRAM), 14 is bus error Recognition and generation unit, 15 is a clock generation and division unit, 16 is an address decoder, 17 is a DMAC, 18 is a DUSCC, 19 is a signal loop control unit, 20 is an MFP, 21 is a state recognition register, 22 is a state control register, 23 denotes a B-bus connection control unit, respectively.

The level 3 function control unit reads (receives) the dual port RAM (DP-RAM) 6 of the message input / output board when the signal terminal or the user part needs to exchange messages, or reads the information in the dual port RAM (DP). RAM, and the message I / O board buffers the address, data, and control signals to access the dual-port RAM (DP-RAM) 6 by the VME bus for this purpose. It is used after (4,5,7). The dual-port RAM access control section 8 uses the address signal of the VME bus to determine the area where the dual-port RAM 6 can be accessed in the level 3 function control section. By using the control signal of the bus, the dual-port RAM (DP-RAM) is converted into a control signal that can be accessed, and a dual-port RAM with the same level 3 function control unit and MPU (Micro Processor Unit) of the message input / output board A control signal is also generated to prevent data loss when accessing the (DP-RAM) area.

When a message input / output dedicated board receives or transmits a message through the DP-RAM 6, a method of continuously checking the presence or absence of a message at a predetermined time period will generally degrade performance. As a solution to this problem, an interrupt method is introduced for transmission and reception, and when there is a message to be transmitted to the level 3 function control unit, the DP-RAM 6 is filled with a message and an interrupt is generated to inform that there is a message. Read the message in RAM (6). The interrupt control section 9 is a circuit section for this purpose.

The interrupt recognition unit 10 receives the interrupts from the level 3 function control unit and encodes various interrupts in the message input / output dedicated board, encodes them to the MPU 11, and recognizes the interrupts in the MPU 11. Create and send an interrupt to the device that generated it.

The selection signal of each device in the message input / output dedicated board is generated by the address signal and the control signal of the MPU 11 in the address decoder 16, and the reset circuit 3 resets when the power is supplied. The reset signal sent by the set switch is simultaneously sent to each device on the board to maintain operational synchronization. The clock generation and division unit 15 is composed of a clock generation and division circuit.

The bus error recognition and generation unit 14 recognizes a bus error for the memory access outside the memory area of each device in the board due to an operation error of the control software, and notifies the MPU 11 of a serious case in case. Function block to recover the system normally in case of an operation error.

The state recognition register 21 and the state control register 22 are 16-bit registers for analyzing the operation state of the message input / output dedicated board and controlling the state to an appropriate state when necessary.

The signal loop controller 19 is located at a connection point between a signal for serial I / O (serial input / output) and an external signal (B-bus and STG-bus) in the message input / output dedicated board. It has the function to block the signal majored from the board to the outside by the control of the outside and loopback the inside, so that the self test without affecting the other boards connected with the message input / output dedicated board in FIG. It provides the ability to do so.

The B-bus connection control unit 23 is a function block that provides a function for transmitting and receiving a message by connecting to a B-bus, a communication channel between processors, in a TDX-1 series electronic switchboard. Have

In order to be able to transmit messages by occupying the B-bus with equal opportunity, the received transmission clock can be counted and the counter initialized to an arbitrary value. In addition, when the bus is occupied by the counterpart processor connected to the B-bus, the controller recognizes the occupancy state and performs valid data reception only in the occupied state. In addition, it should provide the occupancy of the bus to other processors connected to the B-bus equally, and have a hardware timer that prohibits the occupancy of the bus for more than a certain period of time in order to prevent inoperation of the communication channel due to an operation error. Watch.

In addition, since message input / output dedicated board is designed to operate dependently on B-bus, it operates according to received operation clock and synchronous clock, and monitors the reception status of clock and stops reception of clock while monitoring clock reception status. If it is disabled, the bus to be used is switched in the redundant structure of the B-bus.

As a preferred embodiment, the message input / output dedicated board is composed of the following main ICs in addition to the above-described functional blocks. The MPU 11 uses the MC68000 in the embodiment of the present invention to access and control elements in the board through the internal bus 2. The PROM 12 is a programmable ROM connected to the internal bus 2, and in the embodiment of the present invention, two EPROMs (150 ns) of 32K bytes are used.

The SRAM 13 is a static RAM connected to the internal bus 2. In the embodiment of the present invention, two SRAMs (120 ns) of 32K bytes are used.

The DMAC 17 is connected to the internal bus 2 and has an independent four processing channels for sending and receiving messages. As the embodiment of the present invention, the MC68450 is used.

The DSUCC 18 is connected to the internal bus 2 and the DMAC 17 and is a multifunctional serial communication controller having two channels for independent transmission and reception for the transmission and reception of messages. Was used.

The MFP 20 is connected to the internal bus 2 and incorporates an asynchronous serial communication controller, three timers, an input / output port, an interrupt prioritization module of various causes, and the like. In the example, MC68901 was used.

So far, the main functions of the functional block of the message input / output dedicated board according to the present invention of FIG. 2 have been described. Next, the linkage of each functional block and the overall operation procedure will be described.

In the level 3 function control unit, when there is a message to be transmitted to the signal terminal or the user unit, the message is filled in the DP-RAM 6 and an interrupt is sent to the message input / output dedicated board. The message input / output dedicated board recognizes the interrupt, reads the message from the DP-RAM (6), moves it to a specific area of the SRAM (13), and then uses the status control register to normalize the interrupt from the VME-bus (1). After recovering to the state, the received message is interpreted, and the specific channels of the DMAC 17 and the DUSCC 18 corresponding to the B-bus or STG-bus are controlled and transmitted. When transmitting on the B-bus, the state of the B-bus connection control unit 23 is properly controlled through the state recognition register 21, and then the bus occupancy state is determined by an interrupt caused by a change in the input port of the MFP 20. Recognizes and drives the DMAC 17. When receiving, the receiving channel of DMAC 17 and DUSCC 18 is in an operating state. When receiving a message, an interrupt is recognized from the receiving channels of DMAC 17 and DUSCC 18 corresponding to the B-bus or STG-bus. . When the MPU 11 recognizes the reception completion status by the interrupt, it reads a message from a specific area of the SRAM 13, fills it with the DP-RAM 6, and interrupts the level 3 function control unit through the interrupt control unit. Signals that a message has been received from the bus or STG bus.

Hereinafter, each functional block of the message input / output dedicated board of the present invention will be described in detail with reference to the accompanying drawings. 3 is a detailed view of the DA-RAM access control section 8.

In the figure, 31 is a switch, 32 is an 8-bit comparator, 33 is a ROM, and 34 is a PAL (Programmable Array Logic). If the address (A23 ~ Al6) of the VME bus and the setting value of the switch in the message input / output dedicated board match, additional decoding is performed and based on the AM (Address Modifier) code of the VME bus and the control signal. A selection signal of the DP-RAM is generated and a bus error signal is generated when the level 3 function controller accesses another address area.

4A and 4B are detailed views of an interrupt controller, in which 41 and 45 are PALs, 42 and 46 are flip-flop circuits, 43 are 8-bit registers, and 44 are select switches.

Since the selection process and the necessary control signal are generated by using a programmable array logic (PAL) in the realization process, the operation state is described by using the resultant output signal of each PAL. 4A shows a method of interrupting the message input / output dedicated board from the level 3 functional control unit. When writing data to a specific area of the DP-RAM in the level 3 function controller using the address signal from the VME bus and the control signal (a) required for DP-RAM access, the message input / output dedicated board is interrupted. And a register application signal generated and latched by the signal (b) of the status control register. 4b shows a method of applying an interrupt to the level 3 function control unit from the message input / output dedicated board. When latching the interrupt vector value from the MPU to the level 3 function controller in the 8-bit register 43, the interrupt signal to the VME bus is driven by the select signal c of the address decoder to D-flip / flop 46. Is latched in. An interrupt switch on the VME bus can be selected by placing a selector switch 44 on the board. When the address signal VA1 to VA2 of the VME bus coincides with the setting value of the internal switch 44 in the interrupt response cycle of the level 3 function controller, the vector of the 8-bit register 43 is used by using the control signal of the VME bus. The PAL 45 generates a signal for exporting the value to the data bus of the VME bus and a signal for restoring the interrupt signal to the VME bus to a normal state.

FIG. 5 is a detailed view of the B-bus connection controller, in which 51a and 51b are redundant bus interface stages, 52 is a selector, 53 is DUSCC, 54 is a clock monitoring circuit, 55 is a synchronization signal monitoring circuit, 56 is a counter, 57a and 57b denote AND gates, 58 denote flip-flops, and 59 denote bus occupancy time monitoring circuits.

In the TDX-1 series exchange, the B-bus is redundant, so the message input / output dedicated board also duplicates the bus transmission / reception interface stages 51a and 51b, and the control signal (d) of the status control register A side of the bus or It is comprised so that selection on the B side is possible. The B-bus consists of four signals: data, ASST (a signal to inform the other processor of the occupancy status in each processor on the bus), a clock signal that determines the transmission speed, and a synchronization signal. The value of the counter 58 is initialized using the synchronization signal, and the bus occupancy signal AST is latched on the D-flip / flop 58 at the end of the counter according to the control signal e of the status control register. Is sent to. When the message is completed, the occupancy signal must be recovered by using the control signal (f) of the status control register. The bus occupancy time monitoring circuit 59 maintains the bus occupancy state within the board for a predetermined period of time. g) informs the MFP and status register. The clock monitoring circuit 54 and the synchronization signal monitoring circuit 55 send a status signal h to the MFP when the clock signal and the synchronization signal of the B-bus are not recognized, and apply an input / output dedicated board to the MPU. The clock monitoring circuit, the synchronization signal monitoring circuit, and the bus occupancy time monitoring circuit are implemented as a multivibrator as shown in the configuration diagram of the bus error recognition unit of FIG.

FIG. 6 shows the configuration of the signal loop control unit. In the embodiment of the present invention, LS157 is used. It is useful to find out the location of error when self-test of STG bus connection function of message input / output dedicated board or when there is a problem in connection with signal terminal. The operation clock on the STG bus uses an internal clock signal k of the clock generator and the divider, and performs a signal loop function if necessary by using the control signal j of the status control register.

7 is a detailed configuration diagram of the bus error recognition and generation unit, where 71 is an OR gate, 72 is an AND gate, and 73 is a multivibrator.

In the figure, 1 is a reset signal in the board, m is a signal corresponding to two divisions of the MPU operating frequency, and n is an address strobe signal of the MPU.

Therefore, when the address strobe AS signal is not generated for a predetermined time, the bus error signal is generated by the multivibrator 63 connected to the output terminal of the AND gate 72. The MPU 11 then recognizes the bus error signal, processes it as a serious error in the control routine, and initializes the control routine in the board.

Thus, the message input / output dedicated board of the present invention as described above has a B-bus connection function of the TDX-1 series, an STG bus connection function for linking with a signaling terminal (ST), and a VME- Performs bus and DP-RAM (Dual Port RAM) connection functions and monitors the operation status of message I / O boards.

The present invention configured and operated as described above has the following effects. It provides hardware connection technology that can transfer the function of the common line signaling system to the TDX-1 series of domestic electronic switchboards. In addition, the board of the present invention greatly reduces the burden on the processor related to message input and output of the level 3 functional control unit having a signal network function, thereby increasing the overall processing performance of the message transfer unit. This method, which implements the message input / output function separately, is applied to a device having a communication function with the outside by a specific communication protocol.

Claims (6)

In the message input / output dedicated board of the message delivery part of an electronic switchboard; Buffer means (4, 5, 7) connected to the VME bus (1) for stably providing various signals, dual port RAM (DP RAM) (6) connected to the buffer means (4, 5), internal bus An MPU 11 connected to the DP RAM 6 via the (2), the buffer means 4, 7, the DP RAM 6, and DP RAM access control means 8 connected to the internal bus 2, Reset means 3 connected to the VME bus 1 and maintaining the operational co-operation of each element in the board upon power supply and reset request, to the VME bus 1 and the internal bus 2; Interrupt recognition means (10) connected to the MPU (11), the interrupt is encoded by encoding the required interrupt to the MPU (11) and sends an acknowledgment signal to the corresponding interrupt generating element when the interrupt is recognized by the MPU (10) Is connected to the MPU 11 and monitors the operation state of the MPU to recognize a bus error due to an operation error and informs the MPU 11 of the system to normal. A bus error recognizing and generating means (14) for recovering, a PROM (12) and an SRAM (13) connected to the internal bus (2), clock generating and distributing means (15) for providing a clock signal to each element in the board, Decoding means 16 connected to an internal bus to generate a selection signal for the MPU 11 to control each element in the board, DMA control means 17 connected to the internal bus 2, the internal A serial communication control means (DSUCC) 18 connected to the bus 2 and the DMA control means 17 and having independent function of sending and receiving messages, the serial communication control means 18 and the STG-bus. And a signal loop control means 19 for checking an error position by intercepting a signal transmitted to the outside from the board and looping back to the inside when an error occurs, the MFP 20 connected to the internal bus, the internal bus 2 and Connected to the MFP (20) to check the operating status of the board. Is connected to the state recognition register 21, the internal bus and the MFP 22, the state control register 22 for controlling the operation state in the board to an appropriate state, the serial communication control means 18, the MFP 20, Level 3 function implementation of the common line signaling message transfer unit, characterized in that it comprises a B-bus connection control means 23 connected to the state recognition register 21 and the state control register 22 and connected to the B-bus. I / O dedicated board for messages. The VME-bus of claim 1, wherein the DP RAM accessing means (8) is connected to the switch (31) for setting a predetermined value for generating a selection signal of the DP RAM, the VME bus and the VME- inputted to the switch (31). An 8-bit comparator 32 for comparing the address A23 to Al6 of the bus with the switch setting value, a ROM 33 connected to the 8-bit comparator 32 and the VME bus, and the ROM 33 And a PAL (34) for receiving a control signal of the VME bus and an MPU control signal to generate a DP RAM selection signal. 2. The interrupt control means (9) according to claim 1, wherein said interrupt control means (9) inputs an address signal (A1 to A11) from the VME bus and a DP RAM access control signal (a) to generate an interrupt; An interrupt is generated from the level 3 function controller to the message input / output dedicated board by the flip-flop 42 connected to the PAL 41 and the status control register and restoring the interrupt application signal latched in accordance with the control signal b. A switch 44 for selecting an interrupt number of the VME bus, a PAL 45 connected to the switch 44 and the VME bus, and a data signal on the board under the control of the PAL 45 and the address decoder; And a level 43 function control unit in the message input / output dedicated board is generated by a register 43 for outputting to the VME bus and a flip flop 46 connected to the PAL 45 and the address decoder. Common line signaling messages Message input and output board to implement negative level 3 functions. 2. The bus control means (23) according to claim 1, wherein said B bus control means (23) is connected to bus interface means (51a, 51b), said bus interface means (51a, 51b), which are redundantly connected to a B bus. The selector 52 controlled by the selector 52, the bus interface means 51a and 51b and the DUSCC 53 connected to the selector 52, the clock signal and the synchronization signal from the B-bus are monitored to interrupt the MPU in an abnormal state. A signal monitoring means (54, 55) for generating, a counter (56) for inputting a counter initial value and a synchronization signal and generating an end signal, a first AND gate (57a) connected to the counter and controlled by a status control register, A flip-flop 58 connected to a first AND gate and controlled by a state control register, bus occupancy monitoring means 59 connected to the flip-flop to monitor the occupancy state of the bus, and the flip-flop 58 and bus occupancy Input stage to the monitoring means (59) Connected and the output terminal is a message dedicated to input and output boards for implementing a common channel signaling system message transfer part level 3 functions, characterized by consisting of a first 2AND gate (57b) coupled to the bus interface unit. 2. The message input / output dedicated board for implementing a level 3 function of the common line signaling message transfer unit according to claim 1, wherein said signal loop control means (19) comprises LS157. The OR gate 71 according to claim 1, wherein the bus error recognition and generation means (14) logically combines the reset signal (1) in the board and the signal (m) corresponding to two divisions of the operating frequency of the MPU (11). ), An AND gate 72 for ANDing the output of the OR gate 61 and the address strobe signal n of the MPU 11, and a multivibrator 73 connected to an output terminal of the AND gate 72. Message input / output dedicated board for level 3 function implementation of common line signaling system.

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