GB2217551A - Electronic system for packet switching - Google Patents

Electronic system for packet switching Download PDF

Info

Publication number
GB2217551A
GB2217551A GB8809299A GB8809299A GB2217551A GB 2217551 A GB2217551 A GB 2217551A GB 8809299 A GB8809299 A GB 8809299A GB 8809299 A GB8809299 A GB 8809299A GB 2217551 A GB2217551 A GB 2217551A
Authority
GB
United Kingdom
Prior art keywords
control
local bus
packet
bus
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8809299A
Other versions
GB8809299D0 (en
GB2217551B (en
Inventor
Antonio Golderos Sanchez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonica SA
Original Assignee
Telefonica de Espana SA
Telefonica Nacional de Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonica de Espana SA, Telefonica Nacional de Espana SA filed Critical Telefonica de Espana SA
Priority to GB8809299A priority Critical patent/GB2217551B/en
Publication of GB8809299D0 publication Critical patent/GB8809299D0/en
Publication of GB2217551A publication Critical patent/GB2217551A/en
Application granted granted Critical
Publication of GB2217551B publication Critical patent/GB2217551B/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

An electronic system for packet switching for handling data from a plurality of subscribers comprises two pairs of common communication buses 7a-7D establishing four main lines of communication and two control units 1, 2 connected to the four common buses. An information and control console 6 is connected to the control units for accepting and providing information and display for an operator. A plurality, e.g. up to 34 packet switches 3, 4 etc. are also connected to the four shared communication buses for controlling data and signals from subscribers, the receipt and transmission of data by means of line interfaces 27, 28; 46, 47 ,48, control data transfer between one packet switch and another, the treatment of control information and supervision exchange with one or each of the control units, maintainance of the separate packet switches and measurements and statistics for each individual packet switch. <IMAGE>

Description

Electronic System for Packet Switching The present invention relates in general to communication between computers, and in particular to a new and useful telecomputer system having two control units and up to thirty four packet switches all interconnected by four communication buses.
Telecomputing systems are known which utilise a plurality of computer terminals which can be interconnected by a telephone or other communication lines for transferring and processing information according to various programs stored at various locations and in various devices of the system.
The present invention refers to a packet switching system which has been designed to be used as a swiching centre and as a concentrator in data communication networks that use the packet switching technique. The network centres made up by this system carry out the packet switching in accordance with the virtual circuits technique. By means of this technique, the packet switching network controls the communication between two subscribers without establishing a physical connection between them.
Thanks to the storage and retransmission facilities available in the network centres, the subscribers remain virtually connected to each other while the communication lasts.Globally, the functions that the system carries out are the following: Control functions; Signalling functions; Packet switching functions; and Man-machine communications functions.
The purpose of the control functions is to manage the service and to supervise the operation of the entire system. The purpose of the signalli ng functions is to exchange information with the subscriber's terminal and with other network centres in order to establish, maintain and release communications. The purpose of the packet switching functions is to store, treat and retransmit packets between virtual input circuits and virtual output circuits. The purpose of the man-machine communication functions is the interaction and dialogue between the operator and the system for the assignment of operation and maintainance.
The structure of the system is based on the function distribution and load distribution philosophy. In accordance with the function distribution philosophy the centre is structured on the basis of units specialised in carrying out the different aforementioned functions.
Attending to the load distribution concept, the system divides up the messages, handling loads among the various parts of its functional units and equips the redundant units, where the reliabili e of the system requires it, in such a way that under normal working the message handling load is shared and under special conditions, one of them can handle the entire load of the system.
Therefore, an object of the present invention is to provide a packet switching system which is composed of a plurality of processing units connected between them by means of bus lines.
Accordingly, the present invention provides an electronic system for packet switching, comprising; four main communication buses; two control units connected to said common communication buses, each independantly capable of keeping the system in operation and carrying out measurements and statistics of the system, and controlling a plurality of peripherals of the system; a console connected to said two control units for receiving and displaying information from them; and a plurality of packet switches each connected to sail common communication buses and each for controlling data from subscribers of the system, for controlling the receipt and transmission of data using line interfaces, for controlling data transfer to other packet switches and to at least one of said control units and for controlling internal maintenance, measurements and statistics for itself.
The system thus provided can receive and process information from multiple locations and is adaptable to overcome a variety of failure situations while remaining functional.
The various features of novelty which characterise the invention are set out in the appended claims. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and description in which a preferred embodiment of the inventio is illustrated and described.
In the drawings: Fig.l is a schematic block diagram showing the general layout of the packet switching system according to the invention; and Fig. 2 is a more detailed block diagram of the packet switching switching system according to the invention.
The basic organisation of the system of the invention is as shown in Fig. 1. In this layout, the control functions are assigned to the control units 1 and 2, the signalling an packet switching functions are assigned to the packet switches 3,4,5, and the man-machine communications functions are assigned to the auxiliary units that make up the system console. The internal information transfer buses7, carry L out the intercommunication among the distinct units of the system.
The centre adopts a multiprocessing structure in which the distinct processing units intercommunicate between each other by means of a common information transfer bus system. The layout of the centre is shown in Fig. 2.
The group of processing functions of the centre are carried out a single type of processing unit, which can be modularly increased according to the needs of the centre. This processing unit is made by means of a microprocesser with its logic and associated periphery, with its memory and with a certain number of interfaces for the connection of devices.
According to whether these devices are peripherals for manmachine communication or transmission lines, the processing unit is referred to as a control unit 1, 2, or packet switch 3,4,5, respectively.
Every processing unit can communicate with the others through the common buses 7. There are four of these buses, 7a - 7d, in order to increase reliability and speed in communication. The acess to said buses is controlled by the bus access peripherals 27, 28, 29; 46, 47, and 48.
The console 6 which contains the separate peripheral units required for man-machine communication is connected to control units 1 and 2 by means of the appropriate peripheral interfaces. The transmission lines are divided up among the packet switches or computers 3,4, 5, being connected to them by means of the line interface board 31, 32, and 33 which will be indicated below.
The control unit functions are : Supervision of the operation of the system; automatic maintenance of the system; control of the peripherals of the system; and compiling measurements and statistics of the system.
The load that trying out these functions entails is divided up among the two control units 1,2 in the normal working of the centre. In the event of a failure, a single control unit, 1 or 2, can handle all the functions. In order to handle the failure situations, each one of the control units, 1, 2 knows the operative state of the other at all times.
Internally each control unit 1, 2 makes use of a local bus 14, 15 through which the peripherals communicate with the processer. The processer 16 or 17 executes the control programs that are stoted in its local memory 18 or 19. The peripheral devices are connected by means of their corresponding interfaces to the local bus and they interrupt the processer, in order to exchange information by means of an interruption control peripheral 20, 21. These peripheral devices comprise a peripheral memory 22, an incidence register unit 23, a control and presentation unit 24, an alarm unit 25, and a day clock 26, and make up the system console.
The peripheral memory 22 is a massive storage device that helps with programming the system. The incidence register unit 23 registers in writing all the incidences that occur in the working of the centre. The control and presentation unit allows the operator to have interactive dialogue with the machine. The alarm unit 25 contains the sound and visual alarms of the system. The day clock 26 synchronises the clocks of the separate processing units and it shows, by means of displays, the local time. At both sides of the common buses there are impedance adaptors 10, 11, 12, and 13.
The maximum number of peripherals which can be connected to each control unit is forty four.
The access to the common buses for carrying out the transfer of information to and from the rest of the units is controlled by a device referred to as a bus access peripheral, 27, 28, 29; 46, 47 and 48.
The basic functions of the packet switches are: Control of the signalling from subscribers and from the network; Control of the receiving/transmission of data by means of the line interfaces; Control of data transfer between the packet switches themselves and other packet switches by means of the common buses; Treatment of the control and supervision information exchanged with either control unit by means of the common buses; Maintenance of the subsystem; and making measurements and compiling statistics of the subsystem.
A network centre can be equipped with up to 34 packet switches.
The internal structure of a packet switch is exactly the same as that of a control unit, except that, while a control unit, which never carries out packet switching, has no line interfaces, a packet switch usually only hs4 such interfaces, although it may sometimes also have interfaces for peripherals.
Thus a packet switch consists of a local bus 34, 35, or 36 to which are connected a processoer 37, 38, or 39, a local memory 40, 41, or 42, and if the unit carries out management functions, peripheral interfaces (not shown).
The line interfaces, through which the communications lines are connected to the packet switches, are specialised for various standard communications lines, e.g. synchronic, asynchronic, HDLC/SDLC, telex, etc.
The maximum number of lines which can be connected to a packet switch depends upon the speed of these lines and on their mode of transmission, being able to vary between 11 and 44 lines.
THe above described physical structure provides the hardware medium for the programming of the system. This hardware supplies the basic devices for information transfer between their distinct units which allows, for the system programming to effect control, supervision and packet switching functions.
Information transfer between the separate units of the system takes place as is decribed hereafter.
When a peripheral or line interface 27-31 receives a control signal from its associated peripheral or line, which indicates to the interface the beginning of an information block transmission, it interupts the processer 14,15, 35, 36, or 37, by means of the interruption control peripheral 18, 19, 41, 42, or 43 respectively.
The processer prepares the direct memory access of the interface in question for the direct transfer of the information block through said interface, to the local memory, where the processer assigns local memory space 16, 17, 38, 39, or 40, and organises the direct memory access in order to catenate a block if it is necessary.
Upon completing the transfer of each block, the interface interrupts the processer once again, informing it of the length of the block. When the processer disposes of the entire block in its local memory it processes this information and prepares itself to transfer the block to the appropriate destination unit. This unit may-be the same unit or another processing unit. In the event of a transfer to another processing unit, before carrying out the transfer, the processer makes sure that the destination unit can receive the block.
Once it is sure of this, the processer asks its bus access peripheraTh25, 26, 44, 45, or 46, to capture a common bus 8 or 9.
The bus access peripheral of the source unit signals in the common bus the address of the bus access peripheral of the destination processing unit and its own address. Upon identifying its address, the destination bus access peripheral verifies that there is available space assigned to the source processer in the local memory of the destination processer. The destination bus access peripheral prepares its circuits for direct memory access and indicates this to the source bus access peripheral. Then the bus access peripheral of the source unit pulls out the block from the memory, through direct memory access, and sends it to the bus access peripheral of the destination unit, which pushes the data through direct memory access into its local memory after verifying the cyclic redundancy code.Once the transfer is complete the destination processer communicates its availability to the source processer.
If the transferred block has to go through a line interface or a peripheral interface, the data transfer from the local memory to said interface is similar to that described above for the transfer in the opposite direction. Information transfers for the purpose of control or supervision among units is carried out by means of reading or direct writing of or to the input/output registers which are disposed in the separate bus access peripherals.
The control units perform the functions of supervision, control and maintenance of the common buses.
The programs existing in the network centre are structured in accordance to the following classifications: Basic operating system programs; Communication lines control programs; Applicatios programs; Programs for developing and control centres; Utility and asstance programs; and test and maintenance programs.
The basic operating system programs operate the facjties of the system, i.e. the procJessors, memories and input/output parts of the system. The main activities that these programs perform are as follows.
Task management is the basic activity on which the whole operating system rests. By means of it the tasks are activated, prepared, blocked or delayed and the exchange of messages among tasks and with the interruption system is controlled; in accordance with the priority and reentry of each task.
For failure recovery, there are programs which avoid some failures of the system, by means of the redundant parts and the fault tolerant parts which the system has, and notifying the operator of irrecoverable failures.
For memory management, the system has programs specialised in developing the control activities of the local memories.
Bus management organises the utilisation of the common and local buses in the system, attending the interruptions from the packet switches and the control units.
The interuption control program looks after the interuptions, keeping their masking and priority in mind, and channeling them towards the intended receiver.
In load and dumping management, the dumping of loads and programs are considered, both in the local memory from/ towards store in a peripheral and from/towards another network centre.
System generation considers both parametric generation as well as dynamic reconfiguration of the system.
Peripheral control programs are specialised in the operation of each of the peripherals of the system, understanding as such,; line interfaces, peripheral memory, control and presentaion unit 22, incidence register unit 12, and the alarm unit 23.
The communication lines control programs have the functions to control the different line protocols that the system supports; transfer the information coming from the lines to the several applications processers which must process it; and receieve from the applications processers the information which they supply and transmit it by the line which is indicated to them.
The basic tasks to be carried out by these programs are operation of high speed lines using X25 procedure and operation of medium speed lines with the BSC transparent and non-transparent procedures, RETD duplex procedure and terminal control procedures with more than 1200 bps, synchronous or asynchronous.
Applications programs haye their own entity and are identified with the different functional specification of the special data transmission network in which they are based. The basic functions of the applications programs are to receive from the lines control programs the information which the lines supply, and to process it, and, to transfer to the line control programs the information generated in such processing.
Generically there are two types of application, -line concentration and switching, and some of the tasks which the applications programs carry out are, packing and unpacking data; information packet processing; control packet generation and processing; and message handling routing.
Programs for developing and management centres have the following functions; to facilitate the development of the programs, which implies compilation, assembly, debugging and test; and to provide the medium necessary for the use of the centre as a developing centre itself, as a network management centre as an added services centre. By means of this group of programmes, it is possible to use the system in management applications.
The functions of the utility and assistance programs are; to squire information during the actual working of the centre for the purposes of measurement, statistics and out-plant control of the performance of the system; and to facilitate the working of the centre. Some of the tasks which these programs carry out are; examination/altersion of the local or peripheral memory; observation of the message handling from lines, centres or the network; .lines, centres or the network; following a packet through the system and network; obtaining measurements and statistics from the network, system, subsystems, applications, tasks, centres and terminals; and dynamic dumping from local or peripheral memory or local input/output peripherals or remote control centre.
Some of these tasks are carried out "in line", during the working of the centre, and others are carried out " out of line" being based on the data collected during work in real time of the centre.
Test and maintenance programs function to provide media for the preventive maintenance of the system; and to provide, once a failure has occured and been detected, the most adequate means for its diagnostic elimination and correct operation test even under the most unfavourable conditions.
These types of programs need not be resident, and they can be loaded via operation, considering that they can be divided into two large groups.
These are machine dedicated programs, which whether run with or without control of the basic operating system, it is not possible to overlap the running of other programs; and service test programs which run under the control of the operating system concurrently with other programs which are also active.
Allrthe programs are modular and structured data, being able to be executed in packet switches as well as in control units.
It is necessary to distinguish between programs which carry out shared functions for all of the processing subsystems, and programs which carry out functions specific to some of the processing subsystems.
The pattern of programs of any processing subsystem is obtained by choosing from the different program groups mentioned above, those that carry outthe functions which the respective processing subsystem has entrusted to it ,from time to time.
The physical components of the system may be any processers, interfaces, etc. which are available and are compatable with each other and the system as a whole.
While a specific embodiment of the invention has been described and illustrated in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from the scope of the appended claims.

Claims (8)

Claims
1. An electronic system for packet swiching, comprising; four main communication buses; two control units connected to said common communication buses, each independantly capable of keeping the system in operation and carrying out measurements and statistics of the system, and controlling a plurality of peripherals of the system; a console connected to said two control units for receiving and displaying information from them; and a plurality of packet switches each connected to said common communication buses and each for controlling data from subscribers of the system, for controlling the receipt and transmission of data using line interfaces, for controlling data transfer to other packet switches and to at least one of said control units and for controlling internal maintenance, measurements and statistics for itself.
2. A system according to Claim 1, wherein there are up to 34 of said packet switches connected to said common communication buses.
3. A system according to Claim 1 or 2, wherein each said control unit comprises a local bus, a microprocesser connected to said local bus for executing control programs, a local memory connected to said local bus for storing data and control programs, an interrution control peripheral connected to said local bus and to said microprocesser for controlling activation and deactivation of said microprocesser, and two bus access peripherals, each connecting the local bus with two of the common buses for establishing communication between the unit and the common bus, and up to 44 peripheral interfaces which connect the local bus with the console and to other peripherals.
4. A system according to any preceding Claim, wherein each of said packet switches comprises a local bus, a microprocesser connected to said local bus for executing control programs, a local memory connected to said local bus for storing data and the control programs, an interrupt control peropheral connected between the local bus and the microprocesser for controlling activation and deactivation of said microprocesser, two bus access peripherals each connecting the local bus with two of the common buses for establishing communication between the unit and the common bus, and from 1 to 44 line interfaces that connnect the lines to the local bus for receiving and transmitting data to and from subscribers of the system.
5. A system according to Claim 3 or 4, wherein said local memory in either the control unit or the packet switch is modular and is enlargeable to a capacity of up to 1 megabyte, and is connected to the local bus of each of said packet switches.
6. A system according to Claim l, including four common communication buses connected to each of said two control units and each of said plurality of packet switches.
7. A system according to Claim 2 wherein said console comprises a day clock for providing clock pulses, an alarm unit which is activable upon a failure to indicate the occurence of the failure, a peripheral memory for locally storing data in said console, an incidence register unit for registering the occurence of communication between said console and either of said control units, and a display for displaying information and data to an operator of said console.
8. A packet switching system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
GB8809299A 1988-04-20 1988-04-20 Electronic system for packet switching Expired GB2217551B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8809299A GB2217551B (en) 1988-04-20 1988-04-20 Electronic system for packet switching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8809299A GB2217551B (en) 1988-04-20 1988-04-20 Electronic system for packet switching

Publications (3)

Publication Number Publication Date
GB8809299D0 GB8809299D0 (en) 1988-05-25
GB2217551A true GB2217551A (en) 1989-10-25
GB2217551B GB2217551B (en) 1992-06-03

Family

ID=10635500

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8809299A Expired GB2217551B (en) 1988-04-20 1988-04-20 Electronic system for packet switching

Country Status (1)

Country Link
GB (1) GB2217551B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2271041A (en) * 1992-09-23 1994-03-30 Netcomm Ltd Data network switch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2271041A (en) * 1992-09-23 1994-03-30 Netcomm Ltd Data network switch
GB2271041B (en) * 1992-09-23 1996-03-20 Netcomm Ltd Data network switch

Also Published As

Publication number Publication date
GB8809299D0 (en) 1988-05-25
GB2217551B (en) 1992-06-03

Similar Documents

Publication Publication Date Title
CA1181512A (en) Digital information switching system
KR0131339B1 (en) Interprocessor switching network
US3921141A (en) Malfunction monitor control circuitry for central data processor of digital communication system
US3810121A (en) Timing generator circuit for central data processor of digital communication system
US4862350A (en) Architecture for a distributive microprocessing system
US3838261A (en) Interrupt control circuit for central processor of digital communication system
GB1081811A (en) Data handling system
US6667960B1 (en) Protocol for identifying components in a point-to-point computer system
JPH0797874B2 (en) Multiprocessor computer
EP0183431B1 (en) System control network for multiple processor modules
US4649534A (en) Telecomputer package switching system
EP0073239A1 (en) Multi-processor office system complex
GB2217551A (en) Electronic system for packet switching
CA1236923A (en) Architecture for a distributive microprocessing system
CA1269171A (en) Circuit for ccis data transfer between a cpu and a plurality of terminal equipment controllers
KR980013469A (en) Interprocessor communication device in all electronic exchanges
JPH06236299A (en) Method and device for monitoring system
CA1229400A (en) Telecommunications packet switching system
JPH01278146A (en) Packet switching electronic system
JP2859229B2 (en) Monitoring and control equipment
KR0153017B1 (en) Rink process system of the full electronic switching system having memory and line inter-facing unit
KR950011481B1 (en) An electronic exchanger
PT87258B (en) ELECTRONIC TELECOMPUTER SYSTEM FOR PACKAGE SWITCHING
Clark et al. Traffic Service Position System No. 1B: Hardware Configuration
KR920008791B1 (en) Signal relying system

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930420