GB1523517A - Method of manufacturing a monolithic - Google Patents

Method of manufacturing a monolithic

Info

Publication number
GB1523517A
GB1523517A GB5253276A GB5253276A GB1523517A GB 1523517 A GB1523517 A GB 1523517A GB 5253276 A GB5253276 A GB 5253276A GB 5253276 A GB5253276 A GB 5253276A GB 1523517 A GB1523517 A GB 1523517A
Authority
GB
United Kingdom
Prior art keywords
transistor
zone
circuit
dec
injection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5253276A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of GB1523517A publication Critical patent/GB1523517A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]
    • H01L27/0244I2L structures integrated in combination with analog structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8226Bipolar technology comprising merged transistor logic or integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
GB5253276A 1975-12-22 1976-12-16 Method of manufacturing a monolithic Expired GB1523517A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752557911 DE2557911C2 (de) 1975-12-22 1975-12-22 Verfahren zum Herstellen einer monolithisch integrierten Schaltung

Publications (1)

Publication Number Publication Date
GB1523517A true GB1523517A (en) 1978-09-06

Family

ID=5965236

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5253276A Expired GB1523517A (en) 1975-12-22 1976-12-16 Method of manufacturing a monolithic

Country Status (4)

Country Link
DE (1) DE2557911C2 (de)
FR (1) FR2336798A1 (de)
GB (1) GB1523517A (de)
IT (1) IT1065296B (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2835330C3 (de) * 1978-08-11 1982-03-11 Siemens AG, 1000 Berlin und 8000 München Integrierter bipolarer Halbleiterschaltkreis sowie Verfahren zu seiner Herstellung
DE3020609C2 (de) * 1979-05-31 1985-11-07 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Verfahren zum Herstellen einer integrierten Schaltung mit wenigstens einem I↑2↑L-Element

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1559608A (de) * 1967-06-30 1969-03-14
US3909807A (en) * 1974-09-03 1975-09-30 Bell Telephone Labor Inc Integrated circuit memory cell

Also Published As

Publication number Publication date
FR2336798A1 (fr) 1977-07-22
FR2336798B1 (de) 1982-10-22
IT1065296B (it) 1985-02-25
DE2557911A1 (de) 1977-06-30
DE2557911C2 (de) 1982-11-04

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee