EP0348626A3 - Verfahren zur Herstellen von isolierten vertikalbipolaren und JFET-Transistoren - Google Patents

Verfahren zur Herstellen von isolierten vertikalbipolaren und JFET-Transistoren Download PDF

Info

Publication number
EP0348626A3
EP0348626A3 EP19890107212 EP89107212A EP0348626A3 EP 0348626 A3 EP0348626 A3 EP 0348626A3 EP 19890107212 EP19890107212 EP 19890107212 EP 89107212 A EP89107212 A EP 89107212A EP 0348626 A3 EP0348626 A3 EP 0348626A3
Authority
EP
European Patent Office
Prior art keywords
vpnp
region
jfet
junction isolation
isolated vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890107212
Other languages
English (en)
French (fr)
Other versions
EP0348626B1 (de
EP0348626A2 (de
Inventor
Michael R. Seacrist
Joe R. Trogolo
Kenneth M. Bell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to EP94112898A priority Critical patent/EP0627767B1/de
Publication of EP0348626A2 publication Critical patent/EP0348626A2/de
Publication of EP0348626A3 publication Critical patent/EP0348626A3/de
Application granted granted Critical
Publication of EP0348626B1 publication Critical patent/EP0348626B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34—Bipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10W10/031—
    • H10W10/30—

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
EP89107212A 1988-06-27 1989-04-21 Verfahren zur Herstellung von isolierten vertikalbipolaren und JFET-Transistoren und entsprechender IC Expired - Lifetime EP0348626B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP94112898A EP0627767B1 (de) 1988-06-27 1989-04-21 Verfahren zur Herstellung von JFET-Transistoren und Kondensatoren

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21164188A 1988-06-27 1988-06-27
US211641 1988-06-27

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP94112898A Division EP0627767B1 (de) 1988-06-27 1989-04-21 Verfahren zur Herstellung von JFET-Transistoren und Kondensatoren
EP94112898.5 Division-Into 1989-04-21

Publications (3)

Publication Number Publication Date
EP0348626A2 EP0348626A2 (de) 1990-01-03
EP0348626A3 true EP0348626A3 (de) 1991-07-31
EP0348626B1 EP0348626B1 (de) 1998-08-05

Family

ID=22787775

Family Applications (2)

Application Number Title Priority Date Filing Date
EP89107212A Expired - Lifetime EP0348626B1 (de) 1988-06-27 1989-04-21 Verfahren zur Herstellung von isolierten vertikalbipolaren und JFET-Transistoren und entsprechender IC
EP94112898A Expired - Lifetime EP0627767B1 (de) 1988-06-27 1989-04-21 Verfahren zur Herstellung von JFET-Transistoren und Kondensatoren

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP94112898A Expired - Lifetime EP0627767B1 (de) 1988-06-27 1989-04-21 Verfahren zur Herstellung von JFET-Transistoren und Kondensatoren

Country Status (4)

Country Link
EP (2) EP0348626B1 (de)
JP (2) JPH0691192B2 (de)
KR (1) KR0169097B1 (de)
DE (2) DE68928763T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2305776B (en) * 1995-09-28 1999-11-17 Gresham Sensor Technology Limi Charge amplifier
EP0849771A1 (de) * 1996-12-19 1998-06-24 Motorola Semiconducteurs S.A. Verfahren zum Herstellen eines Verarmungs-JFET und Verfahren zum Herstellen eines Verarmungs-JFET und eines Bipolartransistors auf einem Halbleitersubstrat
JP3530414B2 (ja) 1999-03-26 2004-05-24 三洋電機株式会社 半導体装置
US10500770B2 (en) 2010-03-02 2019-12-10 So-Semi Technologies, Llc LED packaging with integrated optics and methods of manufacturing the same
US11482521B2 (en) * 2020-02-06 2022-10-25 Globalfoundries U.S. Inc. Integrated circuit with P-N-P junction and vertically aligned field effect transistor, and method to form same
CN113097309B (zh) * 2021-03-31 2024-09-27 上海晶丰明源半导体股份有限公司 结型场效应晶体管及半导体器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1559609A (de) * 1967-06-30 1969-03-14
EP0006119A1 (de) * 1978-06-13 1980-01-09 International Business Machines Corporation Integrierter Sperrschicht-Feldeffekt-Transistor und Verfahren zu dessen Herstellung

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322738A (en) * 1980-01-21 1982-03-30 Texas Instruments Incorporated N-Channel JFET device compatible with existing bipolar integrated circuit processing techniques
JPS57128073A (en) * 1981-12-21 1982-08-09 Hitachi Ltd Semiconductor integrated circuit device
US4419812A (en) * 1982-08-23 1983-12-13 Ncr Corporation Method of fabricating an integrated circuit voltage multiplier containing a parallel plate capacitor
JPS60117765A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1559609A (de) * 1967-06-30 1969-03-14
EP0006119A1 (de) * 1978-06-13 1980-01-09 International Business Machines Corporation Integrierter Sperrschicht-Feldeffekt-Transistor und Verfahren zu dessen Herstellung

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS, vol. 61, no. 17, November 1988, pages 125,128, Hasbrook Heights, NJ, US; S. WEBER: "TI's new linear process powers an advanced family of OP amps" *
ELEKTRONIK, vol. 26, no. 11, November 1977, page 22; "Le technologie BIFET" *

Also Published As

Publication number Publication date
JPH04226061A (ja) 1992-08-14
JPH0691192B2 (ja) 1994-11-14
DE68928763T2 (de) 1999-04-08
KR0169097B1 (ko) 1999-01-15
DE68928763D1 (de) 1998-09-10
EP0627767B1 (de) 2002-11-06
DE68929433D1 (de) 2002-12-12
EP0348626B1 (de) 1998-08-05
EP0348626A2 (de) 1990-01-03
DE68929433T2 (de) 2003-06-26
JPH0251264A (ja) 1990-02-21
EP0627767A1 (de) 1994-12-07
KR900001036A (ko) 1990-01-31

Similar Documents

Publication Publication Date Title
GB1522958A (en) Fabrication of semiconductor devices
KR970054342A (ko) 베이스 결정박막 바이폴러 트랜지스터의 소자격리와 컬렉터－베이스 자기정렬의 동시 형성방법
GB1536988A (en) Semiconductor devices
KR860007863A (ko) 반도체 장치
GB1470211A (en) Semiconductor devices
HK41690A (en) Process for producing a semiconductor device
SE0200414D0 (sv) Semiconductor fabrication process lateral pnp transistor, and integrated circuit
EP0348626A3 (de) Verfahren zur Herstellen von isolierten vertikalbipolaren und JFET-Transistoren
EP0310047A3 (de) Doppel-diffundierter MOSFET
EP0221742A3 (en) Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions
EP0347550A3 (de) Verfahren zur Herstellung von isolierten vertikalen und superverstärkenden Bipolar-Transistoren
EP0656660A3 (de) BICMOS-Verfahren zum Ermöglichen vom unschmolzenen Vorrichtungen
KR910015063A (ko) 상보형 쌍극 트랜지스터
KR940001257B1 (ko) 반도체 소자 제조방법
GB1241809A (en) A method for manufacturing a semiconductor device
EP0316562A3 (de) Halbleiterbipolartransistor mit Basis und Emitterstruktur in einem Graben und Verfahren zu seiner Herstellung
JPS5762552A (en) Manufacture of semiconductor device
JPS56100460A (en) Bipolar mos semiconductor device and manufacture thereof
SE0103805D0 (sv) Lateral PNP transistor device, integrated circuit, and fabrication process thereof
JPS63136659A (ja) 半導体集積回路の製造方法
GB1523517A (en) Method of manufacturing a monolithic
JPS57143855A (en) Semiconductor integrated circuit device
TW283794B (en) Fabrication method of transistor with vertical bipolar junction
GB1309502A (en) Semiconductor device and method of making the same
GB2005071A (en) A junction field effect transistor logic semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT NL

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT NL

17P Request for examination filed

Effective date: 19920102

17Q First examination report despatched

Effective date: 19931029

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

DX Miscellaneous (deleted)
AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT NL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT

Effective date: 19980805

Ref country code: FR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19980805

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19980805

REF Corresponds to:

Ref document number: 68928763

Country of ref document: DE

Date of ref document: 19980910

EN Fr: translation not filed
NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20070313

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20070430

Year of fee payment: 19

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20080421

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20081101

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080421