GB1447680A - Data processing systems - Google Patents

Data processing systems

Info

Publication number
GB1447680A
GB1447680A GB5705473A GB5705473A GB1447680A GB 1447680 A GB1447680 A GB 1447680A GB 5705473 A GB5705473 A GB 5705473A GB 5705473 A GB5705473 A GB 5705473A GB 1447680 A GB1447680 A GB 1447680A
Authority
GB
United Kingdom
Prior art keywords
address
page
store
real
darp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5705473A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1447680A publication Critical patent/GB1447680A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)

Abstract

1447680 Data processing system SIEMENS AG 10 Dec 1973 [18 Jan 1973] 57054/73 Heading G4A A data processing system having a virtual memory system is arranged to transfer data between the working store and peripheral devices, there being a chain list store containing an entry for each real page in the working store, each entry containing the real address of the next page in the working store to be used in a data transfer, and means arranged when a page boundary is crossed during a transfer to access the chain list store to obtain the real address of the next page to be used in the transfer. Accessing the chain list store may also be used to locate the next page during normal program operation as well as for I/O operations. In an I/O operation a real working store address consisting of a page part and a byte part is stored in register DARP to access, via decoder DEC1, a section DSP of the working store from or to which data is transferred to or from peripherals PG. The byte part of the address is incremented (or decremented) in adder ADD to produce a new real address which is transferred to DARP to continue the I/O operation. If a page boundary is crossed, indicated by a carry from the highest bit position of the byte part of the address, a signal U12 prevents the transfer of the old page part of the address to register DARP (the carry not having been added into the page part). The old page part is concatenated with a base address from a register KBR to access, via decoder DEC2, the chain list store KSP which may be permanently resident in the working store. From the resulting accessed entry corresponding to the old page a new, real page part is obtained and is fed to register DARP together with the modified byte part from adder ADD to form a new real address to continue the I/O operation. The chain list store may contain in each entry two real page addresses corresponding to the succeeding and preceding pages in the sequence of virtual pages for use when the adder ADD increments and decrements respectively the address in DARP, the appropriate address being selected in accordance with a single bit in the I/O command which also serves to control the adder appropriately. The chain list store may also contain conventional checking bits to initiate appropriate action in the event of a fault. Several modifications are mentioned, e.g. the base register KBR may be dispensed with and register DARP may be replaced by a store containing one address for each of a number of I/O operations.
GB5705473A 1973-01-18 1973-12-10 Data processing systems Expired GB1447680A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19732302379 DE2302379C3 (en) 1973-01-18 1973-01-18 Circuit arrangement for performing sequentially running input / output operations in a data processing system working with virtual addressing
DE19732314070 DE2314070C3 (en) 1973-01-18 1973-03-21 Method and circuit arrangement for creating the entries of a linked list memory in a method and a circuit arrangement for performing sequentially running input / output operations in a data processing system operating with virtual addressing
DE19742444406 DE2444406A1 (en) 1973-01-18 1974-09-17 METHOD FOR PERFORMING INPUT / OUTPUT OPERATIONS IN A DATA PROCESSING SYSTEM WORKING WITH VIRTUAL ADDRESSING

Publications (1)

Publication Number Publication Date
GB1447680A true GB1447680A (en) 1976-08-25

Family

ID=27184986

Family Applications (2)

Application Number Title Priority Date Filing Date
GB5705473A Expired GB1447680A (en) 1973-01-18 1973-12-10 Data processing systems
GB691174A Expired GB1454357A (en) 1973-01-18 1974-02-15 Data processing systems

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB691174A Expired GB1454357A (en) 1973-01-18 1974-02-15 Data processing systems

Country Status (6)

Country Link
BE (3) BE809930A (en)
DE (3) DE2302379C3 (en)
FR (4) FR2214923B1 (en)
GB (2) GB1447680A (en)
LU (2) LU69174A1 (en)
NL (3) NL7400649A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2437300A1 (en) * 1978-09-26 1980-04-25 Cii Honeywell Bull Stored data checking technique - determines whether items are within page limits by using address calculator which performs addition or subtraction from origin

Also Published As

Publication number Publication date
BE809930A (en) 1974-07-18
BE812640R (en) 1974-09-23
FR2214923A1 (en) 1974-08-19
DE2302379A1 (en) 1974-08-15
FR2285658B2 (en) 1978-09-08
DE2444406A1 (en) 1976-03-25
NL7403609A (en) 1974-09-24
FR2285658A2 (en) 1976-04-16
FR2222696B2 (en) 1978-09-08
DE2314070A1 (en) 1974-10-10
FR108891A (en)
GB1454357A (en) 1976-11-03
BE833520R (en) 1976-03-17
NL7400649A (en) 1974-07-22
FR2222696A2 (en) 1974-10-18
LU69174A1 (en) 1974-04-08
DE2302379C3 (en) 1978-12-07
NL7510623A (en) 1976-03-19
DE2314070C3 (en) 1980-08-07
DE2314070B2 (en) 1979-11-29
DE2302379B2 (en) 1977-03-31
LU69663A1 (en) 1974-10-17
FR2214923B1 (en) 1978-08-04

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee