GB1514555A - Data processing systems - Google Patents

Abstract

1514555 Data processing system SIEMENS AG 16 Sept 1975 [17 Sept 1974] 38092/75 Addition to 1447680 Heading G4A] The Parent Specification is modified to enable larger storage systems to be handled by dividing the data in the chain list store into pages in a conventional hierarchical manner using a higher order segment table providing the base addresses of a group of pages each storing chain list entries. Thus the chain list pages can be treated within the virtual memory system in exactly the same way as other pages of stored data, i.e. they can be transferred in and out of the working store as required. Input/output operations between peripherals and the working store DM of a virtual memory system proceed as in the Parent Specification by incrementing or decrementing (depending on signal DTB) the byte address part DR1 of a real address comprising byte DR1 and page DR2 parts for each byte of data transferred until a page boundary is crossed indicated by a carry PCR from register DR1. Since the next page into or from which data is to be transferred is not necessarily stored in the next real page address the old page part DR2 of the address is transferred to register CR4 which, in combination with the current chain list page PCT base address in register CR3, addresses the appropriate chain list entry. Each such entry, as in the Parent, provides the real page address of the next page which is to be used in the I/O operation which is fed to register DR2 to enable the operation to continue. Each entry however also includes a four bit indication (bits 5-8) and a bit S which is "1" when the next chain list entry is not within the same page. In such a case the four bits are fed at any time during execution of the I/O operation in the newly selected page to register CR2 which, in combination with register CR1 which contains the fixed base address of the higher order segment table SPT, addresses the segment table. Each entry in the segment table contains two addresses one of which is selected in unit SC, in accordance with whether the I/O operation was proceeding with incrementing or decrementing of the byte addresses, and fed to register CR3 where it provides the base address of the next chain list page. This page is accessed when the next page boundary is crossed during execution of the I/O operation at an entry determined by the contents of register CR4, transferred from DR2 as before, to provide the real page address of the page which is to be used in the I/O operation. This arrangement allows any access to the chain list store to be completed in a single store access since even when a chain list page boundary is crossed the address of the next chain list page is obtained during execution of the I/O operation before the access to the chain list is required. The hierarchy of the chain list may be extended by providing three or more levels depending on the number of entries required and the size of a page.