FR2214923B1 - - Google Patents

Info

Publication number
FR2214923B1
FR2214923B1 FR7401140A FR7401140A FR2214923B1 FR 2214923 B1 FR2214923 B1 FR 2214923B1 FR 7401140 A FR7401140 A FR 7401140A FR 7401140 A FR7401140 A FR 7401140A FR 2214923 B1 FR2214923 B1 FR 2214923B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7401140A
Other languages
French (fr)
Other versions
FR2214923A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2214923A1 publication Critical patent/FR2214923A1/fr
Application granted granted Critical
Publication of FR2214923B1 publication Critical patent/FR2214923B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
FR7401140A 1973-01-18 1974-01-14 Expired FR2214923B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19732302379 DE2302379C3 (en) 1973-01-18 1973-01-18 Circuit arrangement for performing sequentially running input / output operations in a data processing system working with virtual addressing
DE19732314070 DE2314070C3 (en) 1973-01-18 1973-03-21 Method and circuit arrangement for creating the entries of a linked list memory in a method and a circuit arrangement for performing sequentially running input / output operations in a data processing system operating with virtual addressing
DE19742444406 DE2444406A1 (en) 1973-01-18 1974-09-17 METHOD FOR PERFORMING INPUT / OUTPUT OPERATIONS IN A DATA PROCESSING SYSTEM WORKING WITH VIRTUAL ADDRESSING

Publications (2)

Publication Number Publication Date
FR2214923A1 FR2214923A1 (en) 1974-08-19
FR2214923B1 true FR2214923B1 (en) 1978-08-04

Family

ID=27184986

Family Applications (4)

Application Number Title Priority Date Filing Date
FR108891D Active FR108891A (en) 1973-01-18
FR7401140A Expired FR2214923B1 (en) 1973-01-18 1974-01-14
FR7409060A Expired FR2222696B2 (en) 1973-01-18 1974-03-18
FR7527583A Granted FR2285658A2 (en) 1973-01-18 1975-09-09 PROCEDURE AND CIRCUIT FOR PERFORMING INPUT / OUTPUT OPERATIONS TAKING PLACE IN SEQUENCE IN A DATA PROCESSING INSTALLATION WHICH OPERATES WITH VIRTUAL ADDRESSING

Family Applications Before (1)

Application Number Title Priority Date Filing Date
FR108891D Active FR108891A (en) 1973-01-18

Family Applications After (2)

Application Number Title Priority Date Filing Date
FR7409060A Expired FR2222696B2 (en) 1973-01-18 1974-03-18
FR7527583A Granted FR2285658A2 (en) 1973-01-18 1975-09-09 PROCEDURE AND CIRCUIT FOR PERFORMING INPUT / OUTPUT OPERATIONS TAKING PLACE IN SEQUENCE IN A DATA PROCESSING INSTALLATION WHICH OPERATES WITH VIRTUAL ADDRESSING

Country Status (6)

Country Link
BE (3) BE809930A (en)
DE (3) DE2302379C3 (en)
FR (4) FR2214923B1 (en)
GB (2) GB1447680A (en)
LU (2) LU69174A1 (en)
NL (3) NL7400649A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2437300A1 (en) * 1978-09-26 1980-04-25 Cii Honeywell Bull Stored data checking technique - determines whether items are within page limits by using address calculator which performs addition or subtraction from origin

Also Published As

Publication number Publication date
BE809930A (en) 1974-07-18
FR2222696B2 (en) 1978-09-08
DE2314070A1 (en) 1974-10-10
FR2285658A2 (en) 1976-04-16
BE833520R (en) 1976-03-17
DE2302379B2 (en) 1977-03-31
FR2285658B2 (en) 1978-09-08
LU69663A1 (en) 1974-10-17
NL7400649A (en) 1974-07-22
DE2314070B2 (en) 1979-11-29
FR2222696A2 (en) 1974-10-18
DE2302379C3 (en) 1978-12-07
GB1447680A (en) 1976-08-25
LU69174A1 (en) 1974-04-08
FR108891A (en)
DE2314070C3 (en) 1980-08-07
BE812640R (en) 1974-09-23
NL7510623A (en) 1976-03-19
FR2214923A1 (en) 1974-08-19
DE2444406A1 (en) 1976-03-25
GB1454357A (en) 1976-11-03
NL7403609A (en) 1974-09-24
DE2302379A1 (en) 1974-08-15

Similar Documents

Publication Publication Date Title
AR201758A1 (en)
AU476761B2 (en)
AU465372B2 (en)
AR201235Q (en)
AR201231Q (en)
AU474593B2 (en)
AU474511B2 (en)
AU474838B2 (en)
AU471343B2 (en)
AU465453B2 (en)
AU465434B2 (en)
AU450229B2 (en)
AU476714B2 (en)
AR201229Q (en)
AU466283B2 (en)
AU476696B2 (en)
AU472848B2 (en)
AR199451A1 (en)
AU477823B2 (en)
FR2222696A2 (en)
AR197627A1 (en)
AU461342B2 (en)
AR200885A1 (en)
AR210729A1 (en)
AR193950A1 (en)

Legal Events

Date Code Title Description
ST Notification of lapse