GB1393570A - Device for electrical counting - Google Patents

Device for electrical counting

Info

Publication number
GB1393570A
GB1393570A GB5586272A GB5586272A GB1393570A GB 1393570 A GB1393570 A GB 1393570A GB 5586272 A GB5586272 A GB 5586272A GB 5586272 A GB5586272 A GB 5586272A GB 1393570 A GB1393570 A GB 1393570A
Authority
GB
United Kingdom
Prior art keywords
memory
circuit
adder
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5586272A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of GB1393570A publication Critical patent/GB1393570A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/002—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Manipulation Of Pulses (AREA)
  • Dram (AREA)

Abstract

1393570 Counters; bi-stable circuits BURROUGHS CORP 4 Dec 1972 [27 Dec 1971] 55862/72 Heading G4D [Also in Division H3] Each stage of a counter, for instance in a large scale integrated circuit, comprises a halfadder circuit 31 and a two state memory circuit 41 connected together as shown in Fig. 3. The adder 31 receives an input 311 to be counted and the read output 413 of the memory and delivers a carry output 314 to the next stage and a sum output 313 to a setting input 411 of the memory. In Fig. 4 the half-adder comprises OR-gate 317, NAND-gates 316, 319 and inverters 143, 318; the memory 41 comprises a flipflop circuit having three MOSFET's 421, 423, 425 and two inverters 422, 424. A clock pulse at terminal 414 causes the state of the memory circuit to change to that of the adder output 313. The memory also includes three further dating transistors 65-67; MOSFET 65 allows a zero setting voltage V 0 to be applied to the flip-flop while 66, 67 control the application of forcing signals. The memory is a dynamic one, so terminals 417, 418 provide an input for a regeneration signal. Other, conventional, memory circuits may be substituted.
GB5586272A 1971-12-27 1972-12-04 Device for electrical counting Expired GB1393570A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7146765A FR2166483A5 (en) 1971-12-27 1971-12-27

Publications (1)

Publication Number Publication Date
GB1393570A true GB1393570A (en) 1975-05-07

Family

ID=9088141

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5586272A Expired GB1393570A (en) 1971-12-27 1972-12-04 Device for electrical counting

Country Status (7)

Country Link
BE (1) BE792638A (en)
BR (1) BR7205847D0 (en)
DE (1) DE2257622A1 (en)
FR (1) FR2166483A5 (en)
GB (1) GB1393570A (en)
IT (1) IT971810B (en)
NL (1) NL7216420A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104538A (en) * 1977-04-29 1978-08-01 Fairchild Camera And Instrument Corporation Digitally synthesized back-up frequency
JPS6240824A (en) * 1985-08-19 1987-02-21 Toshiba Corp Synchronous type binary counter
FR2595520B1 (en) * 1986-03-07 1993-09-10 Thomson Csf BASIC BINARY COUNTER, SYNCHRONOUS BINARY COUNTER AND FREQUENCY DIVIDER USING THE BASIC COUNTER
JPH05216624A (en) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp Arithmetic unit

Also Published As

Publication number Publication date
FR2166483A5 (en) 1973-08-17
BE792638A (en) 1973-03-30
DE2257622A1 (en) 1973-07-05
NL7216420A (en) 1973-06-29
IT971810B (en) 1974-05-10
BR7205847D0 (en) 1974-08-22

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Legal Events

Date Code Title Description
PS Patent sealed
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee