GB1384830A - Polyphase logical circuits - Google Patents

Polyphase logical circuits

Info

Publication number
GB1384830A
GB1384830A GB4004773A GB4004773A GB1384830A GB 1384830 A GB1384830 A GB 1384830A GB 4004773 A GB4004773 A GB 4004773A GB 4004773 A GB4004773 A GB 4004773A GB 1384830 A GB1384830 A GB 1384830A
Authority
GB
United Kingdom
Prior art keywords
level
aug
division
charge
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4004773A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1384830A publication Critical patent/GB1384830A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Shift Register Type Memory (AREA)

Abstract

1384830 Shift registers HITACHI Ltd 23 Aug 1973 [25 Aug 1972] 40047/73 Heading G4C [Also in Division H3] A 4-phase dynamic shift register comprises two C-MOS logic circuits (see also Division H3) connected in cascade. In operation, when clock pulse # 1 reaches the "O" level, T 23 is turned off and T 21 conducts to charge an output capacitance C L and the parasitic capacitances associated with logic circuit LB 3 via T 22 . Subsequently when # 1 returns to the "1" level, T 23 is rendered conductive and the charge or discharge of C L is determined by the level of the input signal Vin to the logic transistor T 24 during the remainder of the period of conduction of T 22 . The second circuit functions in a similar manner during the # 3 # 3+4 periods. The FETs T 22 , T 32 may each be replaced by a pair of parallel connected FETs driven by separate clock pulse trains # 1 , # 2 ; # 3 , # 4 .
GB4004773A 1972-08-25 1973-08-23 Polyphase logical circuits Expired GB1384830A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47084574A JPS4940851A (en) 1972-08-25 1972-08-25

Publications (1)

Publication Number Publication Date
GB1384830A true GB1384830A (en) 1975-02-26

Family

ID=13834430

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4004773A Expired GB1384830A (en) 1972-08-25 1973-08-23 Polyphase logical circuits

Country Status (7)

Country Link
JP (1) JPS4940851A (en)
CH (1) CH567840A5 (en)
DE (1) DE2337070A1 (en)
FR (1) FR2197278B1 (en)
GB (1) GB1384830A (en)
IT (1) IT993007B (en)
NL (1) NL7309964A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5196275A (en) * 1975-02-20 1976-08-24
DE2556735C3 (en) * 1975-12-17 1979-02-01 Deutsche Itt Industries Gmbh, 7800 Freiburg MOS power stage for generating two non-overlapping clock signals
JPS52115637A (en) * 1976-03-24 1977-09-28 Sharp Corp Mos transistor circuit
US4044270A (en) * 1976-06-21 1977-08-23 Rockwell International Corporation Dynamic logic gate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1127687A (en) * 1965-12-13 1968-09-18 Rca Corp Logic circuitry
US3573487A (en) * 1969-03-05 1971-04-06 North American Rockwell High speed multiphase gate
US3601627A (en) * 1970-07-13 1971-08-24 North American Rockwell Multiple phase logic gates for shift register stages

Also Published As

Publication number Publication date
CH567840A5 (en) 1975-10-15
IT993007B (en) 1975-09-30
NL7309964A (en) 1974-02-27
FR2197278A1 (en) 1974-03-22
DE2337070A1 (en) 1974-03-21
FR2197278B1 (en) 1976-05-28
JPS4940851A (en) 1974-04-17

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees