GB1305319A - - Google Patents
Info
- Publication number
- GB1305319A GB1305319A GB2323671*A GB2323671A GB1305319A GB 1305319 A GB1305319 A GB 1305319A GB 2323671 A GB2323671 A GB 2323671A GB 1305319 A GB1305319 A GB 1305319A
- Authority
- GB
- United Kingdom
- Prior art keywords
- cells
- points
- tracks
- terminals
- providing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001465 metallisation Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US76245968A | 1968-09-25 | 1968-09-25 | |
| US1684070A | 1970-03-05 | 1970-03-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1305319A true GB1305319A (enrdf_load_stackoverflow) | 1973-01-31 |
Family
ID=34315863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2323671*A Expired GB1305319A (enrdf_load_stackoverflow) | 1968-09-25 | 1971-04-19 |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1305319A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2153590A (en) * | 1984-02-01 | 1985-08-21 | Ramesh Chandra Varshney | Matrix of functional circuits on a semiconductor wafer |
-
1971
- 1971-04-19 GB GB2323671*A patent/GB1305319A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2153590A (en) * | 1984-02-01 | 1985-08-21 | Ramesh Chandra Varshney | Matrix of functional circuits on a semiconductor wafer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PE20 | Patent expired after termination of 20 years |