GB1266243A - - Google Patents

Info

Publication number
GB1266243A
GB1266243A GB1266243DA GB1266243A GB 1266243 A GB1266243 A GB 1266243A GB 1266243D A GB1266243D A GB 1266243DA GB 1266243 A GB1266243 A GB 1266243A
Authority
GB
United Kingdom
Prior art keywords
area
substrate
layer
silicon nitride
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1266243A publication Critical patent/GB1266243A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/03—Diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
GB1266243D 1968-12-30 1969-10-14 Expired GB1266243A (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US78776968A 1968-12-30 1968-12-30

Publications (1)

Publication Number Publication Date
GB1266243A true GB1266243A (https=) 1972-03-08

Family

ID=25142467

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1266243D Expired GB1266243A (https=) 1968-12-30 1969-10-14

Country Status (6)

Country Link
US (1) US3574010A (https=)
JP (1) JPS4811511B1 (https=)
DE (1) DE1961634B2 (https=)
FR (1) FR2027308B1 (https=)
GB (1) GB1266243A (https=)
NL (1) NL6917012A (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2021923B2 (de) * 1970-05-05 1976-07-22 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen eines feldeffekttransistors mit isolierter gateelektrode
JPS4926747B1 (https=) * 1970-10-09 1974-07-11
US3841926A (en) * 1973-01-02 1974-10-15 Ibm Integrated circuit fabrication process
CA1008564A (en) * 1974-04-18 1977-04-12 Robert L. Luce Method of mos circuit fabrication
US4003126A (en) * 1974-09-12 1977-01-18 Canadian Patents And Development Limited Method of making metal oxide semiconductor devices
FR2294544A1 (fr) * 1974-12-13 1976-07-09 Thomson Csf Procede de fabrication, en circuit integre, de transistors a effet de champ destines a fonctionner en tres haute frequence, et structure ou dispositifs obtenus
US4043025A (en) * 1975-05-08 1977-08-23 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
US3975220A (en) * 1975-09-05 1976-08-17 International Business Machines Corporation Diffusion control for controlling parasitic capacitor effects in single FET structure arrays
JPS5326017U (https=) * 1976-08-13 1978-03-06
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4222164A (en) * 1978-12-29 1980-09-16 International Business Machines Corporation Method of fabrication of self-aligned metal-semiconductor field effect transistors
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4263066A (en) * 1980-06-09 1981-04-21 Varian Associates, Inc. Process for concurrent formation of base diffusion and p+ profile from single source predeposition
US4317276A (en) * 1980-06-12 1982-03-02 Teletype Corporation Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer
US4389768A (en) * 1981-04-17 1983-06-28 International Business Machines Corporation Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors
JPS5825788U (ja) * 1981-08-17 1983-02-18 三菱自動車工業株式会社 トラツクの車体構造
DE102006030261B4 (de) * 2006-06-30 2011-01-20 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit reduzierter Bordiffusion und Transistor

Also Published As

Publication number Publication date
NL6917012A (https=) 1970-07-02
DE1961634B2 (de) 1972-01-13
FR2027308B1 (https=) 1973-10-19
DE1961634A1 (de) 1970-07-09
JPS4811511B1 (https=) 1973-04-13
FR2027308A1 (https=) 1970-09-25
US3574010A (en) 1971-04-06

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees