NL6917012A - - Google Patents
Info
- Publication number
- NL6917012A NL6917012A NL6917012A NL6917012A NL6917012A NL 6917012 A NL6917012 A NL 6917012A NL 6917012 A NL6917012 A NL 6917012A NL 6917012 A NL6917012 A NL 6917012A NL 6917012 A NL6917012 A NL 6917012A
- Authority
- NL
- Netherlands
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
- H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/03—Diffusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US78776968A | 1968-12-30 | 1968-12-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL6917012A true NL6917012A (https=) | 1970-07-02 |
Family
ID=25142467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL6917012A NL6917012A (https=) | 1968-12-30 | 1969-11-12 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3574010A (https=) |
| JP (1) | JPS4811511B1 (https=) |
| DE (1) | DE1961634B2 (https=) |
| FR (1) | FR2027308B1 (https=) |
| GB (1) | GB1266243A (https=) |
| NL (1) | NL6917012A (https=) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2021923B2 (de) * | 1970-05-05 | 1976-07-22 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zum herstellen eines feldeffekttransistors mit isolierter gateelektrode |
| JPS4926747B1 (https=) * | 1970-10-09 | 1974-07-11 | ||
| US3841926A (en) * | 1973-01-02 | 1974-10-15 | Ibm | Integrated circuit fabrication process |
| CA1008564A (en) * | 1974-04-18 | 1977-04-12 | Robert L. Luce | Method of mos circuit fabrication |
| US4003126A (en) * | 1974-09-12 | 1977-01-18 | Canadian Patents And Development Limited | Method of making metal oxide semiconductor devices |
| FR2294544A1 (fr) * | 1974-12-13 | 1976-07-09 | Thomson Csf | Procede de fabrication, en circuit integre, de transistors a effet de champ destines a fonctionner en tres haute frequence, et structure ou dispositifs obtenus |
| US4043025A (en) * | 1975-05-08 | 1977-08-23 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
| US3975220A (en) * | 1975-09-05 | 1976-08-17 | International Business Machines Corporation | Diffusion control for controlling parasitic capacitor effects in single FET structure arrays |
| JPS5326017U (https=) * | 1976-08-13 | 1978-03-06 | ||
| US4190466A (en) * | 1977-12-22 | 1980-02-26 | International Business Machines Corporation | Method for making a bipolar transistor structure utilizing self-passivating diffusion sources |
| US4222164A (en) * | 1978-12-29 | 1980-09-16 | International Business Machines Corporation | Method of fabrication of self-aligned metal-semiconductor field effect transistors |
| DE2926874A1 (de) * | 1979-07-03 | 1981-01-22 | Siemens Ag | Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie |
| US4263066A (en) * | 1980-06-09 | 1981-04-21 | Varian Associates, Inc. | Process for concurrent formation of base diffusion and p+ profile from single source predeposition |
| US4317276A (en) * | 1980-06-12 | 1982-03-02 | Teletype Corporation | Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer |
| US4389768A (en) * | 1981-04-17 | 1983-06-28 | International Business Machines Corporation | Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors |
| JPS5825788U (ja) * | 1981-08-17 | 1983-02-18 | 三菱自動車工業株式会社 | トラツクの車体構造 |
| DE102006030261B4 (de) * | 2006-06-30 | 2011-01-20 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit reduzierter Bordiffusion und Transistor |
-
1968
- 1968-12-30 US US787769A patent/US3574010A/en not_active Expired - Lifetime
-
1969
- 1969-10-14 GB GB1266243D patent/GB1266243A/en not_active Expired
- 1969-11-12 NL NL6917012A patent/NL6917012A/xx unknown
- 1969-12-08 JP JP44097914A patent/JPS4811511B1/ja active Pending
- 1969-12-09 DE DE19691961634 patent/DE1961634B2/de not_active Withdrawn
- 1969-12-11 FR FR6942870A patent/FR2027308B1/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1961634B2 (de) | 1972-01-13 |
| FR2027308B1 (https=) | 1973-10-19 |
| DE1961634A1 (de) | 1970-07-09 |
| JPS4811511B1 (https=) | 1973-04-13 |
| GB1266243A (https=) | 1972-03-08 |
| FR2027308A1 (https=) | 1970-09-25 |
| US3574010A (en) | 1971-04-06 |