GB1185857A - Improvements in or relating to Integrated Circuit Assemblies - Google Patents

Improvements in or relating to Integrated Circuit Assemblies

Info

Publication number
GB1185857A
GB1185857A GB37486/67A GB3748667A GB1185857A GB 1185857 A GB1185857 A GB 1185857A GB 37486/67 A GB37486/67 A GB 37486/67A GB 3748667 A GB3748667 A GB 3748667A GB 1185857 A GB1185857 A GB 1185857A
Authority
GB
United Kingdom
Prior art keywords
chip
assembly
printed circuit
encapsulated
plastics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB37486/67A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of GB1185857A publication Critical patent/GB1185857A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
GB37486/67A 1966-08-16 1967-08-15 Improvements in or relating to Integrated Circuit Assemblies Expired GB1185857A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57272066A 1966-08-16 1966-08-16
US61897367A 1967-02-27 1967-02-27

Publications (1)

Publication Number Publication Date
GB1185857A true GB1185857A (en) 1970-03-25

Family

ID=27075925

Family Applications (1)

Application Number Title Priority Date Filing Date
GB37486/67A Expired GB1185857A (en) 1966-08-16 1967-08-15 Improvements in or relating to Integrated Circuit Assemblies

Country Status (3)

Country Link
JP (1) JPS552735B1 (enrdf_load_stackoverflow)
DE (1) DE1614575A1 (enrdf_load_stackoverflow)
GB (1) GB1185857A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4329779A (en) 1979-02-26 1982-05-18 National Research Development Corporation Methods of applying circuit elements to a substrate
FR2498814A1 (fr) * 1981-01-26 1982-07-30 Burroughs Corp Boitier pour circuit integre, moyen pour le montage et procede de fabrication
US4355199A (en) 1975-10-10 1982-10-19 Luc Penelope Jane Vesey Conductive connections
GB2124433A (en) * 1982-07-07 1984-02-15 Int Standard Electric Corp Electronic component assembly
GB2188485A (en) * 1986-03-25 1987-09-30 Western Digital Corp Integrated circuit chip mounting and packaging assembly
EP0299775A3 (en) * 1987-07-16 1990-01-17 Digital Equipment Corporation Tab bonded semiconductor chip package
GB2247104A (en) * 1990-08-15 1992-02-19 Emi Plc Thorn Connections for semiconductor chips
WO2007052199A1 (en) * 2005-11-01 2007-05-10 Nxp B.V. Methods of packaging a semiconductor die and package formed by the methods
CN111446227A (zh) * 2020-05-19 2020-07-24 华进半导体封装先导技术研发中心有限公司 一种封装结构及封装方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2151765C2 (de) * 1970-11-05 1983-06-16 Honeywell Information Systems Italia S.p.A., Caluso, Torino Verfahren zum Kontaktieren von integrierten Schaltungen mit Beam-Lead-Anschlüssen
JPS58145297U (ja) * 1982-03-26 1983-09-30 ヤンマーディーゼル株式会社 小形船内機用船尾軸受装置
JPS58145295U (ja) * 1982-03-26 1983-09-30 ヤンマーディーゼル株式会社 小形船内機用プロペラ軸の中間軸
JPS58145298U (ja) * 1982-03-26 1983-09-30 ヤンマーディーゼル株式会社 小形船内機用船尾軸受装置
JPH0465693U (enrdf_load_stackoverflow) * 1990-10-15 1992-06-08

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4355199A (en) 1975-10-10 1982-10-19 Luc Penelope Jane Vesey Conductive connections
US4329779A (en) 1979-02-26 1982-05-18 National Research Development Corporation Methods of applying circuit elements to a substrate
FR2498814A1 (fr) * 1981-01-26 1982-07-30 Burroughs Corp Boitier pour circuit integre, moyen pour le montage et procede de fabrication
US4641176A (en) * 1981-01-26 1987-02-03 Burroughs Corporation Semiconductor package with contact springs
GB2124433A (en) * 1982-07-07 1984-02-15 Int Standard Electric Corp Electronic component assembly
US4843188A (en) * 1986-03-25 1989-06-27 Western Digital Corporation Integrated circuit chip mounting and packaging assembly
GB2188485A (en) * 1986-03-25 1987-09-30 Western Digital Corp Integrated circuit chip mounting and packaging assembly
GB2188485B (en) * 1986-03-25 1990-04-04 Western Digital Corp Electronic component mounting and pakaging assembly
EP0299775A3 (en) * 1987-07-16 1990-01-17 Digital Equipment Corporation Tab bonded semiconductor chip package
GB2247104A (en) * 1990-08-15 1992-02-19 Emi Plc Thorn Connections for semiconductor chips
WO2007052199A1 (en) * 2005-11-01 2007-05-10 Nxp B.V. Methods of packaging a semiconductor die and package formed by the methods
CN101356633B (zh) * 2005-11-01 2011-03-23 Nxp股份有限公司 半导体裸片的封装方法以及通过该方法形成的裸片封装
US8183682B2 (en) 2005-11-01 2012-05-22 Nxp B.V. Methods of packaging a semiconductor die and package formed by the methods
CN111446227A (zh) * 2020-05-19 2020-07-24 华进半导体封装先导技术研发中心有限公司 一种封装结构及封装方法

Also Published As

Publication number Publication date
JPS552735B1 (enrdf_load_stackoverflow) 1980-01-22
DE1614575A1 (de) 1970-05-27

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Legal Events

Date Code Title Description
PS Patent sealed
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee