GB2247104A - Connections for semiconductor chips - Google Patents
Connections for semiconductor chips Download PDFInfo
- Publication number
- GB2247104A GB2247104A GB9017944A GB9017944A GB2247104A GB 2247104 A GB2247104 A GB 2247104A GB 9017944 A GB9017944 A GB 9017944A GB 9017944 A GB9017944 A GB 9017944A GB 2247104 A GB2247104 A GB 2247104A
- Authority
- GB
- United Kingdom
- Prior art keywords
- electrical
- electrically conductive
- covering member
- substrate
- compliant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
An electrical apparatus includes a substrate (1) and electrical components (3) flip-chip bonded to the substrate. Onto the flip-chip bonded electrical components (3) is deposited compliant electrically conductive material (9). A covering member (5) is applied over the components and is provided with conductive tracking 7 for supplying signals to the components. <IMAGE>
Description
ELECTRICAL CONNECTING APPARATUS
The present invention relates to flip chip bonded apparatus and in particular to an apparatus for applying voltage-biasing to a flip chip bonded element of such an apparatus.
The flip chip process is well known in its application for applying elements, such as semiconductor elements, to a substrate. The process forms a bond which is essentially straight and orthogonal to the faces of the elements being bonded. The process may further use the phenomenon of surface tension in order to bring the elements being bonded into highly accurate alignment. One example of the flip chip bonding method is disclosed in Japanese Patent Application No. J63 062266. In this application is described a method whereby the flip chip process is used to form a dustproof bond.
However, this type of process suffers from several drawbacks, one of which is manifest when it is required to form a single further connection to the faces of several flip chip bonded elements remote from the bond surface, such as, for example, when it is required to provide a common voltage bias to the bonded elements. For a common contact or connection to be readily provided, the faces remote from the bond surface should all be at the same height with respect to each other. Otherwise, it is difficult to ensure that all the elements will make contact with the common connection. This problem is relatively easy to overcome with elements mounted using a wire bonding technique, which is well known to those skilled in the art, yet poses difficulties with regard to flip chip bonding.
It is a first object of the present invention to provide an apparatus for providing single electrical connections to predetermined elements of a flip chip bonded structure.
It is a further object to provide a method whereby the apparatus may be produced.
Thus the invention provides apparatus for forming an electrical connection, the apparatus comprising; a substrate; at least one electrical component flip chip bonded to the substrate; at least one element of compliant electrically conductive material; and an electrically conductive covering member, the at least one element arranged to be situated intermediate and in electrical contact with the at least one component and with the covering member, and the at least one component being situated intermediate and in contact with the substrate and the at least one element.
Preferably the covering member comprises an electrical insulator having on a major surface thereof an electrically conductive track for contact by the at least one element of compliant electrically conductive material.
Preferably the track and or the covering member are adapted to apply a bias voltage to the at least one component via the at least one compliant electrically conductive material.
Preferably the covering member is in the form of a lid.
Preferably the electrical components comprise semiconductor integrated circuits.
According to a second aspect of the present invention there is provided a method of producing apparatus for forming an electrical connection, the method comprising applying compliant electrically conductive material to at least one electrical component flip chip bonded to a substrate, and to this electrically compliant material applying a covering member.
The invention will now be described, by way of example only, with reference to the following drawings, of which:
Figure 1 shows a schematic representation of a flip chip bonded device and;
Figure 2 shows a schematic representation of the same device incorporating the present invention.
Referring to Figure 1, a substrate 1 has electrical components 3, such as a semiconductor integrated circuit flip chip bonded to its uppermost surface.
By utilising a flip chip bond 4, the benefits of which are well known to those skilled in the art, the lower surfaces of the components 3 are in certain circumstances all equi-spaced from the uppermost surface of the substrate 1, i.e. the lower surfaces are all coplanar, as shown by line I.
This results because a flip chip bond is achieved by applying a known amount of bondable material to the substrate 1 and thus the separation of electrical components 3 and substrate 1 may be accurately controlled.
However, if now it is required to form an electrical connection to any or all of the components 3 such as applying a cover member such as lid or the like, problems may arise as their uppermost surfaces are not coplanar, because the components are not all of equal dimensions as shown by line II, which is almost universally the case in practice. By now referring to Figure 2 it will be seen that cover member 5 such as a lid may be placed over, and in electrical contact with all the components 3, by applying elements 7, such as globules or spots, of compliant electrically conductive material to the uppermost surfaces of components 3.
By applying an electrical tracking 9 to the cover member 5 it is possible for all or any of the components 3 to have applied to them, via the tracking 9 and elements 7, electrical signals such as one or more bias voltages or power signals when the cover member 5 is placed in contact with the elements 7.
It will be appreciated that it is not imperative to apply tracking 9 to the cover member 5. If the cover member 5 is constructed so as to be inherently electrically conductive, the need for tracking 9 may be negated.
It will further be appreciated that the use of a conducting block 10 may allow a direct connection between a terminal on the substrate 1 and a corresponding terminal on the lid 5. This may be utilised to allow, for example, bias voltages to be connected within the package or to allow a low electrical resistance of tracking on a lid to be used for power distribution around a module.
It will thus be appreciated that the present invention provides apparatus and a method whereby flip chip bonded components may have electrical signals applied to them via a cover member, such as a lid and thus negates the need for separate electrical connections to each of the components.
Claims (7)
1. Apparatus for forming an electrical connection, the apparatus comprising; a substrate; at least one electrical component flip chip bonded to the substrate; at least one element of compliant electrically conductive material; and an electrically conductive covering member, the at least one element arranged to be situated intermediate and in electrical contact with the at least one component and with the covering member, and the at least one component being situated intermediate and in contact with the substrate and the at least one element.
2. Apparatus according to claim 1 wherein the covering member comprises an electrical insulator having, on a major surface thereof, an electrically conductive track for contact by the at least one element of compliant electrically conductive material.
3. Apparatus according to claim 2 wherein the track and/or the covering member are arranged for applying a bias voltage to the at least one component via the at least one element of compliant electrically conductive material.
4. Apparatus according to either claim 2 or claim 3 wherein the covering member is in the form of a lid.
5. Apparatus according to any preceding claim wherein the electrical components comprise semiconductor integrated circuits.
6. Apparatus as substantially hereinbefore described with reference to the accompanying drawings.
7. A method of producing apparatus for forming an electrical connections, the method comprising applying compliant electrically conductive material to at least one electrical component flip chip bonded to a substrate, and to this electrically compliant material applying a covering member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9017944A GB2247104A (en) | 1990-08-15 | 1990-08-15 | Connections for semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9017944A GB2247104A (en) | 1990-08-15 | 1990-08-15 | Connections for semiconductor chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9017944D0 GB9017944D0 (en) | 1990-09-26 |
| GB2247104A true GB2247104A (en) | 1992-02-19 |
Family
ID=10680726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9017944A Withdrawn GB2247104A (en) | 1990-08-15 | 1990-08-15 | Connections for semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2247104A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1185857A (en) * | 1966-08-16 | 1970-03-25 | Signetics Corp | Improvements in or relating to Integrated Circuit Assemblies |
| GB2013027A (en) * | 1978-01-19 | 1979-08-01 | Int Computers Ltd | Integrated circuit packages |
-
1990
- 1990-08-15 GB GB9017944A patent/GB2247104A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1185857A (en) * | 1966-08-16 | 1970-03-25 | Signetics Corp | Improvements in or relating to Integrated Circuit Assemblies |
| GB2013027A (en) * | 1978-01-19 | 1979-08-01 | Int Computers Ltd | Integrated circuit packages |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9017944D0 (en) | 1990-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |