DE1614575A1 - Aufbau einer integrierten Schaltung und Verfahren zum Herstellen dieses Aufbaues - Google Patents

Aufbau einer integrierten Schaltung und Verfahren zum Herstellen dieses Aufbaues

Info

Publication number
DE1614575A1
DE1614575A1 DE19671614575 DE1614575A DE1614575A1 DE 1614575 A1 DE1614575 A1 DE 1614575A1 DE 19671614575 DE19671614575 DE 19671614575 DE 1614575 A DE1614575 A DE 1614575A DE 1614575 A1 DE1614575 A1 DE 1614575A1
Authority
DE
Germany
Prior art keywords
lines
component
integrated circuit
sections
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19671614575
Other languages
German (de)
English (en)
Inventor
Byrne Robert Craig
Youmans Albert Peeples
King Alan Vaughn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of DE1614575A1 publication Critical patent/DE1614575A1/de
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49524Additional leads the additional leads being a tape carrier or flat leads
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49572Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/01049Indium [In]
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    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
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    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/181Encapsulation
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE19671614575 1966-08-16 1967-08-04 Aufbau einer integrierten Schaltung und Verfahren zum Herstellen dieses Aufbaues Pending DE1614575A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57272066A 1966-08-16 1966-08-16
US61897367A 1967-02-27 1967-02-27

Publications (1)

Publication Number Publication Date
DE1614575A1 true DE1614575A1 (de) 1970-05-27

Family

ID=27075925

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19671614575 Pending DE1614575A1 (de) 1966-08-16 1967-08-04 Aufbau einer integrierten Schaltung und Verfahren zum Herstellen dieses Aufbaues

Country Status (3)

Country Link
JP (1) JPS552735B1 (enrdf_load_stackoverflow)
DE (1) DE1614575A1 (enrdf_load_stackoverflow)
GB (1) GB1185857A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2152081A1 (de) * 1970-11-05 1972-05-18 Honeywell Inf Systems Verfahren zum Anbringen von Chips mit integrierter Schaltung auf Zwischenverbindungstraegern

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1574699A (en) 1975-10-10 1980-09-10 Luc Technologies Ltd Conductive connections
DE3064555D1 (en) 1979-02-26 1983-09-22 Nat Res Dev Method of incorporating a distributed microwave circuit element in a microwave integrated circuit
FR2498814B1 (fr) * 1981-01-26 1985-12-20 Burroughs Corp Boitier pour circuit integre, moyen pour le montage et procede de fabrication
JPS58145295U (ja) * 1982-03-26 1983-09-30 ヤンマーディーゼル株式会社 小形船内機用プロペラ軸の中間軸
JPS58145297U (ja) * 1982-03-26 1983-09-30 ヤンマーディーゼル株式会社 小形船内機用船尾軸受装置
JPS58145298U (ja) * 1982-03-26 1983-09-30 ヤンマーディーゼル株式会社 小形船内機用船尾軸受装置
GB2124433B (en) * 1982-07-07 1986-05-21 Int Standard Electric Corp Electronic component assembly
US4843188A (en) * 1986-03-25 1989-06-27 Western Digital Corporation Integrated circuit chip mounting and packaging assembly
US4843695A (en) * 1987-07-16 1989-07-04 Digital Equipment Corporation Method of assembling tab bonded semiconductor chip package
GB2247104A (en) * 1990-08-15 1992-02-19 Emi Plc Thorn Connections for semiconductor chips
JPH0465693U (enrdf_load_stackoverflow) * 1990-10-15 1992-06-08
JP2009514242A (ja) * 2005-11-01 2009-04-02 エヌエックスピー ビー ヴィ 半導体ダイの実装方法および半導体パッケージ
CN111446227A (zh) * 2020-05-19 2020-07-24 华进半导体封装先导技术研发中心有限公司 一种封装结构及封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2152081A1 (de) * 1970-11-05 1972-05-18 Honeywell Inf Systems Verfahren zum Anbringen von Chips mit integrierter Schaltung auf Zwischenverbindungstraegern

Also Published As

Publication number Publication date
JPS552735B1 (enrdf_load_stackoverflow) 1980-01-22
GB1185857A (en) 1970-03-25

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