FR2846790B1 - Dispositif pour la determination de la version de masque utilisee pour chaque couche metal d'un circuit integre - Google Patents

Dispositif pour la determination de la version de masque utilisee pour chaque couche metal d'un circuit integre

Info

Publication number
FR2846790B1
FR2846790B1 FR0213651A FR0213651A FR2846790B1 FR 2846790 B1 FR2846790 B1 FR 2846790B1 FR 0213651 A FR0213651 A FR 0213651A FR 0213651 A FR0213651 A FR 0213651A FR 2846790 B1 FR2846790 B1 FR 2846790B1
Authority
FR
France
Prior art keywords
metal layer
mask
metal3
integrated circuit
source voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0213651A
Other languages
English (en)
Other versions
FR2846790A1 (fr
Inventor
Arnaud Deleule
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0213651A priority Critical patent/FR2846790B1/fr
Priority to US10/699,613 priority patent/US7120886B2/en
Publication of FR2846790A1 publication Critical patent/FR2846790A1/fr
Application granted granted Critical
Publication of FR2846790B1 publication Critical patent/FR2846790B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR0213651A 2002-10-31 2002-10-31 Dispositif pour la determination de la version de masque utilisee pour chaque couche metal d'un circuit integre Expired - Fee Related FR2846790B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0213651A FR2846790B1 (fr) 2002-10-31 2002-10-31 Dispositif pour la determination de la version de masque utilisee pour chaque couche metal d'un circuit integre
US10/699,613 US7120886B2 (en) 2002-10-31 2003-10-30 Device for determining the mask version utilized for each metal layer of an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0213651A FR2846790B1 (fr) 2002-10-31 2002-10-31 Dispositif pour la determination de la version de masque utilisee pour chaque couche metal d'un circuit integre

Publications (2)

Publication Number Publication Date
FR2846790A1 FR2846790A1 (fr) 2004-05-07
FR2846790B1 true FR2846790B1 (fr) 2005-10-28

Family

ID=32104350

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0213651A Expired - Fee Related FR2846790B1 (fr) 2002-10-31 2002-10-31 Dispositif pour la determination de la version de masque utilisee pour chaque couche metal d'un circuit integre

Country Status (2)

Country Link
US (1) US7120886B2 (fr)
FR (1) FR2846790B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI315479B (en) * 2006-09-18 2009-10-01 Novatek Microelectronics Corp Apparatus and method of expressing circuit version identification
JP2008078363A (ja) * 2006-09-21 2008-04-03 Matsushita Electric Ind Co Ltd 可変経路配線セル、半導体集積回路およびその設計方法ならびに可変経路配線セルの形成方法
TW201140786A (en) * 2010-05-14 2011-11-16 Realtek Semiconductor Corp Layout structure and version control circuit for integrated circuit
US9913363B2 (en) * 2011-09-29 2018-03-06 Rambus Inc. Structure for delivering power

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459355A (en) * 1992-12-09 1995-10-17 Intel Corporation Multiple layer programmable layout for version identification
US5399505A (en) * 1993-07-23 1995-03-21 Motorola, Inc. Method and apparatus for performing wafer level testing of integrated circuit dice
US5594273A (en) * 1993-07-23 1997-01-14 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5644144A (en) * 1994-09-23 1997-07-01 Advanced Micro Devices, Inc. Device and method for programming a logic level within an integrated circuit using multiple mask layers
US5787012A (en) * 1995-11-17 1998-07-28 Sun Microsystems, Inc. Integrated circuit with identification signal writing circuitry distributed on multiple metal layers
US5895962A (en) * 1996-06-13 1999-04-20 Micron Technology, Inc. Structure and a method for storing information in a semiconductor device
US6194738B1 (en) * 1996-06-13 2001-02-27 Micron Technology, Inc. Method and apparatus for storage of test results within an integrated circuit
JP3770724B2 (ja) * 1998-02-09 2006-04-26 株式会社リコー 半導体集積回路装置のマスクパターン検証装置
US6268228B1 (en) * 1999-01-27 2001-07-31 International Business Machines Corporation Electrical mask identification of memory modules
US6530074B1 (en) * 1999-11-23 2003-03-04 Agere Systems Inc. Apparatus for verification of IC mask sets
DE19958906A1 (de) * 1999-12-07 2001-07-05 Infineon Technologies Ag Herstellung von integrierten Schaltungen
US6629239B1 (en) * 2000-04-07 2003-09-30 Sun Microsystems, Inc. System and method for unpacking and merging bits of a data world in accordance with bits of a mask word
TW466658B (en) * 2000-06-28 2001-12-01 Mosel Vitelic Inc Method to form the identification device of mask ROM
US7120884B2 (en) * 2000-12-29 2006-10-10 Cypress Semiconductor Corporation Mask revision ID code circuit
JP2003023091A (ja) * 2001-07-10 2003-01-24 Mitsubishi Electric Corp バージョン管理回路およびその製造方法
US6559544B1 (en) * 2002-03-28 2003-05-06 Alan Roth Programmable interconnect for semiconductor devices
US20040064801A1 (en) * 2002-09-30 2004-04-01 Texas Instruments Incorporated Design techniques enabling storing of bit values which can change when the design changes

Also Published As

Publication number Publication date
FR2846790A1 (fr) 2004-05-07
US20040143805A1 (en) 2004-07-22
US7120886B2 (en) 2006-10-10

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Effective date: 20070629