FR2662302A1 - Method for manufacturing a capacitor of a semiconductor memory device - Google Patents

Method for manufacturing a capacitor of a semiconductor memory device Download PDF

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Publication number
FR2662302A1
FR2662302A1 FR9011611A FR9011611A FR2662302A1 FR 2662302 A1 FR2662302 A1 FR 2662302A1 FR 9011611 A FR9011611 A FR 9011611A FR 9011611 A FR9011611 A FR 9011611A FR 2662302 A1 FR2662302 A1 FR 2662302A1
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France
Prior art keywords
conductive layer
layer
manufacturing
etching
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9011611A
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French (fr)
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FR2662302B1 (en
Inventor
Kyung-Hun Kim
Seong-Tae Kim
Hyeong-Kyu Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR9007268A priority Critical patent/KR930000718B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2662302A1 publication Critical patent/FR2662302A1/en
Application granted granted Critical
Publication of FR2662302B1 publication Critical patent/FR2662302B1/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor
    • H01L27/10817Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor the storage electrode having multiple wings

Abstract

<P> It comprises the steps of: <BR/> forming a transistor on a substrate (1) and depositing an insulating layer between layers (10); forming a predetermined pattern of a first conductive layer (30) by vertically etching it using a mask; horizontally overwrite the configuration; depositing a first insulating film (32) and a second conductive layer (33); vertically etching the second conductive layer, the first insulating film and the insulating layer; further depositing the second conductive layer; forming a determined pattern of the second conductive layer by etching vertically using a mask; horizontally overgrading the configuration of the second conductive layer; depositing a second insulating film (36) and a third conductive layer (37); vertically etching the third conductive layer (37) and the second insulating film (36); additionally deposit the third conductive layer (37). </ P>

Description

* 1

  The present invention relates to a method of

  manufacture of a semiconductor device, and more

  particularly to a method of manufacturing a capacitor of an integrated semiconductor memory device

on a very large scale.

  Recently, in a semiconductor memory device

  such as a DRAM, the 4M DRAM was manufactured in series and the 16M DRAM was actively studied In other words, the submicron stage represented by the 4M DRAM is open and the structure of a three-dimensional device

  is considered in addition to finesse by the proportional reduction

classic.

  In a DRAM, according to the memory cell structure, the typical three-dimensional structures such as

  the trench type and the stack type have been studied.

  The trench type is manufactured in such a way that a capacitor is formed within the groove on the semiconductor substrate, and the stack type is constructed such that a capacitor is formed by three-dimensional superimposition of the capacitors. conductive layers on the surface of the semiconductor substrate Compared to the stacking type, the trench type has a flatter surface, resulting in an advantage in lithography But it is disadvantageous in that the operating voltage is modified by a leakage current and a breakdown between the trench and the adjacent trench, and the

  electron-hole pairs generated by "trans-

  placed inside the substrate The stacking type is

  by superimposing elementary layers on the substrate, so that the sequence of the manufacturing steps is simpler than that of the trench type, and does not have these disadvantages as in said trench type As a result, the stack type is more advantageous in comparison

trench type.

  To obtain the effective capacity required in

  the limited cell area, the stack type should be used

  In the conventional stack type, a thin insulating film covers the top surface and the side surface of the memory electrode layer, and then the electrode plate layer is formed above. , for

  maintain equal or more effective capacity in the over-

  limited cell face based on reduced cell size to achieve very large scale integration,

  the height of the superimposed layers must be higher.

  As a result, this is disadvantageous because the topography

  global device is corrupted.

  One of the aims of the present invention is to

  a process for the manufacture of a semiconductor device

  providing greater effective capacity in the field of

  what the electrode plate layer even surrounds the sur-

  underside of the memory electrode layer of the con-

  denser, and the problem of the classical technique can

to be determined.

  Another object of the present invention is to

  a method of manufacturing the semiconductor device

  in which the surrounding electrode plate layer

  even the lower surface of the electrode electrode layer

  simply moire without additional mask, can be formed.

  Another object of the present invention is to

  a method of manufacturing a semiconductor device

  to make a DRAM of 16 M bits or more.

  To achieve these goals, a process of

  of the semiconductor device having a plurality of

  memory cells, each consisting of a transistor and a stack capacitor, comprises the steps of:

  forming said transistor on a semicon-

  conductor by the conventional method of manufacturing a transistor and then depositing an insulating layer between layers on the entire surface; depositing a first conductive layer on the entire surface of said insulating layer between

  layers and then form an engraving pattern using

  mask and simultaneously vertically etch the first conductive layer to form a predetermined configuration thereof; horizontally supergrading said resulting configuration of the first conductive layer by wet etching, using the etch pattern used to vertically etch said first conductive layer; depositing a first thin insulating film over the entire surface of the structure in which said first horizontally supergraded conductive layer is formed, and then depositing a second conductive layer to obtain a thickness sufficient to protect said first insulating film;

  vertically etch said second layer

  ductive, said first thin insulating film and the

  so-called insulating layer between layers using the mask

  used during the etching of said first layer

  conductor so as to form a first contact hole for contacting said transistor; deposit the same material as said

  second conductive layer according to a predefined thickness

  born over the entire surface of the structure in which said contact hole is formed;

  to form an engraving pattern using a mas-

  that and etch vertically said second conductive layer

  to form a specific configuration thereof; horizontally supergrading said second conductive layer by wet etching using the etching pattern used to vertically etch said second conductive layer; depositing a second thin insulating film over the entire surface of the structure after removing the etching pattern from said second conductive layer, and then

  deposit a third conductive layer so as to ob-

  holding a thickness to protect said second insulating film; exposing a partial surface of the first conductive layer by vertically etching the third conductive layer and the second thin insulating film by applying said mask used in etching said second conductive layer; and depositing the same materials as the third conductive layer in a predetermined thickness over the entire surface of the structure in which the surface

  partial of said first conductive layer is exposed.

  By adapting the aforementioned manufacturing method, with the same masking process as the conventional method, even the lower surface of the memory electrode layer can be used as an effective surface of

  capacitor without using an additional mask.

  Other features and advantages of the

  The following description will emerge from the description which follows

keeping the attached drawings.

  Figures 1A to 1H illustrate the success of manufacturing steps of the conventional 4M DRAM stack type; and Figures 2A to 2M illustrate the succession

  advanced manufacturing steps from DRAM to integrating

  on a very large scale according to the present invention. With reference to FIG. 1A, on a semiconductor substrate 1 slightly doped with P-type impurities,

  such as boron, a P 2 type well is

  Ion impurity ionization An active region 3

  is defined by photolithography After an implanta-

  ionic contamination of p-type impurities in the isolating layer.

  4 was again performed, the field oxide layer 5 was heated by thermal oxidation by the LOCOS process. Thanks to this thermal oxidation, the well of the type

  P 2 is more deeply dilated in the semicon-

  1, and a P-channel ion-blocking layer 6 is formed directly beneath the field oxide layer 5 In the active region 3, a polycrystalline silicon layer doped with N-type impurities, such as phosphor (P) forming the thin gate oxide film 7, is deposited on the entire surface The polycrystalline silicon layer is etched by conventional photolithography so as to form the conductive layer 8 of the word transmission line extending over the along the direction

  This conductive layer of transmission line

  Word translation 8 serves as a gate electrode layer in the active region 3 and on the field oxide, conducting layer layer for connecting the gate electrode layers. An ion implantation of N-type impurities such as P, is performed on the entire surface of the

  structure having the conductive layer of transmission line

  8, so that the N + 9a and 9b ion layers self-aligned on the gate electrode layer are formed in the active region 3 Thus, the N-ion layer 9a between the field oxide 5 and the gate electrode layer 8 serves as the source electrode layer and the N + 9b ion layer between the gate electrode layers 8 serves as the drain electrode layer as described herein. above, the interlayer insulating layer 10 such as HTO is deposited on the entire surface of the structure in which an NMOS transistor is formed on the surface

of the P type well 2.

  Referring to Fig. 1B, for coating the entire surface of the structure in which the interlayer insulating layer 10 is formed with photoresist coating, and forming the contact hole 12 on the surface of the N 9 ion layer provided as the source electrode layer,

  the insulating layer between layers 10 is vertically

  by conventional photolithography.

  Referring to Figure l C, after formation of

  said contact hole 12, the photosensitive varnish 1 is eli-

  and then the polycrystalline silicon layer 13 is deposited to a thickness of 1500 to 2000 A according to

the LPVCD process.

  With reference to FIG. 1D, to cover the entire surface of the polycrystalline silicon layer 13 with photoresist 14 and form the memory electrode layer, the polycrystalline silicon layer 13 is vertically etched by conventional photolithography. polycrystalline silicon layer 13 between a pair of word transmission line conductive layers 8, consisting of the gate electrode layer disposed on the active region 3 and the conductive layer disposed on the field oxide layer 5 remains as

  as memory electrode layer.

  With reference to Figure 1E, after training

  of the memory electrode layer, an insulating film

  the thin film is deposited in a thickness of 60 to 80 Å.

  the entire surface of the structure This iso-

  lante 15 consists of the laminated film of the thermal oxide film and the nitride film,

  for example, ONO film (silica, silicon nitride

  This insulating film plays the role of

  dielectric film of the capacitor.

  With reference to Figure 1F, the silicone layer

  N + doped polycrystallineium 16 is deposited in a thick

  from 1500 to 2000 A on the entire surface of the film

  LPVCD insulation. This layer of silicone is

  polycrystalline copper 16 serves as a

capacitor trode.

  With reference to Figure 1G, to isolate the

  the electrode plate around the contact hole of the bit transmission line, the photosensitive varnish 17 is applied to the structure and the polycrystalline silicon layer 16 is then etched vertically by

classic photolithography.

  With reference to FIG. 1H, according to the conventional manufacturing treatment sequence of a 4M DRAM, the glass layer 18, such as a borosilicate and phosphorus silicate glass film BPS G is deposited to flatten the surface and the contact hole of the bit transmission line 19 is formed on the surface of the N + 9b ion layer by conventional photolithography And then, after formation of the bit transmission line

  20 by conventional metallization, a film of passiva-

  tion 21 is applied and then the chip is completed according to

  the classic manufacturing process.

  The sequence of manufacturing steps mentioned above

  was explained about the fundamental processes alone.

  to obtain the illustrated structure, but some

  processes were omitted for the sake of simplicity.

  The succession of manufacturing steps according to the present invention will now be explained with reference

  2 A to 2 L In the succession of manufacturing steps

  cation of the present invention, using the same number

  masks than that used in the manufacturing process

  of a cell capacitor of a 4M DRAM, the electrode plate layer is arranged to surround even the lower surface of the memory electrode layer by interposing the insulating film between them

  to increase the effective capacity of the memory cell.

  Thus, a 16M DRAM is easily obtained by applying the proportionally reduced dimension of a 4M DRAM. Referring to FIG. 2A, after carrying out the step described in FIG. 1A, a polycrystalline silicon layer is described. N-doped, serving as

  first conductive layer, is deposited on all the surface

  face of the resulting structure according to a thickness of o

  1500 to 2000 A by the LPCVD process.

  Referring to Figure 2 B, to form the layer

  polycrystalline silicon 30 according to the prior configuration

  determined, a photoresist 31 is applied to the polycrystalline silicon layer 30, the contact hole mask is applied, and the photoresist 31

  as well as the polycrystalline silicon layer 30 are

  vertically by conventional photolithography.

  With reference to FIG. 2C, following vertical etching, the horizontal etching is performed in the polycrystalline silicon layer 30, so that the exposed side of the resulting exposed polysilicon layer 30 is etched horizontally to a predetermined depth while maintaining the pattern of

  etching of the photoresist 31 in the initial state.

  After etching, the remaining pattern of the silicone layer

  Polycrystallineium 30 is provided as a

  of the electrode plate layer to surround the lower surface of the memory electrode layer of the

cell capacitor.

  With reference to FIG. 2D, after removal of the varnish 31, the first thin insulating film 32 is deposited over the entire surface of the resulting structure, and then an N + 33 doped polycrystalline silicon layer 33 serving as a second conductive layer is successively deposited in in this case, the first insulating film 32 has a thickness of about 60 to 80 A, and the polycrystalline silicon layer 33 has a thickness such that 300 to 500 A to protect the first insulating film

  32 during the next burning process.

  With reference to Figure 2E, after deposit of the

  polycrystalline silicon layer 33, the photosensitive varnish

  ble 34 is applied over the entire surface, and then the polycrystalline silicon layer 33, the insulating film

  32 and the insulating layer between layers 10 are successively

  engraved in the vertical direction using the mask

  of contact hole used in the photolitho-

  graph as shown in Figure 2 D, so that the contact hole 12 is formed to bring the layer

  of the capacitor electrode of the cell capacitor in

  This instant, the insulating film 32 is protected during the etching process by the polycrystalline silicon layer 33 with a thickness of 300 to 500 A. With reference to FIG. 2F, after the formation of the contact hole 12 on the electrode layer 9a, the varnish 34 is eliminated, and then the silicon layer

  polycrystalline 33 is deposited in a predetermined thickness

  As shown in FIG. 2G, the varnish 35 is applied to the polycrystalline silicon layer 33, and then the polycrystalline silicon layer 33 is etched vertically using the electrode mask. of memory

by conventional photolithography.

  With reference to Figure 2H, following the

  vertical engraving, the lateral surface of the

  polycrystalline silicon layer 33 exposed to the outside

  laughing while performing horizontal engraving by etching by

  wet track is horizontally etched to the depth

  determined. With reference to Figure 2 I, after the wet etching, the varnish 35 is removed and then on any

  the surface of the remaining structure, the second film

  The insulating thin member 36 is deposited at a thickness of from 0 to 80 A, and then an N + -copped polycrystalline silicon layer 37 serving as a third conductive layer is deposited at a thickness of 300 to 500 A, for example to protect the second layer. insulating film 36

during the engraving process.

  With reference to FIG. 2J, varnish 38 is

  * applied over the entire surface of the silicon layer

  lycrystalline above 37 and then, with the aid of the aforementioned memory electrode mask, a partial surface of the

  polycrystalline silicon 30 is exposed by green etching.

  of the polycrystalline silicon layer 37 and the second insulating film 36, by conventional photolithography. With reference to Figure 2 K, after the above-mentioned blanking step, the varnish 38 is removed and then a polycrystalline silicon layer 37 having a

  thickness from 1500 to 2000 A is N-doped over the entire

  face of the structure according to the LPCVD method for coming into electrical contact with the polycrystalline silicon layer

  having its surface partially exposed.

  With reference to FIG. 2L, after the deposition of the aforementioned polycrystalline silicon layer 37, the varnish 39 is applied over the entire surface of the structure, and then, by applying the mask of the electrode plate layer, the layers of polycrystalline silicon 37 and 30 / around the location where the line contact

  transmission of bits must be arranged, are engraved ver-

  in conventional photolithography.

  With reference to FIG. 2 M, after the aforementioned etching step, the bit transmission line 20 is formed by the same processes as represented on FIG.

  Figure 1H, so as to complete the manufacturing process.

  As described above, in the present invention

  to manufacture a cell capacitor of a DRAM, the method of manufacturing the stacking type 4M DRAM

  classic is applied, and the upper surface and the

  side face as well as the lower surface of the memory electrode layer is used as the effective surface Thus, by the present method of manufacturing a 4M DRAM, the capacity of the memory cell can be doubled in comparison with the conventional cell, so that a 16 M DRAM can be easily manufactured In addition, no additional mask is necessary due to the use of horizontal etching by the wet process

Claims (7)

R E V E N D I C A T IO N S
  1 Method of manufacturing a device with semicon-
  drivers placing a plurality of memory cells
  each of which consists of a transistor and a
  a denser of the stack type, said method being
  controlled by the steps of
  forming said transistor on a semicon-
  conductor (1) according to the conventional method of manufacturing a transistor and then depositing an insulating layer between layers (10) over the entire surface; deposit a first conductive layer (30)
  the entire surface of said insulating layer between
  and then forming an etching pattern using a mask and vertically etching the first conductive layer simultaneously to form a predetermined pattern thereof; horizontally supergrading said resulting configuration of the first conductive layer by etching
  wet, using said etching pattern used
  to vertically etch said first layer
  ductrice; depositing a first thin insulating film (32) over the entire surface of the structure in which
  said first conductive layer overgraded horizontally
  is formed, and then depositing a second conductive layer (33) to obtain a thickness sufficient to protect said first insulating film;
  vertically etch said second layer
  ductive, said first thin insulating film and the
  said inter-layer insulating layer using the mask used to etch said first conductive layer so as to form a first contact hole (12) for contacting said transistor;
  deposit the same material as said
  conductive layer conductive to a predetermined thickness over the entire surface of the structure in which is formed said contact hole; forming an etching pattern using a mask and vertically etching said second conductive layer to form a determined pattern thereof, horizontally enhancing said second conductive layer by wet etching, using said etch pattern used to vertically etch said second conductive layer; depositing a second thin insulating film (36) over the entire surface of the structure after removing the etching pattern from said second conductive layer, and then depositing a third conductive layer (37) to obtain a thickness sufficient to protect said second film insulation; exposing a partial surface of the first conductive layer by vertically etching the third conductive layer and the second thin insulating film
  by applying said mask used to engrave said se-
conductive layer; and
  deposit the same materials as the third
  second conductive layer according to a predetermined thickness
  over the entire surface of the structure in which an over-
  partial face of said first conductive layer is
exposure.
  2 Method of manufacturing a device with semicon-
  Conductors according to claim 1, characterized in that said first and second insulating films (32, 36) are formed by superimposing thermal oxide films.
and nitride films.
  3 Method of manufacturing a device with semicon-
  Conductors according to claim 2, characterized in that said first to third conductive layers (30, 33, 37) consist of polycrystalline silicon doped with impurities.
  4 Method of manufacturing a device with semicon-
  Conductors according to claim 3, characterized in that said first and second insulating films (32, 36) have a thickness of 60 to 80 A. A method of manufacturing a semiconductor device according to claim 4, characterized in that the thicknesses of the first (30) and third (37) layers
  are approximately 300 to 500 A which can
  said first and second insulating films.
  6 Method of manufacturing a device with semicon-
  Conductors according to claim 5, characterized in that the predetermined thicknesses of the first and third conductive layers (30, 37) are about 1500 to 2000 A.
  7 Method of manufacturing a device with semicon-
  ducters according to claim 1, characterized in that
  said transistor is a MOS transistor.
  8 Method of manufacturing a device with semicon-
  conductors according to claim 7, characterized in that said method further comprises the steps of depositing a molten glass layer (18) over the entire surface of said third conductive layer; vertically etching said molten glass layer, the third and first conductive layers (30,37) and the interlayer insulating film (10) so as to
  forming a second contact hole (19) to come into contact
  tact of said transistor; and forming a bit transmission line (20) of said memory cell on the structure having
  said second contact hole (19) by a process of
tallisation.
FR9011611A 1990-05-21 1990-09-20 Process for manufacturing a capacitor of a semiconductor memory device. Expired - Lifetime FR2662302B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR9007268A KR930000718B1 (en) 1990-05-21 1990-05-21 Method for fabricating semiconductor device

Publications (2)

Publication Number Publication Date
FR2662302A1 true FR2662302A1 (en) 1991-11-22
FR2662302B1 FR2662302B1 (en) 1992-08-14

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FR9011611A Expired - Lifetime FR2662302B1 (en) 1990-05-21 1990-09-20 Process for manufacturing a capacitor of a semiconductor memory device.

Country Status (6)

Country Link
JP (1) JPH0724285B2 (en)
KR (1) KR930000718B1 (en)
DE (1) DE4031414A1 (en)
FR (1) FR2662302B1 (en)
GB (1) GB2244375B (en)
IT (1) IT1243103B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930006732B1 (en) * 1991-05-08 1993-07-23 경상현 Semiconductor substrate having the structure assembly varied and method of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63293967A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Manufacture of charge storage capacitor for dram
US4899203A (en) * 1987-12-11 1990-02-06 Oki Electric Industry Co., Ltd. Semiconductor memory integrated circuit and process of fabricating the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120070A (en) * 1985-11-20 1987-06-01 Toshiba Corp Semiconductor memory
JPH0736437B2 (en) * 1985-11-29 1995-04-19 株式会社日立製作所 A method of manufacturing a semiconductor memory
DE3856528D1 (en) * 1987-06-17 2002-06-13 Fujitsu Ltd Dynamic random access memory device and method of making the same
KR910010167B1 (en) * 1988-06-07 1991-12-17 강진구 Stack capacitor dram cell and its manufacturing method
US5116776A (en) * 1989-11-30 1992-05-26 Sgs-Thomson Microelectronics, Inc. Method of making a stacked copacitor for dram cell
KR920010204B1 (en) * 1989-12-02 1992-11-21 김광호 Ulsi dram cell and method for manufacturing of the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63293967A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Manufacture of charge storage capacitor for dram
US4899203A (en) * 1987-12-11 1990-02-06 Oki Electric Industry Co., Ltd. Semiconductor memory integrated circuit and process of fabricating the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 13, no. 126 (E-734)[3474], 28 mars 1989; & JP-A-63 293 967 (HITACHI LTD) 30-11-1988 *

Also Published As

Publication number Publication date
GB2244375B (en) 1994-06-15
DE4031414A1 (en) 1991-11-28
IT9021550D0 (en) 1990-09-24
KR910020901A (en) 1991-12-20
GB2244375A (en) 1991-11-27
JPH0424961A (en) 1992-01-28
KR930000718B1 (en) 1993-01-30
FR2662302B1 (en) 1992-08-14
IT9021550A1 (en) 1990-12-24
IT1243103B (en) 1994-05-24
JPH0724285B2 (en) 1995-03-15
GB9020502D0 (en) 1990-10-31

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