GB2244375A

GB2244375A - A method for manufacturing dram cells

Info

Publication number: GB2244375A
Application number: GB9020502A
Authority: GB
Inventors: Kyung-Hun Kim; Seong-Tae Kim; Hyeong-Kyu Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-05-21
Filing date: 1990-09-20
Publication date: 1991-11-27
Anticipated expiration: 2010-09-20
Also published as: GB9020502D0; DE4031414A1; IT1243103B; FR2662302B1; FR2662302A1; GB2244375B; KR910020901A; IT9021550A0; IT9021550A1; KR930000718B1; JPH0724285B2; JPH0424961A

Abstract

The method comprises the steps of: forming a transistor on a substrate, depositing an insulating layer (10), patterning a first conductive layer (30) by vertically and horizontally etching it using a first mask, depositing a first insulating film (32), depositing a second conductive layer (33) to protect the first insulating film (32), vertically etching the second conductive layer (33), first insulating film (32) and insulating layer 10 using the first mask, forming a pattern of the second conductive layer (33) by vertically and horizontally etching it using a second mask, depositing a second insulating film (36), depositing a third conductive layer (37) to protect the second insulating film (36), vertically etching the third conductive layer (37) and second insulating film (36) using the second mask, and increasing the thickness of the third conductive layer (37). The method achieves a larger effective capacitance as the plate electrode layer 30, 37 also surrounds the lower surface of the storage electrode layer 33 of the stack capacitor. <IMAGE>

Description

1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE The present invention

relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor for an ultra large integrated semiconductor memory device.

In recent times, in semiconductor memory devices, such as DRAM (Dynamic Random Access Memory), 4M DRAM has been mass-produced and 16M DRAM has been actively studied. In other words, the submicron stage as 2. epresented by 4M DRAM, is i realised and the 3-dimensional device structure has been introduced, in addition to the resolution available by conventional proportional reduction.

In DRAM, according to the memory cell structure, the typical three dimensional structures such as, trench type and stack type, have been extensively studied. The trench type structure is manufactured in such a manner that a capacitor is formed inside a groove provided on the semiconductor substrate, and the stack type structure is constructed such that a capacitor is formed by laminating in three dimensions the conductive layers on the surface of the semiconductor substrate. Compared with the stack type, trench type structure has a flatter surface, which is advantageous for lithography. But a trench type structure is disadvantageous in that the operational voltage is changed by leakage current and punchthrough between the trench and neighbouring trenches, and by electron-hole pairs generated by a-particles transmitted inside the substrate. The stack type structure is formed by laminating 2 element layer s on the substrate, so that the fabrication process sequence is simpler than that of the trench type, and does not have such disadvantages as those of the trench type. As a result, the stack type is more profitable when compared with the trench type.

To attain the required effective capacitance in the limited cell area, the stack type has to utilize the capacitor area maximally. In the conventional stack type, a thin insulating film covers the upper surface and the side surface of the storage electrode layer and then the plate electrode layer is formed thereon. Therefore, to keep the effective capacitance at least as great in the limited cell area based on the decreased cell size to achieve VLSI, the height of the stacked layers should be greater. This has the disadvantageous result that the topography of the overall device is poorer.

It is an object of the present invention to provide a manufacturing method for a semiconductor device providing larger effective capacitance, in which the plate electrode layer surrounds even the lower surface of the storage electrode layer of the capacitor, and the problem of the conventional technique can be solved.

It is another object of the present invention to provide a 'manufacturing method for a semiconductor device in which the plate electrode layer surrounding even the lower surface of the storage electrode layer can be formed simply without any extra mask.

It is yet another object of the present invention to provide a manufacturing method for the semiconductor device 3 which enables a DRAM of 16M bit or more to be fabricated.

According to the present invention there is provided a method for manufacturing a semiconductor device having a plurality of memory cells, each of which consists of a transistor and a stack capacitor, comprising the steps of:

forming said transistor on a semiconductor substrate by the commercial manufacturing method of transistor and then depositing an interlayer insulating layer on the whole surface; depositing a first conductive layer on the whole surface of said interlayer insulating layer and then forming an etching pattern by using a mask and simultaneously vertically etching the first conductive layer to form a designed pattern thereof; horizontally over-etching said resultant pattern of the first conductive layer via a wet etching process, by using the etching pattern used for vertically etching said firs', conductive layer; depositing a thin first insulating film on the whole surface of the structure in which said horizontally over-etched first conductive layer is formed, and then depositing a second conductive layer of sufficient thickness to protect said first insulating film; vertically etching said second conductive layer, said thin first insulating film and said interlayer insulating layer by using the mask used in etching said first conductive layer so as to form a first contact hole to contact said transistor; additionally depositing the same material as said second conductive layer in a predetermined thickness on the 4 whole surface of the structure in which said contact hole is formed; forming an etching pattern by using a mask and vertically etching said second conductive layer to f orm a designed pattern thereof; horizontally over-etching said second conductive layer via the wet etching process, by using the etching pattern used for vertically etching said second conductive layer; depositing a thin second insulating film on the whole surf ace of the structure after removing the etching pattern of said second conductive layer, and then depositing a third conductive layer so as to have the thickness to protect said second insulating film; exposing a part of the surface of the first conductive layer by vertically etching the third conductive layer and the thin second insulating film with applying said mask used in etching said second conductive layer; and additionally depositing the same materials as the third conductive layer in a predetermined thickness on the whole surface of the structure in which partial surface of said first conductive layer is exposed.

By adapting the above manufacturing method, with the same mask process as the conventional method, even the lower surface of the storage electrode layer can be used as the effective area of capacitor without using any extra mask.

Embodiments of the present invention -will now be described, by way of example, with reference to the accompanying drawings, in which:

FIG.lA to 1H illustrate the fabrication process sequence of the conventional 4M DRAM of stack type; and FIG.2A to 2M illustrate an improved fabrication process sequence f or an ultra very large integrated DRAM according to an embodiment of the present invention.

Referring to FIG.1A, on a semiconductor substrate 1 weakly doped with Ptype impurity such as, f or example, Boron, P-type well 2 is formed by ion- implantation of P-type impurity. An active region 3 is defined through photo lithography process. After further ion- implantation of the P-type impurity to the isolation region 4, the field oxide layer 5 is grown by thermal oxidation by the LOCOS method. By this thermal oxidation the P-type well 2 is more deeply expanded into the semiconductor substrate 1, and P+ channel stop ion layer 6 is formed directly under the field oxide layer 5. In the active region 3, a polycrystalline silicon layer doped with an N-type impurity such as, for example, phosphor (P) forming the thin gate oxide film 7, is deposited on the whole surface. The polycrystalline silicon layer is etched by a commercial photo lithography process so as to form a word line conductive layer 8 running in the vertical direction. This word line conductive layer 8 serves as the gate electrode layer in the active region 3 and serves on the f ield oxide layer 5 as the conductive layer to connect the gate electrode layers. Ion-implantation of N+type impurity such as, for example, phosphor is carried out on the whole surface of the structure having the word line conductive layer 8, so that N+ ion layers 9a and 9b selfaligned to the gate electrode layer, are formed in the active

I- 1 6 region 3. Thus, N+ ion layer ga between the field oxide layer 5 and the gate electrode layer 8 serves as source electrode layer and the N+ ion layer 9b between gate electrode layers 8 serves as drain electrode layer. As described above, an interlayer insulating layer 10, such as, for example, HTO (High Temperature Oxide), is deposited on the whole surface of the structure in which an NMOS transistor is formed on the surface of the P-type well 2.

Referring to FIG. 1B, to cover, with resist, the whole surface of the structure in which the interlayer insulating layer 10 is formed, and form the contact hole 12 on the surface of the N+ ion layer 9a provided as the source electrode layer, the interlayer insulating layer 10 is vertically etched by a commercial photo lithography process.

Referring to FIG.1C, after forming said contact hole 12, the resist 11 is removed and then a polycrystalline layer 13 is deposited so as to have a thickness of 1500 to 2000A by LPCVD method.

Referring to FIG.1D, to cover the whole surface of the polycrystalline silicon layer 13 with resist 14 and form the storage electrode layer, the polycrystalline silicon layer 13 is vertically etched by the commercial photo lithography process. Accordingly, the polycrystalline silicon layer 13 between a pair of word line conductive layers 8, constituted by the gate electrode layer arranged on the active region 3 and the conductive layer arranged on field oxide layer 5, remains as the storage electrode layer.

Referring to FIG.1E, after forming the storage 7 electrode layer, a thin insulating film 15 is deposited with a thickness of 60 to 80A on the whole surface of the structure. This insulating film 15 is constituted by a laminated film of thermal oxide film and nitride film, for instance, ONO (Oxide silicon, Nitride silicon, oxide silicon) film. This insulating film serves as the dielectric film of a capacitor.

Referring to FIG.IF, the N+ doped polycrystalline silicon layer 16 is deposited with a thickness of 1500 to 2000 A on the whole surface of the insulating f ilm 15 by LPMD method. This polycrystalline silicon layer 16 serves as the plate electrode layer of a capacitor.

Referring to FIG.lG, to insulate the plate electrode layer around the bit line contact hole, resist 17 is covered on the structure and the polycrystalline silicon layer 16 is then vertically etched by a commercial photo lithography process.

Referring to FIG.lH, according to the commercial manufacturing processing sequence of 4M DRAM, a glass flow layer 18 such as, for example, BPSG film, is deposited to flat the surface and the bit line contact hole 19 is formed on the surface of the N+ ion layer 9b by a commercial photo lithography process. Then, after bit line 20 is formed by the commercial metallization process, passivation film 21 is overlaid and then the chip is completed through the commercial fabrication process.

The above mentioned fabrication process. sequence was explained in connection with the basic processes only for achieving the illustrated structure. Some processes were 8 omitted from the explanation for simplicity.

Referring to FIGS.2A to 2L, a fabrication process sequence according to an embodiment of the present invention will be explained. In the fabrication process sequence, by using the same number of masks as used in the fabrication process of a 4M DRAM cell capacitor, the plate electrode layer is disposed to surround even the lower surface of the storage electrode layer as well as interposing the insulating film between them so as to increase the ef f ective capacitance of the memory cell. Thus, 16M DRAM..is easily achieved by applying the proportionally reduced dimensions of a 4M DRAM.

Referring to FIG.2A, after carrying out the process described in reference to FIG.1A, N+ doped polycrystalline silicon layer 30 serving as a first conductive layer is deposited on the whole surface of the resulting structure so as to have a thickness of 1500 to 2000 A by LP= method.

Referring to FIG.2B, to form the polycrystalline silicon layer 30 into a predetermined pattern, resist 31 is covered on the polycrystalline silicon layer 30, the mask of contact hole is applied, and the resist 31 and the polycrystalline silicon layer 30 are vertically etched by a commercial photo lithography process.

Referring to FIG.2C, after the vertical etching, a horizontal etching is carried out in the polycrystalline silicon layer 30, so that the exposed side of the resultant exposed polycrystalline silicon layer 30 is horizontally etched to a predetermined depth while keeping the etching pattern of the resist 31 in the original state. After the etching, the 1 9 remaining pattern of polycrystalline silicon layer 30 is provided as a partial electrode for the plate electrode layer to surround the lower surface of the storage electrode layer of the cell capacitor.

Referring to FIG.2D, after removing the resist 31, a first thin insulating film 32 is deposited on the whole surface of the resulting structure, and then an N+ doped polycrystalline silicon layer 33 serving as a second conductive layer is successively deposited. In this case, the first insulating film 32 has a thickness of about 60 to,..80 A, and polycrystalline silicon layer 33 has a thickness, such as, for example, 300 to 500 A to protect the first insulating film 32 in the next succeeding etching-process.

Referring to FIG.2E, after the deposition of the polycrystalline silicon layer 33, the resist 34 is deposited on the whole surface, and then the polycrystalline silicon layer 33, insulating film 32 and interlayer insulating layer 10 are successively etched in the vertical direction using the contact hole mask used in the photo lithography process as illustrated in FIG.2B, so that the contact hole 12 is formed to bring the storage electrode layer of the cell capacitor into contact with the source electrode layer 9a of the MOS transistor. At this time, the insulating film 32 is protected in the etching process by the polycrystalline silicon layer 33 with a thickness of 300 to 500 A.

Referring to FIG.2F, after the formation of the contact hole 12 on the source electrode layer 9a, the resist 34 is removed, and then the polycrystalline layer 33 is deposited with a predetermined thickness such as 1500 to 2000 A.

Referring to FIG. 2G, the resist 35 is covered on the polycrystalline layer 33, and then the polycrystalline silicon layer 33 is vertically etched by means of the mask of the storage electrode by a commercial photo lithography process.

Referring to FIG. 2H, after the vertical etching process, the side surface of the polycrystalline silicon layer 33 exposed to the outside by carrying out the horizontal etching via the wet etching is horizontally etched to a predetermined depth.

Referring to FIG.2I, after the wet etching, the resist 35 is removed and then on the whole surface of the remaining structure the thin second insulating film 36 is deposited in a thickness of 60 to SOA, and then an N+ doped polycrystalline silicon layer 37, serving as a third conductive layer, is deposited in a thickness of, for example, 300 to 5OoA, to protect the above second insulating film 36 in the etching process.

Referring to FIG.2J, the resist 38 is overlaid on the whole surface of the above polycrystalline silicon layer 37, and then, by means of the above mentioned storage electrode mask, the surface of the polycrystalline silicon 30 is partially exposed by vertically etching the polycrystalline silicon layer 37 and the second insulating film 36 by a commercial photo lithography process.

Referring to FIG.2K, after the above exposure process, the resist 38 is removed, and then polycrystalline 1 11 silicon layer 37 having a thickness of 1500 to 2000A is deposited and N+ doped over the whole surface of the structure by WCVD method to be electrically contacted with the polycrystalline silicon layer 30 having the partially exposed surface.

Referring to FIG.2L, after the deposition of the above polycrystalline silicon layer 37, resist 39 is overlaid over the whole surface of the structure, and then by applying the mask of the plate electrode layer, polycrystalline silicon layers 37 and 30 around the position where the bit line contact is to be located, are vertically etched by a commercial photo lithography process.

Referring to FIG. 2M, after the above etching process, the bit line 20 is formed by the same processes as illustrated in FIG.1H, to complete the fabrication process.

As described above, to manufacture the cell capacitor of a DRAM, the manufacturing method for the conventional stack type 4M DRAM is applied, and the upper surface and the side surface as well as the lower surface of the storage electrode layer is utilized as the effective area. Thus, by the present manufacturing method for 4M DRAM, the capacitance of memory cell can be doubled in comparison with the conventional one, so that a 16M DRAM can be easily manufactured. Moreover, no extra mask is required due to using the horizontal etching by the wet etching method.

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Claims

1. A method for manufacturing a semiconductor device having a plurality of memory cells, each of which consists of a transistor and a stack capacitor, said method comprising the steps of: forming said transistor on a semiconductor substrate by a commercial manufacturing method for a transistor and then depositing an interlayer insulating layer on the whole surface; depositing a first conductive layer on the whole surface of said interlayer insulating layer and then forming an etching pattern by using a mask and simultaneously vertically etching the first conductive layer to form a designed pattern thereof; horizontally over- etching said resultant pattern of the first conductive layer via wet etching process, by using said etching pattern used for vertically etching said first conductive layer; depositing a first thin insulating film on the whole surface of the structure in which said horizontally overetched first conductive layer is formed, and then depositing a second conductive layer to have the thickness enough to protect said first insulating film; vertically etching said second conductive layer, said first thin insulating film and said interlayer insulating layer by using the mask used in etching said first conductive layer so as to form a first contact hole to contact said transistor; additionally depositing the same material as said 13 second conductive layer in a predetermined thickness on the whole surface of the structure in which said contact hole is formed; forming an etching pattern by using a mask and vertically etching said second conductive layer to form a designed pattern thereof; horizontally overetching said second conductive layer via the wet etching process, by using the etching pattern used for vertically etching said second conductive layer; depositing a thin second insulating film on the whole surf ace of the structure after removing the etching pattern of said second conductive layer, and then depositing a third -conductive layer so as to have the thickness to protect said second insulating film; exposing partial surface of the first conductive layer by vertically etching the third conductive layer and the thin second insulating film with applying the mask used in etching said second conductive layer; and additionally depositing the same materials as the third conductive layer in a predetermined thickness on the whole surface of the structure in which a part of the surface of said first conductive layer is exposed.

2. A method for manufacturing a semiconductor device as set forth in claim 1, wherein said first and second insulating films are formed by laminating thermal oxide films and nitride f ilms.

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3. A method for manufacturing a semiconductor device as set f orth in claim 1 or 2, wherein said f irst to third conductive layers consist of polycrystalline silicon doped with impurity.

4. A method for manufacturing a semiconductor device as set forth in any of claims 1 to 3, wherein said f irst and second insulating films are 60 to so A in thickness.

5. A method for manufacturing a semconductor device as set forth in any of claims 1 to 4, wherein the thicknesses of the first and third conductive layers are about 300 to 500 to protect said first,and second insulating films.

6. A method for manufacturing a semiconductor device as claimed in any of claims 1 to 5 wherein the thickness of the second and third conductive layers are about 300 to 500 A, to protect said first and second insulating film.

7. A method for nanuf acturing a semiconductor device as set forth in any of claims 1 to 6, wherein the predetermined thicknesses of the f irst and third conductive layers are about 1500 to 2000 A.

8. A method f or manufacturing a semiconductor device as set forth in any of claims 1 to 7, wherein said transistor is a MOS transistor.

9. A method for manufacturing a semiconductor device as set forth in any of claims 1 to 8, wherein said method additionally comprises the steps of:

depositing the glass flow layer on the whole surface of said third conductive layer; vertically etching said glass flow layer, the third and the first conductive layers and the interlayer insulating f iln, so as to form a second contact hole to be contact with said transistor; and forming a bit line of said memory cell on the structure having said second contact hole by a metallization process.

10. A method for manufacturing a semiconductor device substantially as hereinbefore described with reference to Figures 2A to 2M of the accompanying drawings.

11. A semiconductor device manufactured by the method as claimed in any preceding claim.

Published 1991 at The Patent Office, Concept House. Cardiff Road, Newport. Gwent NP9 1 RH. Further copies may be obtained from Sales Branch. Unit 6. Nine Mile Point. Cwnifelinfach, Cross Keys, Newport, NP1 7HZ. Printed by Multiplex techniques ltd, St Mary Cray, Kent.