KR930006732B1 - Semiconductor substrate having the structure assembly varied and method of the same - Google Patents
Semiconductor substrate having the structure assembly varied and method of the same Download PDFInfo
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Abstract
Description
제1도는 종래의 실리콘-실리콘 웨이퍼 접합제조 공정을 나타낸 단면도.1 is a cross-sectional view showing a conventional silicon-silicon wafer bonding process.
제2도는 종래의 다결정 실리콘-실리콘 웨이퍼 접합제조 공정을 나타낸 단면도.2 is a cross-sectional view showing a conventional polycrystalline silicon-silicon wafer bonding process.
제3도는 본 발명의 다결정 실리콘-실리콘 웨이퍼 접합제조 공정을 나타낸 단면도.3 is a cross-sectional view showing a polycrystalline silicon-silicon wafer bonding process of the present invention.
제4도는 본 발명에 의한 소자배치의 효율성이 증대된 것을 나타낸 개략도.4 is a schematic view showing that the efficiency of the device arrangement according to the present invention is increased.
제5도는 구조물로서 커패시터가 형성된 본 발명의 실시예를 나타낸 단면도.5 is a cross-sectional view showing an embodiment of the present invention in which a capacitor is formed as a structure.
제6도는 구조물로서 연결선 또는 저항이 형성된 본 발명의 다른 실시예를 나타낸 단면도.6 is a cross-sectional view showing another embodiment of the present invention in which a connecting line or a resistance is formed as a structure.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,17,21 : 시드웨이퍼 2,4,6,11,15 : 실리콘 산화막1,17,21: seed wafer 2,4,6,11,15: silicon oxide film
3,16,36,56,70 : 핸들웨이퍼3,16,36,56,70: Handle Wafer
8,14,37,41,57a,57b,57c,62a,62b,62c : 기판활성영역8,14,37,41,57a, 57b, 57c, 62a, 62b, 62c: substrate active area
27,29,32,35,45,46,47,48,49,52,55,63a,63b,64,67,69,71a,71b,71c : 절연막27,29,32,35,45,46,47,48,49,52,55,63a, 63b, 64,67,69,71a, 71b, 71c
31,43,51,66 : 다결정 실리콘 구조물31,43,51,66: Polycrystalline Silicon Structures
33,53,68 : 다결정 실리콘33,53,68: Polycrystalline Silicon
본 발명은 에스오아이(SOI : Silicon On Insulator)기판 제조에 관한 것으로 종래의 기판접합(WaferBonding)과는 달리 커패시터, 저항, 연결선 등의 임의의 구조물을 미리 형성한 상태에서 기판접합을 수행 함으로써 웨이퍼의 효율성을 극대화 하고, 소자구조의 다양성을 증가시킬 수 있도록 고안된 다결정 실리콘을 이용한 SIO 기판 제조방법 및 그 장치에 관한 것이다.The present invention relates to the fabrication of a silicon on insulator (SOI) substrate, unlike a conventional wafer bonding, a substrate bonding is performed in a state in which arbitrary structures such as capacitors, resistors, and connecting lines are formed in advance. The present invention relates to a method and apparatus for manufacturing an SIO substrate using polycrystalline silicon designed to maximize efficiency and increase diversity of device structures.
실리콘과 실리콘 웨이퍼를 직접 접합시켜 SOI 기판을 형성하는 종래의 SDB(Silicon Direct Bonding) 기술을 일본 후찌사의 히로시코토 등이 1988년 개발한 것으로 첨부된 제1도에 따라 간단히 설명하면 다음과 같다.The conventional SDB (Silicon Direct Bonding) technology for directly bonding silicon and silicon wafers to form an SOI substrate was developed in 1988 by Hiroshikoto et al., Fuchi, Japan.
제1a도는 웨이퍼에 산화막을 증착하는 과정이 돤료된 상태를 나타낸 것이다. 소자가 형성될 시드웨이퍼(1)와 지지용 핸들웨이퍼(3) 각각의 전표면 약 5000Å 두께로 산화막(2,4)을 증착한다. 다음, 시드웨이퍼(1)와 헨들웨이퍼(3)를 접촉시킨 상태로 약 800℃ 온도에서 100-5OOV 전압펄스를 인가하여 접합한 후, 접합상태를 더욱 강하게 하기 위하여 900-1100℃의 온도로 질소 또는 산소 내에서 약 30분 동안 열처리하여 시드웨이퍼(1)와 핸들웨이퍼(3)가 결합되도록 한다.FIG. 1A illustrates a state in which an oxide film is deposited on a wafer. Oxide films 2 and 4 are deposited to a thickness of approximately 5000 Å on the entire surface of each of the seed wafer 1 and the support handle wafer 3 on which the device is to be formed. Next, after bonding the seed wafer 1 and the handle wafer 3 in contact with 100-5OOV voltage pulses at a temperature of about 800 ° C., the nitrogen at a temperature of 900-1100 ° C. to further strengthen the bonding state. Alternatively, the seed wafer 1 and the handle wafer 3 are combined by heat treatment in oxygen for about 30 minutes.
이와같은 과정이 완료된 상태가 제1b도에 도시되어 있다.The state in which this process is completed is shown in FIG.
상기 과정을 통하여 상기 두 웨이퍼(1,3)가 결합된 웨이퍼(5)는 약 100㎏/㎠ 이상의 강한 결합력을 갖게 된다.Through the above process, the wafer 5 to which the two wafers 1 and 3 are combined has a strong bonding force of about 100 kg / cm 2 or more.
제1c도는 연마(polishing) 과정을 나타낸 것으로, 기계적 및 화학적 연마과정을 통하여 산화막(6)상의 시드웨이퍼(1)를 연마하고, 약 1㎛ 정도 두께의 산화막(6)에 의해 시드웨이퍼(1)와 핸들웨이퍼(3)가 분리된 형태의 OSI 기판(8)이 형성된다.FIG. 1C illustrates a polishing process, wherein the seed wafer 1 on the oxide film 6 is polished through mechanical and chemical polishing processes, and the seed wafer 1 is formed by the oxide film 6 having a thickness of about 1 μm. And the OSI substrate 8 in which the handle wafer 3 is separated.
또한, 1989년 고체소자 자료회의(Selid State Device and Materials)에서 일본 소니사의 마시보 등은 다결정 실리콘을 이용한 P-SDB(Polycystalline to Sillicon Direct Bonding) 방법을 개시하였다. 그것을 첨부된 제2도에 따라 설명하면 다음과 같다.Also, in 1989, at the Solid State Device and Materials, Japan's Sony Corp., etc., disclosed a P-SDB (Polycystalline to Sillicon Direct Bonding) method using polycrystalline silicon. It will be described according to the attached Figure 2 as follows.
제2a도는 다결정 실리콘을 증착하는 과정을 도시한 것으로 우선 원하는 SOI는 두께(약 1000Å)만큼 시드웨이퍼(17)에 메사(mesa : 10)를 형성하고 메사(10)의 상면에 산화막(11)을 1㎛ 두께 정도로 증착한 후 상기 산화막(11)의 상면에 다결정 실리콘(12)을 5.0㎛ 정도의 두께로 증착한다.FIG. 2A illustrates a process of depositing polycrystalline silicon. First, a desired SOI is formed by forming a mesa (10) on the seed wafer 17 by a thickness (about 1000 mW) and forming an oxide film 11 on the upper surface of the mesa 10. After depositing about 1 μm thick, polycrystalline silicon 12 is deposited on the upper surface of the oxide film 11 to about 5.0 μm thick.
제2b도에 나타낸 바와같이 다결정 실리콘(12)이 증착된 표면의 요철을 연마과정을 통하여 경면(mirror surface) 처리하여 다결정 실리콘의 표면요철을 제거한다. 시드웨이퍼와 다결정 실리콘 경면(13)과 핸들웨이퍼(16)에 산화막(15)을 입히고 전술한 것과 동힐한 P-SDB 과정을 통하여 다결정 실리콘 경면(13)과 핸들웨이퍼(16)를 접합시킨 후 제2c도에 나타난 바와같이 시드웨이퍼(17)를 위로 향하도록 배열한다.As shown in FIG. 2B, the surface irregularities of the surface on which the polycrystalline silicon 12 is deposited are subjected to a mirror surface treatment to remove surface irregularities of the polycrystalline silicon. After the oxide film 15 is applied to the seed wafer, the polycrystalline silicon mirror surface 13 and the handle wafer 16, and the polycrystalline silicon mirror surface 13 and the handle wafer 16 are bonded through the P-SDB process described above, Arrange the seed wafer 17 upward as shown in FIG. 2C.
제2d도는 시드웨이퍼(17)의 실리콘 박막화를 위한 연마과정을 나타낸 것으로, 시드웨이퍼(16)를 기계적, 화학적 연마과정을 통해 연마해 내려가다가 메사패턴(10)에 채워져 있는 산화막(11)에 이르러 연마작업을 중단한 상태를 도시한 것이다. 상기 산화막(11)은 연마중지(Polishing Stop) 역활을 하게 되므로 SOI(14)의 두께는 메시식각(10)의 깊이에 의해 조절될 수 있다.2d illustrates a polishing process for thinning the silicon wafer of the seed wafer 17. The seed wafer 16 is polished by mechanical and chemical polishing, and then the oxide film 11 filled in the mesa pattern 10 is reached. It shows a state where the polishing operation is stopped. Since the oxide film 11 plays a role of polishing stop, the thickness of the SOI 14 may be controlled by the depth of the mesh etching 10.
상기와 같이 종래의 P-SDB 제조방법에서 사용된 다결정 실리콘층(12)은 시드웨이퍼에 형성된 메사패턴으로 인하여 발생되는 표면의 요철을 제거하여 접착계면을 평탄화(planarization)함으로써 시드웨이퍼와 핸들웨이퍼의 접착을 용이하게 한다.As described above, the polycrystalline silicon layer 12 used in the P-SDB manufacturing method of the seed wafer and the handle wafer is planarized by removing the irregularities of the surface caused by the mesa pattern formed on the seed wafer. Facilitates adhesion.
본 발명은 시드웨이퍼와 핸들웨이퍼를 접착시키기 전에 시드웨이퍼의 상면에 전도성막 또는 저항성막(본원에서는 다결정 실리콘막을 그 한예로 설명함)을 다층으로 증착하여 전기적 특성을 갖는 임의의 구조물, 예를들면 커패시터(capacitor), 저항, 연결선(interconnector)등을 개별적 또는 복합적으로 형성한 후 시드웨이퍼의 구조물이 형성된 면과 핸들웨이퍼를 접착시켜 SOI 기판을 제조함으로써, 시드웨이퍼와 핸들웨이퍼 사이에 전기걱 특성을 갖는 임의의 구조물이 매몰되어 있는 새로운 형태의 SOI 기판을 형성하여 웨이퍼의 효율성을 극대화하고 소자구조의 다양성을 증가시키는 것을 목적으로 한다.The present invention relates to any structure having electrical properties by depositing a conductive film or a resistive film (herein described as a polycrystalline silicon film as one example) on the top surface of the seed wafer before bonding the seed wafer and the handle wafer, for example, a capacitor. (capacitor), resistance, and interconnector are formed individually or in combination, and then the surface of the seed wafer structure is bonded to the handle wafer to manufacture the SOI substrate, which has a spatula characteristic between the seed wafer and the handle wafer. The purpose is to form a new type of SOI substrate in which an arbitrary structure is buried to maximize the efficiency of the wafer and increase the diversity of device structures.
본 발명을 첨부된 도면을 참고로 하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
제3a도는 제1다결정 실리콘(30)을 증착하는 공정이 완료된 상태를 도시한 것이다. 그 과정을 단계적으로 설명하면 다음과 같다.3A illustrates a state in which a process of depositing the first polycrystalline silicon 30 is completed. The process is described step by step as follows.
먼저, 시드웨이퍼(21)의 상면에 제1격리용 절연막(27)을 소정의 두께로 형성한다. 다음 상기 제1격리용 절연막(27)의 상면에 제2격리용 절연막(29)를 형성한 후 기판 콘택 마스크로 기판콘택(28)을 식각한다. 마지막으로 상기 제2격리용 절연막(29)과 상기 기판콘택(28)의 상면에 제1다결정 실리콘(30)을 소정의 두께로 증착하고 도핑한다.First, the first isolation insulating film 27 is formed on the top surface of the seed wafer 21 to have a predetermined thickness. Next, the second insulating insulating layer 29 is formed on the upper surface of the first insulating insulating layer 27, and the substrate contact 28 is etched using the substrate contact mask. Finally, the first polycrystalline silicon 30 is deposited and doped to the upper surface of the second isolation insulating layer 29 and the substrate contact 28.
이때, SOI의 두께는 제1격리용 절연막(27)이 시드웨이퍼(21)에 침투된 깊이가 되므로 상기 제1격리용 절연막(27)의 두께 조정에 주의하여야 한다. 또한, 제1다결정 실리콘(30)의 두께는 형성되는 구조물의 전기적 특성에 따라서 결정된다. 특히, 구조물이 연결선으로 응용될 경우에는 제1다결정 실리콘(30) 대신 내화금속(refractory metal)이나 폴리사이드(Polycide) 또는 실리사이드(silicide)등으로 대체할 수도 있다.At this time, the thickness of the SOI becomes a depth in which the first isolation insulating layer 27 penetrates the seed wafer 21, so care should be taken in adjusting the thickness of the first isolation insulating layer 27. In addition, the thickness of the first polycrystalline silicon 30 is determined according to the electrical characteristics of the structure to be formed. In particular, when the structure is applied as a connection line, it may be replaced with refractory metal, polycide, or silicide instead of the first polycrystalline silicon 30.
제3b도는 전기적 구조물을 형성하는 공정을 완료한 상태를 도시한 것으로 단계별로 설명하면 다음과 같다.3b illustrates a state in which a process of forming an electrical structure is completed and described in stages.
먼저, 제1다결정 실리콘층(30)에 미세패턴을 형성하여 전기적 구조물(31)을 정의한 후 상기 전기적 구조물을 위한 격리용 절연막(32)을 증착한 후 표면의 요철을 제거하기 위하여 제2다결정 실리콘층을 연마작업에 의한 평탄화 작업을 수행하여 경면(34b)으로 처리한다.First, after forming a fine pattern on the first polycrystalline silicon layer 30 to define the electrical structure 31, and then depositing the insulating insulating film 32 for the electrical structure, the second polycrystalline silicon to remove the surface irregularities The layer is subjected to the flattening operation by polishing to treat the mirror surface 34b.
이때 제3a 및 b도에서 제1다결정 실리콘(30) 및 제2다결정 실리톤(33)은 필요에 따라 N형 또는 P형 불순물으로 도핑된다. 또한, 상기한 바대로 제1다결정 실리콘(30)은 응용분야에 따라 다른 재질로 대체될 수 있다.In this case, the first polycrystalline silicon 30 and the second polycrystalline silicide 33 are doped with N-type or P-type impurities as necessary. In addition, as described above, the first polycrystalline silicon 30 may be replaced with another material according to an application.
제3c도는 제3b도의 전기적 구조물의 형성이 완료된 시드웨이퍼를 뒤집어서 핸들웨이퍼(36)에 접착시킨 상태를 도시한 것으로 그 공정을 설명하면 다음과 같다. 핸들웨이퍼(36) 위에 절연막(35)을 형성하고, 시드웨이퍼(21)의 다결정 실리콘 경면(34b)과 상기 절연막(35)을 접촉시킨 후, 열처리 과정을 통하여 두 웨이퍼(21,36)를 결합시킨다. 이때 절연막(35)은 시드웨이퍼의 제2다결정 실리콘층(33)과 헨들웨이퍼(36)를 전기적으로 분리시키는 역할을 한다. 경우에 따라서는 상기 절연막(35)을 형성시키는 공정은 생략함으로써 핸들웨이퍼와 제2다결정 실리콘층(33)이 전기적으로 연결되게 하여 제2다결정 실리콘층(33)에 인가되어야 할 전기적 포텐실(potential)을 핸들웨이퍼로부터 제공받을 수도 있다.FIG. 3c illustrates a state in which the seed wafer having completed the formation of the electrical structure of FIG. 3b is inverted and bonded to the handle wafer 36. The process will be described below. An insulating film 35 is formed on the handle wafer 36, the polycrystalline silicon mirror surface 34b of the seed wafer 21 is brought into contact with the insulating film 35, and then the two wafers 21 and 36 are bonded through a heat treatment process. Let's do it. In this case, the insulating layer 35 serves to electrically separate the second polycrystalline silicon layer 33 and the handle wafer 36 of the seed wafer. In some cases, the process of forming the insulating layer 35 is omitted to allow the handle wafer and the second polycrystalline silicon layer 33 to be electrically connected to each other, thereby providing an electrical potential to be applied to the second polycrystalline silicon layer 33. ) May be provided from the handle wafer.
상기한 접착공정이 완료되면, 즉 제3c도의 상태에서 시드웨이퍼(21)의 상면으로부터 제1격리용 절연막(27)이 만나는 지점(38)까지 기계적 및 화학적 연마과정을 통하여 시드웨이퍼(21)를 제거함으로써 상기 제1다결정 실리콘을 증착하는 공정에서 설명한 바와같이, 제1격리용 절연막(27)이 시드웨이퍼(21)에 침투된 깊이만큼의 실리콘 박막 두께를 갖는 SOI 기판을 제조할 수 있다.When the above bonding process is completed, that is, the seed wafer 21 is subjected to mechanical and chemical polishing from the top surface of the seed wafer 21 to the point 38 where the first isolation insulating film 27 meets in the state shown in FIG. 3C. As described above, the SOI substrate having the silicon thin film thickness as much as the depth of the first isolation insulating film 27 penetrated into the seed wafer 21 can be manufactured as described in the process of depositing the first polycrystalline silicon.
제3d도는 구조물이 매몰된 형태의 SOI 기판에 대한 단면도를 나타낸 것이다. 시드웨이퍼(21)의 최초 표면은 참조번호 39로 표시된 부분이었으나 SDB 과정 및 연마과정을 거치면서 활성소자가 형성될 실리콘 박막의 두번째 표면(40)이 형성된다.3d illustrates a cross-sectional view of an SOI substrate having a buried structure. Although the initial surface of the seed wafer 21 was indicated by reference numeral 39, the second surface 40 of the silicon thin film on which the active element is to be formed is formed through the SDB process and the polishing process.
본 발명의 제조과정을 통하여 구조물(31)을 미리 형성한 시드웨이퍼(21)와 핸들웨이퍼(36)를 결합시키고 다시 시드웨이퍼의 뒷면을 연마하여 박막화 함으로써 다층의 다결정 실리콘층을 이용한 P-SDB에 의해 새로운 구조의 SOI 기판을 구현한다.Through the fabrication process of the present invention, the seed wafer 21 and the handle wafer 36, which are previously formed of the structure 31, are bonded to each other, and the back surface of the seed wafer is polished and thinned to a P-SDB using a multilayer polycrystalline silicon layer. By implementing a new structure of the SOI substrate.
종래의 기술과 비교할 때 본 발명은 동일 면적내에 보다 효율적으로 소자를 배치할 수 있다. 그와 같은 고밀화 할 수 있는 형태를 개념적으로 구성한 것을 제4도에 나타냈다.Compared with the prior art, the present invention can arrange elements more efficiently in the same area. Figure 4 shows the conceptual construction of such a densable form.
제4a도는 본 발명에 의한 구조물의 배치상태를 나타낸 것이다. 활성영역(41) 내부에 구조물(43)과 그 구조물을 활성영역(41)에 연결하는 기판콘텍(42)이 함께 중첩되게 배치된다.Figure 4a shows the arrangement of the structure according to the present invention. The structure 43 and the substrate contact 42 connecting the structure to the active region 41 are disposed to overlap each other in the active region 41.
제4b도는 제4a도의 단면도로써 SOI 기판 즉, 활성영역(41)과 구조물(43)이 기판콘택(42)을 통해 수직으로 연결되어 있음을 보이고 있다.FIG. 4B is a cross-sectional view of FIG. 4A showing that the SOI substrate, that is, the active region 41 and the structure 43 are vertically connected through the substrate contact 42.
상기 활성영역(41) 상호간을 제1격리용 절연막(46)에 의해 격리된다. 상기 활성영역(11)과 매몰된 구조물(43)은 필요한 위치에 기판콘택(42)을 형성함으로써 그 위치에서는 그들 상호간 전기적으로 연결되지만 그밖의 위치에서는 제2격리용 절연막(47)에 의해 상호 전기적으로 격리된다. 또한, 형성된 구조물을 제3격리용 절연막(45)를 이용하여 전기적으로 격리시킨다.The active regions 41 are separated from each other by the first insulating insulating layer 46. The active region 11 and the buried structure 43 are electrically connected to each other at the required position by forming the substrate contact 42 at the required position, but are electrically connected to each other by the second insulating insulating film 47 at other positions. Are isolated. In addition, the formed structure is electrically isolated using the third isolation insulating layer 45.
상기 배치도(제4도)에서 알 수 있듯이 본 발명에 의한 SOI 구조는 매몰된 층에 전기적 특성을 갖는 소자 예를들면, 커패시터, 저항, 연결선 등을 개별적 또는 복합적으로 형성할 수 있게 되어 실리콘 박막층(41)이 형성되는 소자와 수직적으로 배치가 이루어지게 되므로 소자의 고밀도가 가능해진다.As can be seen from the layout (FIG. 4), the SOI structure according to the present invention can form elements having electrical characteristics, for example, capacitors, resistors, and connection lines, individually or in combination, in a buried layer. Since the arrangement is made perpendicular to the element to be formed 41), high density of the element is possible.
이와같이 소자들이 수직적으로 배치됨으로써 3차원적 소자 배치가 가능하게 되어 새로운 형태의 3차원 집적회로(3-Dimensional Integrated Circuit)가 실현된다.As the devices are arranged vertically, a three-dimensional device arrangement is possible, thereby realizing a new type of 3-Dimensional Integrated Circuit.
제5도는 본 발명에 따른 실시예로써 매립된 구조물이 커패시터 인 경우를 나타낸 단면도이다. 커패시터의 전하축전 전극(51)은 기판콘택(50)을 통하여 활성영역(57a,57b,57c)과 수직적으로 연결되어 있으며, 또한 커패시터의 유전막(52)을 사이에 두고 상기 전하축전 전극(51) 아래에 커패시터의 플레이트 전극(50)으로서 다결정 실리콘층이 형성되어 있다.5 is a cross-sectional view showing a case in which the buried structure is a capacitor according to an embodiment of the present invention. The charge storage electrode 51 of the capacitor is vertically connected to the active regions 57a, 57b, 57c through the substrate contact 50, and the charge storage electrode 51 is disposed with the dielectric film 52 of the capacitor interposed therebetween. A polycrystalline silicon layer is formed below as the plate electrode 50 of the capacitor.
이런 구조에 대한 제조공정 순서를 설명하면 다음과 같다. 먼저, 시드웨이퍼의 활성영역(57a,57b,57c)간의 격리를 위하여 L0COS 방법에 의하여 제1격리용 절연막(48a,48b,48c)을 형성하고, 활성영역(57a,57b,57c)을 OSI화 하기 위하여 제2격리용 절연막(49a,49b,49c)을 형성한 후, 필요한 부분에 기판콘택(50)을 정의한다. 그다음, 커패시터의 전하축전 전극용 다결정 실리콘층(51)을 증착 정의한 후 커패시터 유전막(52)을 형성하고 그위에 플레이트 전극용 다결정 실리콘층(53)을 충분한두께로 증착한다.The manufacturing process sequence for this structure is as follows. First, in order to isolate between the active regions 57a, 57b, and 57c of the seed wafer, the first isolation insulating layers 48a, 48b, and 48c are formed by the L0COS method, and the active regions 57a, 57b, and 57c are OSIized. In order to form the second isolation insulating film 49a, 49b, and 49c, the substrate contact 50 is defined in the required portion. Next, after defining the polycrystalline silicon layer 51 for the charge storage electrode of the capacitor, the capacitor dielectric film 52 is formed, and the polycrystalline silicon layer 53 for the plate electrode is deposited thereon to a sufficient thickness.
이와같이 플레이트 전극용 다결정 실리콘층을 증착한 후 그 표면(54)을 경면처리 하여 표면에 절연막(55)이 형성되어 있는 핸들웨이퍼(56)를 접착시킨다. 그 접착공정이 완료된 후 시드웨이퍼를 화학적, 기계적으로 연마하여 시드웨이퍼의 박막화 공정을 수행한다. 시드웨이퍼의 박막화는 제1격리용 절연막(48a,48b,49c)이 나타나는 지점에서 중단되어 일정한 두께의 실리콘 박막이 활성영역으로 남게된다.After depositing the polycrystalline silicon layer for the plate electrode in this manner, the surface 54 is mirror-treated to bond the handle wafer 56 having the insulating film 55 to the surface. After the bonding process is completed, the seed wafer is chemically and mechanically polished to perform a thinning process of the seed wafer. The thinning of the seed wafer is stopped at the point where the first isolation insulating films 48a, 48b, and 49c appear, leaving a silicon thin film of a constant thickness as an active region.
이와같이 활성영역이 형성된 후 노드콘택(60) 및 플레이트 콘택(59)을 형성하고 금속막을 이용하여 플레이트 전극(61a)과 노드전극(61b)을 형성한다.After the active region is formed, the node contact 60 and the plate contact 59 are formed, and the plate electrode 61a and the node electrode 61b are formed using a metal film.
상기의 공정들을 통하여 매립된 형태의 커패시터 구조물이 형성된다. 본 실시예에 대한 변형예로써, 플레이트 전극용 다결정 실리콘을 절연막(55)이 형성되어 있지 않은 핸들웨이퍼와 접착시킴으로써 핸들웨이퍼를 통하여 바이어스(bias)를 직접 인가할 수도 있다. 또한, 전하축전 전극용 다결정 실리콘(51)은 기판콘택(50)을 통하여 수직으로 연결되어 있는 활성영역에 제조될 반도체 소자 즉, MOSFET 또는 쌍극형 트랜지스터와도 직접 연결이 가능하다.Through the above processes, a capacitor structure having a buried shape is formed. As a modification to the present embodiment, a bias may be directly applied through the handle wafer by bonding the polycrystalline silicon for plate electrode with the handle wafer on which the insulating film 55 is not formed. In addition, the polycrystalline silicon 51 for the charge storage electrode can be directly connected to a semiconductor device, that is, a MOSFET or a bipolar transistor, to be manufactured in an active region vertically connected through the substrate contact 50.
아울러 본 실시예의 커패시터는 전하축전 전극용 다결정 실리콘(51)의 두께가 수천 Å정도로 비교적 얇은 매립형 스택 커패시터(stack capacitor)를 구조물로 표시하였으나 매립형 트랜치 커패시터(trench capacitor) 구조도 상기의 제조공정과 동일한 방법으로 제조할 수 있다.In addition, the capacitor of the present embodiment is a structure of a buried stack capacitor having a relatively thin thickness of the polycrystalline silicon (51) for the charge storage electrode as thousands of 수천, but the buried trench capacitor structure is the same as the manufacturing process It can manufacture by a method.
제6도는 본 발명에 의한 또다른 실시예로써 매립된 구조물이 반도체 집적회로의 필요부분 상호간을 전기적으로 연결하는 도선(interconnection) 또는 저항(resistor)으로 사용된 경우를 나타내는 단면도이다.FIG. 6 is a cross-sectional view illustrating a case in which a buried structure is used as an interconnection or a resistor that electrically connects necessary portions of a semiconductor integrated circuit as another embodiment according to the present invention.
활성영역(62a,62b,62c) 상호간은 제1격리용 절연막(63a,63b)으로 서로 분리되어 있으며, 활성영역(62a)과 또다른 활성영역(62c)을 전기적으로 연결시키기 위하여 불순물이 도핑된 제1다결정 실픽콘(66)이 매립된 구조물 형태로 형성되어 있다. 이러한 경우 연결선(interconnector) 또는 저항으로 사용되는 제1다결정 실리콘(66)은 제2격리용 절연막(64)에 의하여 활성영역 부분들과 전기적으로 분리되어 있으며, 또한 연결이 필요한 부분에서는 기판콘택(65a,65b)을 통하여 활성영역과 전기적으로 연결이 이루어져 있다.The active regions 62a, 62b, and 62c are separated from each other by the first isolation insulating layers 63a and 63b, and are doped with impurities to electrically connect the active region 62a and another active region 62c. The first polycrystalline silpiccon 66 is formed in a buried structure. In this case, the first polycrystalline silicon 66, which is used as an interconnector or a resistor, is electrically separated from the active region portions by the second isolation insulating film 64, and the portion of the substrate contact 65a where the connection is necessary. 65b) is electrically connected to the active area.
이러한 제1다결정 실리콘(66)에 불순물을 주입시킨뒤 연결선 또는 저항으로서 필요한 패턴을 정의한 후 제3격리용 절연막(67)과 제2다결정 실리콘(68)을 형성한다. 제2다결정 실리콘(68) 표면을 경면 처리한 후 절연막(69)가 형성되어 있는 핸들웨이퍼(70)와 접착시킨다. 이때 절연막(69)을 생략함으로써 제2다결정 실리콘에 핸들웨이퍼를 통하여 백 바이어스(back bias)를 인가할 수도 있다.After the impurity is injected into the first polycrystalline silicon 66, a necessary pattern is defined as a connection line or a resistance, and then the third isolation insulating layer 67 and the second polycrystalline silicon 68 are formed. The surface of the second polycrystalline silicon 68 is mirror-polished and then adhered to the handle wafer 70 on which the insulating film 69 is formed. In this case, the back bias may be applied to the second polycrystalline silicon through the handle wafer by omitting the insulating layer 69.
이와같이 기판접착이 이루어진 후 시드웨이퍼는 상기 제3도 에서 설명된 바와같이 화학적 및 기계적인 연마과정을 통하여 제1격리용 절연막(63a,63b)을 만날때 까지 박막화 된다. 이러한 과정을 수행하여 형성된 활성영역중 제1다결정 실리콘(66)과 연결되어 있는 활성영역(62a) 및 활성영역(62c)에 콘텍(72a) 및 콘텍(72b)을 전연막(71a,72b,71c)을 이용하여 형성한 후 도체(73a) 및 도체(73b)들과 각각 연결시킴으로써 제1다결정 실리콘(66)이 매립된 구조물로써 연결선 또는 저항의 역할을 하게 된다.After the substrate is bonded as described above, the seed wafer is thinned until the first isolation insulating layers 63a and 63b are met through chemical and mechanical polishing processes as described in FIG. 3. The contact films 72a and 72b are connected to the active regions 62a and 62c of the active regions 62a and 72c which are connected to the first polycrystalline silicon 66. After forming by using the () and by connecting to the conductors (73a) and the conductors (73b), respectively, the first polycrystalline silicon 66 is a buried structure to act as a connection line or a resistance.
본 실시예에 대한 변형예로써, 연결선 또는 저항으로 이용되는 제1다결정 실리콘(66)은 기판콘텍(65a,65b)을 통하여 전기적으로 연결되어 있는 활성영역(62a,62b)에 제조될 반도체 소작 즉 MOSFET 또는 쌍극형 트렌지스터 등과도 직접 연결이 가능하다. 아울러 매립된 구조물 박막 대신 폴리사이드(polycide) 또는 실리사이드(silicide) 박막을 사용하므로써 연결선의 저항을 감소시킬 수도 있다.As a modification to the present embodiment, the first polycrystalline silicon 66 used as a connection line or a resistor is a semiconductor cauterization to be manufactured in the active regions 62a and 62b electrically connected through the substrate contacts 65a and 65b. Direct connection to MOSFETs or bipolar transistors is also possible. In addition, by using a polycide (silcide) or silicide (silicide) thin film in place of the buried structure thin film it is possible to reduce the resistance of the connection line.
본 발명에 의한 상기의 제조방법과 그 실시예에서 볼 수 있듯이 두장의 실리콘 웨이퍼를 접착시켜 SOI 기판을 제조할 때, 한장의 웨이퍼 즉 시드웨이퍼에 다층의 전도성 박막 혹은 절연막을 이용하여 커패시터, 연결선 또는 저항등을 전기적 특성을 갖는 구조물을 단층 또는 다층으로 형성하거나 혹은 개별적 또는 2가지 이상의 종류가 복합적으로 구성된 형태의 구조물을 형성한 후 다른 한장의 웨이퍼 즉 핸들웨이퍼와 접착시킴으로써 전기적 특성을 갖는 구조물이 매립된 형태의 새로운 SOI 기판을 제조할 수 있다.As can be seen from the above-described manufacturing method and the embodiment of the present invention, when fabricating an SOI substrate by bonding two silicon wafers, a capacitor, a connecting line or the like using a multilayer conductive thin film or insulating film on one wafer, that is, a seed wafer, A structure having electrical characteristics is embedded by forming a structure having electrical characteristics such as resistance in a single layer or a multilayer, or by forming a structure in which an individual or a combination of two or more kinds is formed, and then bonding it with another wafer, that is, a handle wafer. It is possible to manufacture new types of SOI substrates.
이러한 형태의 새로운 SOI 기판 제조기술을 이용하면 반도체 칩(chip) 면적의 효율성을 증가시킬 수 있으며, 특히 매립된 구조물이 커패시터인 경우 DRAM(Dynamic Random Access Memory)의 기억세포(Cell) 등을 보다 작은 면적에서 용이하게 제작할 수 있게 된다.Using this type of new SOI substrate manufacturing technology, the efficiency of semiconductor chip area can be increased. In particular, when embedded structures are capacitors, memory cells of DRAM (Dynamic Random Access Memory) can be made smaller. It can be easily produced in the area.
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JPS63308386A (en) * | 1987-01-30 | 1988-12-15 | Sony Corp | Semiconductor device and manufacture thereof |
JPH01120847A (en) * | 1987-11-05 | 1989-05-12 | Fujitsu Ltd | Semiconductor device |
JPH02208952A (en) * | 1989-02-08 | 1990-08-20 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
KR930000718B1 (en) * | 1990-05-21 | 1993-01-30 | 삼성전자 주식회사 | Method for fabricating semiconductor device |
JP2913785B2 (en) * | 1990-07-12 | 1999-06-28 | 富士通株式会社 | Method for manufacturing semiconductor device |
US5091330A (en) * | 1990-12-28 | 1992-02-25 | Motorola, Inc. | Method of fabricating a dielectric isolated area |
-
1991
- 1991-05-08 KR KR1019910007454A patent/KR930006732B1/en not_active IP Right Cessation
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1992
- 1992-05-08 US US07/880,892 patent/US5286670A/en not_active Expired - Lifetime
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US5286670A (en) | 1994-02-15 |
JPH0661339A (en) | 1994-03-04 |
JPH0821621B2 (en) | 1996-03-04 |
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