KR930006732B1 - Semiconductor substrate having the structure assembly varied and method of the same - Google Patents

Abstract

The method comprises (a) forming a 1st insulation film (27) on the seed wafer (21), (b) forming a 2nd insulation film (29) on (27) and defining substrate contact (28), (c) depositing a 1st polycrystalline silicon (30) on (28), (d) forming fine pattern on (30) to define electric structural body (31), (e) growing or depositing insulation film (32) for (31), (f) depositing a 2nd polycrystalline silicon layer (33) and grinding (33) into mirror plane to remove surface unevenness, (g) forming insulation film (35) on handle wafer (36) and joining the mirror plane (34b) with the film (35), and (h) grinding the wafer (21) into thin film until the film (27) appears from the rear side (21a) of (21).

Description

Semiconductor substrate with embedded structure having electrical characteristics and manufacturing method thereof

1 is a cross-sectional view showing a conventional silicon-silicon wafer bonding process.

2 is a cross-sectional view showing a conventional polycrystalline silicon-silicon wafer bonding process.

3 is a cross-sectional view showing a polycrystalline silicon-silicon wafer bonding process of the present invention.

4 is a schematic view showing that the efficiency of the device arrangement according to the present invention is increased.

5 is a cross-sectional view showing an embodiment of the present invention in which a capacitor is formed as a structure.

6 is a cross-sectional view showing another embodiment of the present invention in which a connecting line or a resistance is formed as a structure.

* Explanation of symbols for main parts of the drawings

1,17,21: seed wafer 2,4,6,11,15: silicon oxide film

3,16,36,56,70: Handle Wafer

8,14,37,41,57a, 57b, 57c, 62a, 62b, 62c: substrate active area

27,29,32,35,45,46,47,48,49,52,55,63a, 63b, 64,67,69,71a, 71b, 71c

31,43,51,66: Polycrystalline Silicon Structures

33,53,68: Polycrystalline Silicon

The present invention relates to the fabrication of a silicon on insulator (SOI) substrate, unlike a conventional wafer bonding, a substrate bonding is performed in a state in which arbitrary structures such as capacitors, resistors, and connecting lines are formed in advance. The present invention relates to a method and apparatus for manufacturing an SIO substrate using polycrystalline silicon designed to maximize efficiency and increase diversity of device structures.

The conventional SDB (Silicon Direct Bonding) technology for directly bonding silicon and silicon wafers to form an SOI substrate was developed in 1988 by Hiroshikoto et al., Fuchi, Japan.

FIG. 1A illustrates a state in which an oxide film is deposited on a wafer. Oxide films 2 and 4 are deposited to a thickness of approximately 5000 Å on the entire surface of each of the seed wafer 1 and the support handle wafer 3 on which the device is to be formed. Next, after bonding the seed wafer 1 and the handle wafer 3 in contact with 100-5OOV voltage pulses at a temperature of about 800 ° C., the nitrogen at a temperature of 900-1100 ° C. to further strengthen the bonding state. Alternatively, the seed wafer 1 and the handle wafer 3 are combined by heat treatment in oxygen for about 30 minutes.

The state in which this process is completed is shown in FIG.

Through the above process, the wafer 5 to which the two wafers 1 and 3 are combined has a strong bonding force of about 100 kg / cm 2 or more.

FIG. 1C illustrates a polishing process, wherein the seed wafer 1 on the oxide film 6 is polished through mechanical and chemical polishing processes, and the seed wafer 1 is formed by the oxide film 6 having a thickness of about 1 μm. And the OSI substrate 8 in which the handle wafer 3 is separated.

Also, in 1989, at the Solid State Device and Materials, Japan's Sony Corp., etc., disclosed a P-SDB (Polycystalline to Sillicon Direct Bonding) method using polycrystalline silicon. It will be described according to the attached Figure 2 as follows.

FIG. 2A illustrates a process of depositing polycrystalline silicon. First, a desired SOI is formed by forming a mesa (10) on the seed wafer 17 by a thickness (about 1000 mW) and forming an oxide film 11 on the upper surface of the mesa 10. After depositing about 1 μm thick, polycrystalline silicon 12 is deposited on the upper surface of the oxide film 11 to about 5.0 μm thick.

As shown in FIG. 2B, the surface irregularities of the surface on which the polycrystalline silicon 12 is deposited are subjected to a mirror surface treatment to remove surface irregularities of the polycrystalline silicon. After the oxide film 15 is applied to the seed wafer, the polycrystalline silicon mirror surface 13 and the handle wafer 16, and the polycrystalline silicon mirror surface 13 and the handle wafer 16 are bonded through the P-SDB process described above, Arrange the seed wafer 17 upward as shown in FIG. 2C.

2d illustrates a polishing process for thinning the silicon wafer of the seed wafer 17. The seed wafer 16 is polished by mechanical and chemical polishing, and then the oxide film 11 filled in the mesa pattern 10 is reached. It shows a state where the polishing operation is stopped. Since the oxide film 11 plays a role of polishing stop, the thickness of the SOI 14 may be controlled by the depth of the mesh etching 10.

As described above, the polycrystalline silicon layer 12 used in the P-SDB manufacturing method of the seed wafer and the handle wafer is planarized by removing the irregularities of the surface caused by the mesa pattern formed on the seed wafer. Facilitates adhesion.

The present invention relates to any structure having electrical properties by depositing a conductive film or a resistive film (herein described as a polycrystalline silicon film as one example) on the top surface of the seed wafer before bonding the seed wafer and the handle wafer, for example, a capacitor. (capacitor), resistance, and interconnector are formed individually or in combination, and then the surface of the seed wafer structure is bonded to the handle wafer to manufacture the SOI substrate, which has a spatula characteristic between the seed wafer and the handle wafer. The purpose is to form a new type of SOI substrate in which an arbitrary structure is buried to maximize the efficiency of the wafer and increase the diversity of device structures.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3A illustrates a state in which a process of depositing the first polycrystalline silicon 30 is completed. The process is described step by step as follows.

First, the first isolation insulating film 27 is formed on the top surface of the seed wafer 21 to have a predetermined thickness. Next, the second insulating insulating layer 29 is formed on the upper surface of the first insulating insulating layer 27, and the substrate contact 28 is etched using the substrate contact mask. Finally, the first polycrystalline silicon 30 is deposited and doped to the upper surface of the second isolation insulating layer 29 and the substrate contact 28.

At this time, the thickness of the SOI becomes a depth in which the first isolation insulating layer 27 penetrates the seed wafer 21, so care should be taken in adjusting the thickness of the first isolation insulating layer 27. In addition, the thickness of the first polycrystalline silicon 30 is determined according to the electrical characteristics of the structure to be formed. In particular, when the structure is applied as a connection line, it may be replaced with refractory metal, polycide, or silicide instead of the first polycrystalline silicon 30.

3b illustrates a state in which a process of forming an electrical structure is completed and described in stages.

First, after forming a fine pattern on the first polycrystalline silicon layer 30 to define the electrical structure 31, and then depositing the insulating insulating film 32 for the electrical structure, the second polycrystalline silicon to remove the surface irregularities The layer is subjected to the flattening operation by polishing to treat the mirror surface 34b.

In this case, the first polycrystalline silicon 30 and the second polycrystalline silicide 33 are doped with N-type or P-type impurities as necessary. In addition, as described above, the first polycrystalline silicon 30 may be replaced with another material according to an application.

FIG. 3c illustrates a state in which the seed wafer having completed the formation of the electrical structure of FIG. 3b is inverted and bonded to the handle wafer 36. The process will be described below. An insulating film 35 is formed on the handle wafer 36, the polycrystalline silicon mirror surface 34b of the seed wafer 21 is brought into contact with the insulating film 35, and then the two wafers 21 and 36 are bonded through a heat treatment process. Let's do it. In this case, the insulating layer 35 serves to electrically separate the second polycrystalline silicon layer 33 and the handle wafer 36 of the seed wafer. In some cases, the process of forming the insulating layer 35 is omitted to allow the handle wafer and the second polycrystalline silicon layer 33 to be electrically connected to each other, thereby providing an electrical potential to be applied to the second polycrystalline silicon layer 33. ) May be provided from the handle wafer.

When the above bonding process is completed, that is, the seed wafer 21 is subjected to mechanical and chemical polishing from the top surface of the seed wafer 21 to the point 38 where the first isolation insulating film 27 meets in the state shown in FIG. 3C. As described above, the SOI substrate having the silicon thin film thickness as much as the depth of the first isolation insulating film 27 penetrated into the seed wafer 21 can be manufactured as described in the process of depositing the first polycrystalline silicon.

3d illustrates a cross-sectional view of an SOI substrate having a buried structure. Although the initial surface of the seed wafer 21 was indicated by reference numeral 39, the second surface 40 of the silicon thin film on which the active element is to be formed is formed through the SDB process and the polishing process.

Through the fabrication process of the present invention, the seed wafer 21 and the handle wafer 36, which are previously formed of the structure 31, are bonded to each other, and the back surface of the seed wafer is polished and thinned to a P-SDB using a multilayer polycrystalline silicon layer. By implementing a new structure of the SOI substrate.

Compared with the prior art, the present invention can arrange elements more efficiently in the same area. Figure 4 shows the conceptual construction of such a densable form.

Figure 4a shows the arrangement of the structure according to the present invention. The structure 43 and the substrate contact 42 connecting the structure to the active region 41 are disposed to overlap each other in the active region 41.

FIG. 4B is a cross-sectional view of FIG. 4A showing that the SOI substrate, that is, the active region 41 and the structure 43 are vertically connected through the substrate contact 42.

The active regions 41 are separated from each other by the first insulating insulating layer 46. The active region 11 and the buried structure 43 are electrically connected to each other at the required position by forming the substrate contact 42 at the required position, but are electrically connected to each other by the second insulating insulating film 47 at other positions. Are isolated. In addition, the formed structure is electrically isolated using the third isolation insulating layer 45.

As can be seen from the layout (FIG. 4), the SOI structure according to the present invention can form elements having electrical characteristics, for example, capacitors, resistors, and connection lines, individually or in combination, in a buried layer. Since the arrangement is made perpendicular to the element to be formed 41), high density of the element is possible.

As the devices are arranged vertically, a three-dimensional device arrangement is possible, thereby realizing a new type of 3-Dimensional Integrated Circuit.

5 is a cross-sectional view showing a case in which the buried structure is a capacitor according to an embodiment of the present invention. The charge storage electrode 51 of the capacitor is vertically connected to the active regions 57a, 57b, 57c through the substrate contact 50, and the charge storage electrode 51 is disposed with the dielectric film 52 of the capacitor interposed therebetween. A polycrystalline silicon layer is formed below as the plate electrode 50 of the capacitor.

The manufacturing process sequence for this structure is as follows. First, in order to isolate between the active regions 57a, 57b, and 57c of the seed wafer, the first isolation insulating layers 48a, 48b, and 48c are formed by the L0COS method, and the active regions 57a, 57b, and 57c are OSIized. In order to form the second isolation insulating film 49a, 49b, and 49c, the substrate contact 50 is defined in the required portion. Next, after defining the polycrystalline silicon layer 51 for the charge storage electrode of the capacitor, the capacitor dielectric film 52 is formed, and the polycrystalline silicon layer 53 for the plate electrode is deposited thereon to a sufficient thickness.

After depositing the polycrystalline silicon layer for the plate electrode in this manner, the surface 54 is mirror-treated to bond the handle wafer 56 having the insulating film 55 to the surface. After the bonding process is completed, the seed wafer is chemically and mechanically polished to perform a thinning process of the seed wafer. The thinning of the seed wafer is stopped at the point where the first isolation insulating films 48a, 48b, and 49c appear, leaving a silicon thin film of a constant thickness as an active region.

After the active region is formed, the node contact 60 and the plate contact 59 are formed, and the plate electrode 61a and the node electrode 61b are formed using a metal film.

Through the above processes, a capacitor structure having a buried shape is formed. As a modification to the present embodiment, a bias may be directly applied through the handle wafer by bonding the polycrystalline silicon for plate electrode with the handle wafer on which the insulating film 55 is not formed. In addition, the polycrystalline silicon 51 for the charge storage electrode can be directly connected to a semiconductor device, that is, a MOSFET or a bipolar transistor, to be manufactured in an active region vertically connected through the substrate contact 50.

In addition, the capacitor of the present embodiment is a structure of a buried stack capacitor having a relatively thin thickness of the polycrystalline silicon (51) for the charge storage electrode as thousands of 수천, but the buried trench capacitor structure is the same as the manufacturing process It can manufacture by a method.

FIG. 6 is a cross-sectional view illustrating a case in which a buried structure is used as an interconnection or a resistor that electrically connects necessary portions of a semiconductor integrated circuit as another embodiment according to the present invention.

The active regions 62a, 62b, and 62c are separated from each other by the first isolation insulating layers 63a and 63b, and are doped with impurities to electrically connect the active region 62a and another active region 62c. The first polycrystalline silpiccon 66 is formed in a buried structure. In this case, the first polycrystalline silicon 66, which is used as an interconnector or a resistor, is electrically separated from the active region portions by the second isolation insulating film 64, and the portion of the substrate contact 65a where the connection is necessary. 65b) is electrically connected to the active area.

After the impurity is injected into the first polycrystalline silicon 66, a necessary pattern is defined as a connection line or a resistance, and then the third isolation insulating layer 67 and the second polycrystalline silicon 68 are formed. The surface of the second polycrystalline silicon 68 is mirror-polished and then adhered to the handle wafer 70 on which the insulating film 69 is formed. In this case, the back bias may be applied to the second polycrystalline silicon through the handle wafer by omitting the insulating layer 69.

After the substrate is bonded as described above, the seed wafer is thinned until the first isolation insulating layers 63a and 63b are met through chemical and mechanical polishing processes as described in FIG. 3. The contact films 72a and 72b are connected to the active regions 62a and 62c of the active regions 62a and 72c which are connected to the first polycrystalline silicon 66. After forming by using the () and by connecting to the conductors (73a) and the conductors (73b), respectively, the first polycrystalline silicon 66 is a buried structure to act as a connection line or a resistance.

As a modification to the present embodiment, the first polycrystalline silicon 66 used as a connection line or a resistor is a semiconductor cauterization to be manufactured in the active regions 62a and 62b electrically connected through the substrate contacts 65a and 65b. Direct connection to MOSFETs or bipolar transistors is also possible. In addition, by using a polycide (silcide) or silicide (silicide) thin film in place of the buried structure thin film it is possible to reduce the resistance of the connection line.

As can be seen from the above-described manufacturing method and the embodiment of the present invention, when fabricating an SOI substrate by bonding two silicon wafers, a capacitor, a connecting line or the like using a multilayer conductive thin film or insulating film on one wafer, that is, a seed wafer, A structure having electrical characteristics is embedded by forming a structure having electrical characteristics such as resistance in a single layer or a multilayer, or by forming a structure in which an individual or a combination of two or more kinds is formed, and then bonding it with another wafer, that is, a handle wafer. It is possible to manufacture new types of SOI substrates.

Using this type of new SOI substrate manufacturing technology, the efficiency of semiconductor chip area can be increased. In particular, when embedded structures are capacitors, memory cells of DRAM (Dynamic Random Access Memory) can be made smaller. It can be easily produced in the area.

Claims (10)

In the method of manufacturing a silicon on insulate (SOI) substrate using polycrystalline silicon, a first insulating insulating layer 27 is formed on the seed wafer 21 at a predetermined thickness, and a first insulating insulating layer 27 is formed on the top surface of the first insulating insulating layer 27. Forming a second insulating insulating film 29, defining a substrate contact 28, and depositing and doping the first polycrystalline silicon 30 on the upper surface of the substrate contact 28, and the first polycrystalline silicon. After forming a fine pattern on the layer 30 to define the electrical structure 31, the second process of growing or depositing the insulating insulating film 32 for the electrical structure 31, and after the second process is completed In order to deposit and do the second polycrystalline silicon layer 33 and to remove surface irregularities, a third process of polishing the second polycrystalline silicon layer 33 by mirror surface treatment, and the insulating film 35 on the handle wafer 36 ) And then the seed wafer 21 having the electrical structure 31 formed thereon. A fourth step of adhering the crystalline silicon mirror surface 34b and the insulating film 35 on the handle wafer 36 and the rear surface 21a of the seed wafer 21 in the bonded two wafers 21 and 36. And a fifth process of thinning the seed wafer 21 by chemical polishing or mechanical polishing until the first isolation insulating layer 27 appears from the buried structure. Semiconductor substrate manufacturing method. The method of manufacturing a semiconductor substrate with a structure having electrical properties according to claim 1, wherein an arbitrary structure is superimposed on a lower portion of the device formed in the active region (1). The insulating layer 27 for isolation between the active region 37 of the SOI substrate, and the insulating layer 29 for isolation between the active region 37 and the structure 31. A structure insulating film 32 is formed between the structure 31 and the second polycrystalline silicon 33, and an adhesive insulating film 35 is formed between the second polycrystalline silicon 33 and the handle wafer 36, respectively. A semiconductor substrate in which a structure having electrical characteristics is embedded, wherein the active region 37, the structure 31, the second polycrystalline silicon 33, and the handle wafer 36 are vertically and horizontally insulated from each other. Manufacturing method. The structure 37 of claim 1, wherein the structure 37 is buried by forming a capacitor dielectric layer 52 in the structure 31 and connecting the substrate contact 50, the node contact 60 and the plate contact 59. A method of manufacturing a semiconductor substrate in which a structure having electrical characteristics is embedded. The semiconductor with embedded structure having electrical characteristics according to claim 1, wherein the first polycrystalline silicon (66) having the geometric size and the impurity doping concentration is used as a resistance line between the elements. Substrate manufacturing method. 2. The semiconductor substrate of claim 1, wherein the first polycrystalline silicon 66 having the geometric size and the impurity concentration of the first polycrystalline silicon 30 is used as a connection line between the devices. Manufacturing method. 7. A method according to claim 5 or 6, wherein a structure having electrical properties is embedded in the semiconductor substrate, wherein polysilicon, silicide or heat-resistant metal is used instead of the first polycrystalline silicon (66). The method of manufacturing a semiconductor substrate with a structure having an electrical characteristic according to claim 5 or 6, wherein the resistance line and the connecting line are connected in a multi-layer to maximize the efficiency of the wiring line. After forming a structure 31 having any electrical characteristics using a conductive or resistive film on the front surface of the seed wafer 21, and again depositing a polycrystalline silicon layer 33 on the structure 31, the polycrystalline silicon layer 33 Surface 34a of the < RTI ID = 0.0 >) < / RTI > to bond the handle wafer 36 and the mirror surface 34b of the seed wafer 21 to any electrical properties between the seed wafer 21 and the handle wafer 36. A semiconductor substrate in which a structure having electrical characteristics is embedded, wherein the structure is inserted in a single layer or a multilayer. 10. The handle wafer and the second polycrystalline silicon of claim 9 are omitted by omitting the insulating films 35, 55 and 69 between the handle wafers 36, 56 and 70 and the second polycrystalline silicon 33, 53 and 68. A semiconductor substrate having a structure having electrical characteristics embedded therein, the electrical potential being provided from the handle wafer to be electrically connected to the second polycrystalline silicon.