JP2861120B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same.

[Prior art and problems] Conventionally, SOI (Silicon on Insula) formed on an insulator
tor) device is a device formed on a silicon substrate,
For example, when a power MOS transistor is integrated,
In some cases, the device formed in the SOI became unstable due to the fluctuation of the drain voltage during operation due to the substrate serving as the drain. Further, when fabricating a highly integrated device, it is necessary to reduce surface irregularities as much as possible, and it is essential to make the surface flat.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device in which an element is hardly affected by external elements and has a smooth surface.

[Means for Solving the Problems] The invention according to claim 1, wherein a first step of forming a groove near an element formation region on one main surface of a first single crystal semiconductor substrate, and the element formation region A second step of forming a conductive thin film disposed on the one main surface of the first single crystal semiconductor substrate over the bottom of the groove and the first single crystal formed by forming the groove; A third step of improving irregularities on the one main surface of the crystalline semiconductor substrate to improve its flatness, and the one main surface of the first single crystal semiconductor substrate having the improved flatness, and a flatness. A fourth main step of joining the one main surface of the second single-crystal semiconductor substrate, which has been secured, so as to sandwich the conductive thin film to form a bonded substrate; Reducing the thickness of the bonding substrate from the surface; A fifth step of forming a semiconductor element in the single-crystal semiconductor region, and a step of making electrical contact with the conductive thin film at a position corresponding to the bottom of the groove from the other main surface of the first single-crystal semiconductor substrate. The gist is a method for manufacturing a semiconductor device including six steps.

According to a second aspect of the present invention, in the first aspect, the groove in the first step is formed so as to surround a periphery of the element formation planned region.

According to a third aspect of the present invention, in the first or second aspect,
The gist is that the conductive thin film is a polycrystalline semiconductor thin film doped with impurities at a high concentration.

According to a fourth aspect of the present invention, in the first aspect, the third step includes flattening the one main surface of the first single crystal semiconductor substrate via the conductive thin film. The gist of the invention is to deposit a film and flatten the surface.

According to a fifth aspect of the present invention, in the method of any one of the first to fourth aspects, the second step includes forming an insulating film over the element formation planned region and a bottom of the groove. And the step of arranging the conductive thin film through the method.

[Operation] According to the invention of claim 1, in the first step, a groove is formed close to an element formation region on one main surface of the first single crystal semiconductor substrate, and in the second step, the element formation region is formed. The conductive thin film disposed on the top and the bottom of the groove is the first thin film.
Formed on the one main surface of the single crystal semiconductor substrate. or,
In the third step, the first step formed by forming the groove is formed.
The unevenness on the one main surface of the single crystal semiconductor substrate is improved,
Its flatness is improved. In the fourth step, the one main surface of the first single crystal semiconductor substrate having the improved flatness and the one main surface of the second single crystal semiconductor substrate having the ensured flatness are It is joined so as to sandwich the conductive thin film to form a joined substrate. In the subsequent step, the thickness of the bonding substrate is reduced from the other main surface of the first single crystal semiconductor substrate, and the fifth step allows a semiconductor element to be formed in the thinned single crystal semiconductor region in the element formation planned region. It is formed. In the sixth step, electrical contact can be made with the conductive thin film at a position corresponding to the bottom of the groove from the other main surface of the first single crystal semiconductor substrate.

According to a second aspect of the present invention, in the first aspect, the effect of the first aspect is realized by forming the groove in the first step so as to surround the periphery of the element formation planned region.

According to a third aspect of the present invention, in the first or second aspect,
The function of claim 1 or 2 is realized by making the conductive thin film a polycrystalline semiconductor thin film doped with impurities at a high concentration.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the third step is a step of forming a flattening film on the one main surface of the first single crystal semiconductor substrate via the conductive thin film. Is deposited and the surface thereof is planarized, thereby realizing the operation of any one of claims 1 to 3.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects, after the insulating film is formed over the element formation planned region and the bottom of the groove in the second step, the insulating film is formed. The operation of any one of claims 1 to 4 is realized by providing the step of arranging the conductive thin film through the intermediary.

First Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, a recess 2 having a depth of 0.5 to several μm is formed on a main surface of a silicon substrate 1 as a first single crystal semiconductor substrate by, for example, alkali etching. As this silicon substrate 1, an N-type (10 to 10Ω · cm)
0) The silicon substrate is used. Further, the recess 2
A groove 3 having a predetermined depth as a groove is formed in a silicon substrate 1 in a ring shape by dry etching or the like. Then, a silicon oxide film 4 as an insulating layer is formed on the entire surface of the silicon substrate 1 including the groove 3 by thermal oxidation or the like. Subsequently, a doped polysilicon film 5 serving as a conductive thin film doped with phosphorus or arsenic at a high concentration and functioning as an electric shield layer is formed on the entire surface of the silicon substrate 1 so as to fill the trench 3.

Next, as shown in FIG. 2, the doped polysilicon film 5 in other portions is removed except for the doped silicon film 5 in the concave portion 2 and the groove portion 3. Then, the main surface of the silicon substrate 1 is
The recess 2 is covered with a silicon oxide film 6 as an insulating layer by CVD so as to be filled, and densification at 800 to 1200 ° C. is performed. Subsequently, as shown in FIG. 3, the surface of the silicon substrate 1 is smoothed by mirror polishing until the silicon substrate 1 on the outer periphery of the concave portion 2 is exposed.

Next, as shown in FIG. 4, an N ⁺ -type silicon substrate 7 as a second single crystal semiconductor substrate having a thickness of 0.005 to 0.02 Ω · cm is provided with N ^−.
The epitaxial layer 8 is formed, and the surface of the epitaxial layer 8 is mirror-polished by a predetermined amount. This is because, at the time of epitaxial growth, a very small amount of a projection, which is considered to be caused by dust, scratches, etc., may be generated, which causes voids, etc. in the next wafer direct bonding. belongs to. Note that the epitaxial layer 8 is previously formed with an extra thickness corresponding to the polishing amount. Then, H ₂ O ₂ is deposited on the surface of the epitaxial layer 8 or the like.
After performing hydrophilic treatment with + H ₂ SO ₄ aqueous solution or the like, the epitaxial layer 8 and the main surface of the silicon substrate 1 are directly joined. That is, heat treatment is performed in nitrogen at 800 to 1200 ° C. for 30 minutes to 5 hours, and the two are bonded to obtain a bonded substrate.

Next, as shown in FIG. 5, the back surface of the silicon substrate 1 is thinned by rough polishing (lapping) to leave a thickness of about 10 to 20 μm, and then a silicon oxide film at the bottom of the groove 3 is formed by mechanical chemical polishing (selective polishing). Mirror polishing until 4 appears. In this manner, an element forming region separated by the silicon oxide films 4, 6 (insulator) is formed in a part of the silicon substrate 1, and a source, a drain, and a gate of the transistor are formed in the element forming region, respectively. Is done.

FIG. 6 shows an example of a semiconductor device having a transistor formed in this manner. This semiconductor device has an N-channel MOS transistor 9 and an N-channel power MOS transistor 10. The manufacture of this semiconductor device is performed as follows.

First, the P ⁺ guard ring region 11 and the P ⁺ region 12 of the N-channel power MOS transistor 10 and the P-well region 13 of the N-channel MOS transistor 9 are formed by boron ion implantation. After the formation of the gate oxide film 14 of 300 to 800 °, a polysilicon gate 15 is formed of phosphorus-doped polysilicon. Next, N-channel power MO
The P region 16 and the N ⁺ region 17 of the S transistor 10 are formed.
On the other hand, N-channel MOS transistor 9 has N ⁺ source region 1
8, N ⁺ drain region 19 is formed. Then, interlayer film 2
0, each electrode layer including the electrode layer 21a of the doped polysilicon film 5
A back electrode (drain electrode) 22 of the N-channel power MOS transistor 10 is formed. The electrode layer 21a electrically connected to the doped polysilicon film 5
Is applied with a predetermined voltage.

Thus, in this embodiment, the silicon substrate (first
A groove (groove) 3 is formed in the main surface (one main surface) of the single crystal semiconductor substrate 1 near the element formation planned region (first step), and the groove (groove) 3 is formed on the element formation planned region and the groove (groove) 3. Doped polysilicon film (conductive thin film) 5 disposed over the bottom
Is formed on a main surface (one main surface) of a silicon substrate (first single crystal semiconductor substrate) 1 (second step), and a silicon substrate (first single crystal semiconductor substrate) 1 formed by forming a groove is formed. The unevenness on the main surface (one main surface) is mirror-polished to improve its flatness (third step), and the main surface of the silicon substrate (first single crystal semiconductor substrate) 1 having the improved flatness (One main face)
And the surface (one main surface) of the epitaxial layer 8 of the silicon substrate (second single-crystal semiconductor substrate) 7 whose flatness has been ensured by mirror polishing, to form a doped silicon film (conductive thin film).
5 so as to sandwich them, and form a bonded substrate (fourth step), a silicon substrate (first single crystal semiconductor substrate) 1
The bonding substrate is thinned from the back surface (other main surface) of the semiconductor device, and N is added to the single-crystal semiconductor region in the thinned region where the element is to be formed.
A channel MOS transistor (semiconductor element) 9 is formed (fifth step) and doped at a position corresponding to the bottom of the groove (groove) 3 from the back surface (other main surface) of the silicon substrate (first single crystal semiconductor substrate) 1. Polysilicon film (conductive thin film)
5 and the electrode layer 21a were in electrical contact (sixth step).

In the N-channel MOS transistor 9, one of the silicon substrate (first single crystal semiconductor substrate) 1, which is disposed on the epitaxial layer 8 of the silicon substrate 7 and whose surface is smoothed, Area, a silicon oxide film 4, 6 (insulating film) including the bottom of the element formation area, and doped polysilicon surrounding the element formation area including the bottom of the element formation area. (Conductive thin film) 5. Therefore, the silicon oxide films 4, 6 (insulating film) and the doped polysilicon film around the region including the bottom of the device forming region in the silicon substrate (first single crystal semiconductor substrate) 1 whose surface is smoothed are formed. (Conductive thin film) 5, it is less susceptible to disturbance and is electrically stable. That is, N
The N-channel MOS transistor 9 is prevented from becoming unstable due to the fluctuation of the drain voltage of the channel MOS transistor 10.

Further, by applying a voltage to the doped polysilicon film 5, the potential of the substrate portion of the N-channel MOS transistor 9 can be further stabilized against the fluctuation of the drain voltage of the N-channel power MOS transistor 10.
In addition, the polishing of the silicon substrate 1 in the third step smoothes the silicon substrate 1, and the surface can be flattened when a highly integrated device is formed on the silicon substrate 1.

Further, in this embodiment, since the semiconductor layer (silicon substrate 1) which is to be an element formation region is formed by direct bonding of the wafer, it can be manufactured with excellent crystallinity and at low cost.

To explain an application example of this embodiment, as shown in FIG. 7, after the silicon oxide film 4 is formed, a region 23 where the silicon oxide film 4 is removed is formed in the concave portion 2 to form the silicon substrate 1 and the doped polycrystalline silicon. The silicon film 5 may be electrically connected. That is, the P-channel MOS transistor 2 in FIG.
As shown in FIG. 4, a P ⁺ source region 25 and a P ⁺ drain region 26 are formed, and a predetermined voltage is applied to the silicon substrate 1 from the electrode layer 21a through the removal region 23 of the silicon oxide film 4. As a result, by controlling the substrate potential of the P-channel MOS transistor 24, it is possible to stabilize against a kink phenomenon, a change in the threshold voltage VT, a leak current, and the like.

In addition, as shown in FIG. 8, a space 27 may be formed between the silicon oxide film 6 in the concave portion 2 of the silicon substrate 1 and the epitaxial layer 8 of the silicon substrate 7.

Further, as shown in FIG. 9 (a plan view of the transistor), the doped polysilicon film 5 may be formed widely to ensure electrical connection. Further, as shown in FIG. 10, after the silicon oxide film 4 is formed on the entire surface of the silicon substrate 1, for example, a part of the silicon oxide film 4 in the concave portion 2 and the groove portion 3 is removed by etching to remove arsenic ( As), a doped polysilicon film 5 doped at a high concentration is formed, and an NPN bipolar transistor 28 is formed as shown in FIG. Then, a so-called N ⁺ buried layer and a deep N ⁺ layer are formed by the As-doped polysilicon film 5 and the N ⁺ diffusion layer 29 formed by thermal diffusion from the film 5, and the collector resistance is reduced to increase the speed and speed. A high performance bipolar transistor can be obtained.

In the above embodiment, the power MOS transistor and the SOI
Although a MOS transistor, a bipolar transistor and the like are integrated, a high-performance semiconductor device using only the SOI portion may be used. In this case, for example, as shown in FIG. Polishing is performed so as to leave the entire surface, and thereafter, the wafers are joined. This bonding may be performed using softened glass or the like, or the silicon oxide film 6 may be bonded.
May be formed after forming polysilicon or the like on the surface, polishing and smoothing.

Further, the conductivity type of the semiconductor is such that the above-mentioned N-type is changed to P-type,
It is possible to form another device by replacing the mold with the N-type, and it is also possible to form the conductivity type of the doped polysilicon film 5 by combining the P-type, the N-type and both. .

Further, the surface of the silicon oxide film 6 in the concave portion 2 in FIG. 3 is partially removed at a predetermined depth, polysilicon is disposed in this portion, and the epitaxial layer 8 of the silicon substrate 7 is formed through the polysilicon. You may join directly. in this case,
As compared with the case where the silicon oxide film 6 is bonded to the epitaxial layer 8 of the silicon substrate 7, the bonding property is excellent.

Further, instead of polishing the back surface of the silicon substrate 1, the silicon oxide film 4 and the doped polysilicon film 5 in the groove 3 may be positioned near the surface by etching.

Furthermore, it is not always necessary to form the groove 3 defining the element formation area in an annular shape, and when forming an element formation area in the vicinity of the square silicon substrate 1, two sides or two sides of the square element formation area are formed. Grooves may be formed on three sides.

Second Embodiment Next, a second embodiment, which is an application example of the first embodiment, will be described.

As shown in FIG. 13, a groove portion 31 as a groove having a depth of 0.1 to several μm is formed on a silicon substrate 30 as a P-type (100) first single crystal semiconductor substrate of 1 to 50 Ω · cm by dry etching.
Is formed in an annular shape. The groove 31 may be formed by partially forming an oxide film by LOCOS and then removing the oxide film. In this embodiment, the description will be made on the assumption that the depth of the groove 31 is about 0.1 to 0.3 μm.

Next, as shown in FIG. 14, the entire surface of the silicon substrate 30
A thermal oxide film 32 as an insulating layer having a thickness of 0.01 to 1 μm is formed, and a doped polysilicon film 33 functioning as a conductive thin film doped with phosphorus at a high concentration and also functioning as an electric shield layer is formed at a thickness of 0.1 to 0.5 μm. A thickness of μm is formed. Then, as shown in FIG. 15, the doped polysilicon film 33 is divided and removed so as to be electrically separated by a predetermined pattern. Subsequently, a silicon oxide film 34 having a thickness of 0.5 to 1 μm is formed on the silicon substrate 30 by, for example, CVD.
Further, a polysilicon film 35 having a thickness of 3 to 5 μm is formed on the silicon oxide film 34.

Next, as shown in FIG. 16, the surface of the polysilicon film 35 is mirror-polished and flattened by lapping, polishing or the like. Then, a silicon substrate 36 as a second single crystal semiconductor substrate is bonded by direct wafer bonding. continue,
As shown in FIG. 17, the back surface of the silicon substrate 30 is polished by lapping, selective polishing, or the like. At this time, polishing of the silicon substrate 30 is stopped when the thermal oxide film 32 appears, and an SOI layer surrounded by the thermal oxide film 32 is formed.

Subsequently, as shown in FIG. 18, a MOS transistor is formed by a normal IC process. That is, a gate oxide film 37, a polysilicon gate 38, source / drain regions 39 formed by As ion implantation, an interlayer film 40 of BPSG, and an electrode layer 41 for establishing electrical connection with the doped polysilicon film 33.
Each electrode layer 41 including a and a passivation film 42 are formed.

Thus, also in this embodiment, as in the first embodiment,
By applying a voltage to the doped polysilicon 33 via the electrode layer 41a, the SOI layer can be electrically stabilized. Further, by making the thermal oxide film 32 approximately the same thickness as the gate oxide film 37, the current of the MOS transistor can be controlled at the same voltage as the gate voltage.

In addition, as an application example of this embodiment, the first embodiment
As shown in FIG. 10, the doped polysilicon film 33 and the silicon substrate 30 may be electrically connected. Further, in addition to the N-channel MOS transistor, a P-channel MOS transistor or a CMOS structure combining them may be used.

[Effects of the Invention] As described in detail above, according to the present invention, a conductive thin film can be easily buried and disposed under a SOI layer, and a structure for making electrical contact can be easily manufactured. it can. With this structure, it is possible to apply a predetermined voltage to the conductive thin film, whereby, for example, SOI
It also becomes easy to manufacture a semiconductor device capable of stabilizing the electrical layer, that is, a semiconductor device that is hardly affected by external potential.

[Brief description of the drawings]

1 to 12 are views for explaining the first embodiment, wherein FIG. 1 shows a manufacturing process, FIG. 2 shows a manufacturing process, and FIG. 3 shows a manufacturing process. FIG. 4, FIG. 4 shows a manufacturing process, FIG. 5 shows a manufacturing process, FIG. 6 shows a semiconductor device, FIG. 7 shows a manufacturing process, and FIG. 8 shows a manufacturing process. FIG. 9, FIG. 9 is a plan view of the semiconductor device, FIG. 10 is a view showing a manufacturing process, FIG. 11 is a view showing the semiconductor device, FIG.
FIGS. 13 to 18 are diagrams illustrating a manufacturing process, FIGS. 13 to 18 are diagrams for explaining the second embodiment, FIG. 13 is a diagram illustrating a manufacturing process, FIG. 14 is a diagram illustrating a manufacturing process, FIG. 15 is a diagram showing a manufacturing process, FIG. 16 is a diagram showing a manufacturing process, FIG. 17 is a diagram showing a manufacturing process, and FIG. 18 is a diagram showing a semiconductor device. 1 is a silicon substrate as a first semiconductor substrate, 3 is a trench, 4 is a silicon oxide film as an insulating layer, 5 is a doped polysilicon film as an electric shield layer, 6 is a silicon oxide film as an insulating layer, 7 is A silicon substrate as a second substrate, 9 is an N-channel MOS transistor.

Claims (5)

(57) [Claims] A first step of forming a groove close to an element formation region on one main surface of a first single crystal semiconductor substrate; and a step of forming a groove over the element formation region and a bottom of the groove. Forming a conductive thin film on the one main surface of the first single crystal semiconductor substrate, and forming irregularities on the one main surface of the first single crystal semiconductor substrate formed by forming the groove. A third step of improving the flatness of the first single crystal semiconductor substrate, the one main surface of the first single crystal semiconductor substrate having the improved flatness, and a second single crystal semiconductor substrate having the ensured flatness A fourth main step of bonding the first main surface of the first single crystal semiconductor substrate to another main surface of the first single crystal semiconductor substrate, and A semiconductor element in a single-crystal semiconductor region in the thinned element formation region; A fifth step of forming; and a sixth step of making electrical contact with the conductive thin film at a position corresponding to the bottom of the groove from the other main surface of the first single crystal semiconductor substrate. Manufacturing method of a semiconductor device. 2. The method according to claim 1, wherein said groove in said first step is formed so as to surround a periphery of said element formation planned region. 3. The semiconductor device according to claim 1, wherein said conductive thin film is a polycrystalline semiconductor thin film doped with impurities at a high concentration.
A method of manufacturing a semiconductor device according to claim 2. 4. The third step is a step of depositing a flattening film on the one main surface of the first single crystal semiconductor substrate via the conductive thin film and flattening the surface. 4. The method for manufacturing a semiconductor device according to claim 1, wherein: 5. The method according to claim 1, wherein the second step is a step of forming an insulating film over the region where the element is to be formed and the bottom of the groove, and then arranging the conductive thin film via the insulating film. The method for manufacturing a semiconductor device according to claim 1, wherein: