JPH0714000B2 - Composite semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a composite semiconductor device requiring element isolation and a method for manufacturing the same, and particularly to element isolation on a composite semiconductor substrate obtained by bonding a plurality of semiconductor substrates. The technology is effectively applied to enable high integration.

[Background Art of the Invention]

In an integrated circuit in which a plurality of functional elements are monolithically formed on a semiconductor substrate, a technique of using an insulating layer and a PN junction is known as a method of separating the functional elements. Fig. 8 shows an example of PN junction separation. That is, a P type semiconductor substrate (2)
Then, an N type vapor phase growth layer (3) is deposited on the substrate, and a P ⁺ type diffusion layer (1) is locally formed on the vapor phase growth layer (3) so as to reach the semiconductor substrate (2). To obtain an island region surrounded by PN junctions. By applying a reverse bias to the PN junction, this island region is electrically separated from other vapor phase growth layer portions.

On the other hand, FIG. 9 shows an example of insulator separation. I will omit the manufacturing method,
The plurality of N-type semiconductor regions are separated by the silicon oxide film (4) and the polycrystalline silicon layer (5) to form island regions.

[Problems of background technology]

The separation method by the PN junction is advantageous in that it is inexpensive, but it is unavoidable that lateral diffusion having the same dimension as the depth direction occurs at the time of forming the P ⁺ diffusion layer (1). There is a drawback that it increases. Further, in the PN junction isolation described above, a reverse bias is applied, but at this time, since it is necessary to ground the P ⁺ diffusion layer to increase the potential of the island region, the integrated circuit formed in this island region is electrically connected. It will come to mind.
Therefore, the bias circuit becomes complicated.

When a transistor having the semiconductor substrate (2) as a collector is formed in the vapor phase growth layer (3) surrounded by the PN junction, an emitter layer, a base layer and the P ⁺ diffusion layer (1) are formed.
Due to this, there is a drawback that a parasitic element is easily formed.

Next, the insulator isolation method has advantages that the bias circuit required for the PN junction isolation is not necessary and that there are few restrictions associated with parasitic elements. However, in this method, since the substrate is made of polycrystalline silicon, a very thick substrate is required, which is economically disadvantageous. It cannot be used as a passage.

[Object of the Invention]

The present invention provides a novel composite semiconductor device that overcomes the drawbacks of the element isolation method and a method for manufacturing the same, and particularly, to fill a composite semiconductor substrate obtained by integrating a plurality of semiconductor substrates by bonding with a filling material. Embedding, and thereby adjusting the distance between the exposed surface of the composite semiconductor substrate and the fill layer.

[Outline of Invention]

Applicant has applied the fact that both semiconductor substrates are joined by making the surfaces of multiple semiconductor substrates with different conductivity types or with different impurity concentrations contained as mirror surfaces and adhering them to each other in a clean air atmosphere. Has confirmed and applied for it first. Although this bonding technique has an advantage that the thickness of the semiconductor substrate can be adjusted, it cannot necessarily satisfy the drawbacks of the groove-type separation method which has recently been awarded as an element separation technique. That is, the so-called RIE (Reactive Ion) used for groove formation
In the Etching method, it takes a lot of time to increase the depth of the groove, and it is difficult to form the inner surface of the groove straight. In other words, it cannot be denied that the RIE method has its limits.

In the present invention, while maintaining the features of the bonding technique, a filling layer and an insulating layer are embedded in a part of the composite semiconductor substrate, and a separation layer connected to the filling layer and the insulating layer is exposed on the composite semiconductor substrate. The surface area is formed to form island regions. Then, there is a difference in thickness between the island region and the other portion of the adjacent composite semiconductor substrate, that is, the distance between the bonding layer and the exposed surface of the composite semiconductor. Therefore, a functional element having a large withstand voltage can be formed in a region having a large distance, a functional element having a small withstand voltage can be formed in the island region, and one semiconductor substrate on which the functional element is not formed is a high withstand voltage functional element. A composite semiconductor device that can be used as a current path is obtained.

Example of Invention

As shown in FIG. 1, a known photo-etching process is performed on one main surface of the N-type silicon semiconductor substrate (10) to form a recess (11) having a depth of about 80 μ, and then the recess including this recess is formed. When the thermal oxide film (12) is deposited on the semiconductor substrate (10), Fig. 1 is obtained,
Further, when a polycrystalline silicon layer (13) is laminated on the thermal oxide film so as to be thicker than the depth of the recess (11), the vertical sectional view of FIG. 2 is obtained. Next, the polycrystalline silicon layer is polished until the underlying N ⁻ type silicon semiconductor substrate (10) is exposed, and finally a mirror surface having a surface roughness of 500 Å or less is obtained. This structure is shown in the sectional view of FIG. On the other hand, an N ⁺ type silicon semiconductor substrate (14) is prepared, and a mirror surface having a surface roughness of 500Å or less is similarly formed on the main surface thereof by the mirror surface polishing step.

Depending on the surface state of these N ⁺ and N ⁻ type silicon semiconductor substrates, H ₂ O ₂ + H ₂ SO ₄ → HF → rare HF is used for degreasing and stains deposited on the semiconductor substrate surface. Remove the film. Then, it is washed with clean water for about several minutes, and dehydration treatment such as spinner treatment is carried out at room temperature. In this treatment step, the water supposed to be adsorbed on the mirror surface of the silicon semiconductor substrate is left as it is to remove excess water, and the adsorbed portion is almost volatilized.
Avoid heating and drying above 0 ° C. The silicon semiconductor substrate that has undergone these treatments is placed in a clean atmosphere of, for example, one class or less, and is adhered to and bonded to each other in a state in which foreign substances (dust) are not substantially present between the mirror surfaces thereof. A substrate (15) is formed. The composite silicon semiconductor substrate bonded in this manner is 200 ° C. or higher, preferably 1000 ° C. to 1
The heat treatment at 200 ° C. can increase the bonding strength.

Some polar groups are formed on the mirror surface of the N ⁺ and N ⁻ type silicon semiconductor substrates by the water washing treatment, and grain boundaries are formed by this bonding, which changes somewhat from the bulk structure of the silicon semiconductor. Then, it is assumed that both semiconductor substrates are integrated by the bonding layer to obtain a composite semiconductor substrate. It has already been verified that desired semiconductor device characteristics can be obtained when a functional device is produced using this composite semiconductor substrate. As shown in FIG. 4, the composite semiconductor substrate (15) has a bonding layer (16).
A polycrystalline silicon layer (13) and a thermal silicon oxide film (12) are formed adjacent to, and as a result, they are buried. In the future, this polycrystalline silicon layer will be called the filling layer, and the thermal silicon oxide film will be called the insulating layer. Due to the formation of the filling layer, the thickness of the composite semiconductor substrate, that is, the distance b connecting the bonding layer (16) and the exposed one surface of the composite semiconductor substrate, is set to the composite layer and the composite layer. This is larger than the distance a connecting the exposed one surface of the semiconductor substrate.

Next, element isolation technology is applied.

A plurality of grooves (17) having a width of 4 to 5 μ reaching the insulating layer (12) are formed by an RIE method on the exposed one surface portion of the composite semiconductor substrate having the distance b of 20 μ. A silicon oxide film (18) is deposited inside. Subsequently, a polycrystalline silicon layer (19) having a thickness of 4 to 5 μm is deposited in this groove to obtain a flat surface. Since this groove functions as a region for separating a specific portion of the composite semiconductor substrate, that is, a separation layer, it is hereinafter referred to as a separation layer.

The specific region of the composite semiconductor substrate is electrically insulated from the other regions of the other composite semiconductor substrate by the separation layer and the insulating layer (12), and becomes a so-called island region (20). Figure 6 shows
2 shows a cross-sectional structure of a composite semiconductor device (21) in which a functional element is formed on the composite semiconductor substrate.

In the island region (20), a control unit having an emitter (23), a base (24) and a collector (25) as a functional element (22) that does not require a high breakdown voltage is formed by a known method, and the distance b is A D-MOS type FET well known as a power element, that is, another functional element (26) is formed in the composite semiconductor substrate region.

An insulating layer (27) is formed on the exposed one surface of the composite semiconductor substrate to passivate the control unit.
n) It also functions as a membrane. On the other hand, the gate (28) of the D-MOS type FET is embedded in this insulator layer, and the source region (29) is formed so as to overlap the projected portion thereof. This source region forms a double impurity region (29, 30) by making full use of a known diffusion method or ion implantation method. A conductive layer (31) is formed on the other exposed surface of the composite semiconductor substrate to operate as a drain electrode of the D-MOS type FET.

Openings are selectively formed in the insulator layer (27) by a known photo-etching process, and a conductive material is deposited on the openings to form the emitter (23), base (24), collector (25), source. (2
9) and the electrodes of the gate (28) are formed to complete the composite semiconductor device (21) . In this device (21), the N ⁺ type silicon semiconductor substrate forming a part of the composite semiconductor substrate operates as a current path of the D-MOS type FET, that is, another functional element.

Polycrystalline silicon has been illustrated as an applicable material of the filling layer (13), but other insulating materials such as silicon oxide can also be applied.

Although an example in which the insulating layer method is adopted as the separation layer is shown, the PN junction separation method by the P ⁺ region can also be adopted.

Further, although a single island region is shown in FIG. 6, a plurality of the filler layers (13) are formed as shown in FIG. 7 according to the necessity of the functional element formed therein. Island regions having a difference in the distance a can be formed.

〔The invention's effect〕

In the composite semiconductor device according to the present invention, the silicon semiconductor substrates having different impurity concentrations are bonded and integrated as described above, but the desired semiconductor surface concentration must be maintained as compared with the case where the vapor phase growth method is adopted. And has the advantage that the thickness of the semiconductor substrate to be bonded can be adjusted, and is based on this precondition.

By the way, in the present application, by adopting the filling layer, it is possible to monolithically form functional elements having different withstand voltage characteristics on the same semiconductor substrate by making the thicknesses of the semiconductor regions different from each other. Is. When a power element is formed as this functional element, a part of the composite semiconductor substrate can be used as a current path thereof, which is convenient as a composite semiconductor device.

In forming the island region, some isolation technique is indispensable, but the distance of the silicon semiconductor region to be processed in which the groove formation or the PN junction is formed by the formation of the filling layer is different from the conventional method. Since it can be made smaller than the conventional one, the accuracy and cost of the processing means can be greatly improved.

The height of the filling layer is determined as the distance b-a required for the D-MOS type FET and the control unit.

[Brief description of drawings]

1 to 5 are cross-sectional views of each step of the present invention, FIG. 6 is a cross-sectional view of a composite semiconductor device, and FIG. 7 is a cross-sectional view of another embodiment of the present invention, FIGS. 8 and 9. FIG. 6 is a cross-sectional view showing conventional element isolation. 10 …… N ^- type silicon semiconductor substrate 14 …… N ⁺ type silicon semiconductor substrate 15 …… Composite semiconductor substrate 13 …… Filling layer 12 …… Insulating layer 17 …… Separating layer 16 …… Joining layer 22 …… Function Element 26 …… Other functional elements 21 …… Composite semiconductor device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-5544 (JP, A) JP-B 39-17869 (JP, B1) JP-B 52-28638 (JP, B2)

Claims (5)

[Claims] 1. A composite semiconductor substrate having a conductive bonding layer between mirror surfaces of a first semiconductor substrate and a mirror surface of a second semiconductor substrate, which face each other, and the first semiconductor substrate and the second semiconductor substrate adjacent to the bonding surface. A filler layer embedded in at least one of the above, and an insulator layer formed between at least one of the first semiconductor substrate and the second semiconductor substrate and the filler layer,
A plurality of separation layers formed between the insulating layer and the exposed surface portion of the composite semiconductor substrate, and a functional element formed on the composite semiconductor substrate surrounded by the separation layer and the insulating layer,
A composite semiconductor device comprising: another functional element formed outside the region where the functional element is provided. 2. A step of forming a recess in a part of one main surface of a first semiconductor substrate, forming an insulating film on at least the surface of the recess, and depositing a filling layer on the insulating film to form a recess in the recess. Filling step, mirroring one main surface of the semiconductor substrate including the surface of the filling layer, second semiconductor substrate having one mirrored main surface having adsorbed water in a clean atmosphere, and mirroring After bonding the two main surfaces of the first semiconductor substrate to each other, a heat treatment is performed to form a composite semiconductor substrate, and a separation layer having the insulating film as a bottom portion is formed in the first semiconductor substrate. A method of manufacturing a composite semiconductor device, comprising: a forming step; and a step of forming different functional elements in the separation layer and in regions of the first semiconductor substrate other than the separation layer. 3. The manufacture of a composite semiconductor device according to claim 2, wherein the surface roughness of one main surface of both the first and second semiconductor substrates, which is mirror-polished, is not more than 500Å. Method. 4. The method for manufacturing a composite semiconductor device according to claim 2, wherein the temperature of the heat treatment is 200 ° C. or higher. 5. The method for manufacturing a composite semiconductor device according to claim 2, wherein the heat treatment is performed at a temperature of 1000 ° C. to 1200 ° C.