FR2487125A1 - Procede de formation de zones etroites dans des circuits integres, notamment pour la formation de grilles, l'isolement de composants, la formation de regions dopees et la fabrication de transistors - Google Patents

Procede de formation de zones etroites dans des circuits integres, notamment pour la formation de grilles, l'isolement de composants, la formation de regions dopees et la fabrication de transistors Download PDF

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Publication number
FR2487125A1
FR2487125A1 FR8114109A FR8114109A FR2487125A1 FR 2487125 A1 FR2487125 A1 FR 2487125A1 FR 8114109 A FR8114109 A FR 8114109A FR 8114109 A FR8114109 A FR 8114109A FR 2487125 A1 FR2487125 A1 FR 2487125A1
Authority
FR
France
Prior art keywords
layer
forming
silicon
region
silica
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8114109A
Other languages
English (en)
French (fr)
Other versions
FR2487125B1 (enExample
Inventor
Dale Thomas Trenary
Allen Harland Frederick
Robert Michael Whelton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of FR2487125A1 publication Critical patent/FR2487125A1/fr
Application granted granted Critical
Publication of FR2487125B1 publication Critical patent/FR2487125B1/fr
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
FR8114109A 1980-07-21 1981-07-20 Procede de formation de zones etroites dans des circuits integres, notamment pour la formation de grilles, l'isolement de composants, la formation de regions dopees et la fabrication de transistors Granted FR2487125A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/170,833 US4318759A (en) 1980-07-21 1980-07-21 Retro-etch process for integrated circuits

Publications (2)

Publication Number Publication Date
FR2487125A1 true FR2487125A1 (fr) 1982-01-22
FR2487125B1 FR2487125B1 (enExample) 1984-04-20

Family

ID=22621451

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8114109A Granted FR2487125A1 (fr) 1980-07-21 1981-07-20 Procede de formation de zones etroites dans des circuits integres, notamment pour la formation de grilles, l'isolement de composants, la formation de regions dopees et la fabrication de transistors

Country Status (6)

Country Link
US (1) US4318759A (enExample)
JP (1) JPS5787136A (enExample)
DE (1) DE3128629A1 (enExample)
FR (1) FR2487125A1 (enExample)
GB (1) GB2081187B (enExample)
IT (1) IT1138064B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2496982A1 (fr) 1980-12-24 1982-06-25 Labo Electronique Physique Procede de fabrication de transistors a effet de champ, a grille auto-alignee, et transistors ainsi obtenus
US4546066A (en) * 1983-09-27 1985-10-08 International Business Machines Corporation Method for forming narrow images on semiconductor substrates
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US4906585A (en) * 1987-08-04 1990-03-06 Siemens Aktiengesellschaft Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches
DE3817326A1 (de) * 1988-05-20 1989-11-30 Siemens Ag Verfahren zur herstellung von gitterstrukturen mit um eine halbe gitterperiode gegeneinander versetzten abschnitten
DE3915650A1 (de) * 1989-05-12 1990-11-15 Siemens Ag Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht
EP0518418A1 (en) * 1991-06-10 1992-12-16 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device whereby field oxide regions are formed in a surface of a silicon body through oxidation
DE10052955A1 (de) * 2000-10-25 2002-06-06 Tesa Ag Verwendung von Haftklebemassen mit anisotropen Eigenschaften für Stanzprodukte
US7569883B2 (en) 2004-11-19 2009-08-04 Stmicroelectronics, S.R.L. Switching-controlled power MOS electronic device
ITMI20042243A1 (it) * 2004-11-19 2005-02-19 St Microelectronics Srl Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
FR2880471B1 (fr) * 2004-12-31 2007-03-09 Altis Semiconductor Snc Procede de nettoyage d'un semiconducteur
CN111696912B (zh) * 2019-03-12 2025-02-25 长鑫存储技术有限公司 半导体结构及其形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2312856A1 (fr) * 1975-05-27 1976-12-24 Fairchild Camera Instr Co Procede de gravure des bords et structure pour produire des ouvertures etroites aboutissant a la surface de matieres
FR2316733A1 (fr) * 1975-06-30 1977-01-28 Ibm Procede de fabrication de dispositifs a semi-conducteurs isoles dielectriquement
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1559608A (enExample) * 1967-06-30 1969-03-14
NL157662B (nl) * 1969-05-22 1978-08-15 Philips Nv Werkwijze voor het etsen van een oppervlak onder toepassing van een etsmasker, alsmede voorwerpen, verkregen door toepassing van deze werkwijze.
US3764865A (en) * 1970-03-17 1973-10-09 Rca Corp Semiconductor devices having closely spaced contacts
DE2139631C3 (de) * 1971-08-07 1979-05-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen eines Halbleiterbauelements, bei dem der Rand einer Diffusionszone auf den Rand einer polykristallinen Siliciumelektrode ausgerichtet ist
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
JPS5131186A (enExample) * 1974-09-11 1976-03-17 Hitachi Ltd
US4063992A (en) * 1975-05-27 1977-12-20 Fairchild Camera And Instrument Corporation Edge etch method for producing narrow openings to the surface of materials
US4040168A (en) * 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2312856A1 (fr) * 1975-05-27 1976-12-24 Fairchild Camera Instr Co Procede de gravure des bords et structure pour produire des ouvertures etroites aboutissant a la surface de matieres
FR2316733A1 (fr) * 1975-06-30 1977-01-28 Ibm Procede de fabrication de dispositifs a semi-conducteurs isoles dielectriquement
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap

Also Published As

Publication number Publication date
IT1138064B (it) 1986-09-10
GB2081187B (en) 1984-03-07
FR2487125B1 (enExample) 1984-04-20
GB2081187A (en) 1982-02-17
US4318759A (en) 1982-03-09
DE3128629A1 (de) 1982-06-09
JPS5787136A (en) 1982-05-31
IT8122944A0 (it) 1981-07-15

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