FR2443720A1 - Circuit logique de correction par arrondi pour multiplicateur utilisant l'algorithme de booth modifie - Google Patents

Circuit logique de correction par arrondi pour multiplicateur utilisant l'algorithme de booth modifie

Info

Publication number
FR2443720A1
FR2443720A1 FR7929908A FR7929908A FR2443720A1 FR 2443720 A1 FR2443720 A1 FR 2443720A1 FR 7929908 A FR7929908 A FR 7929908A FR 7929908 A FR7929908 A FR 7929908A FR 2443720 A1 FR2443720 A1 FR 2443720A1
Authority
FR
France
Prior art keywords
multiplier
logic circuit
correction logic
rounding
booth algorithm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7929908A
Other languages
English (en)
Other versions
FR2443720B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Publication of FR2443720A1 publication Critical patent/FR2443720A1/fr
Application granted granted Critical
Publication of FR2443720B1 publication Critical patent/FR2443720B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Le circuit logique de correction 42 par arrondi selon l'invention est intégré à un multiplicateur numérique binaire 10 à arithmétique à virgule flottante qui utilise un algorithme de Booth modifié pour former un produit final de chiffres binaires. Le circuit logique de correction par arrondi est appliqué, dans le multiplicateur, de façon à arrondir le produit final de celui-ci à un chiffre pré-établi, sans que ce multiplicateur ait à calculer de chiffres binaires moins significatifs à droite du chiffre binaire pré-établi. Les circuits du multiplicateur qui étaient antérieurement nécessaires pour former un produit final non arrondi avant l'opération d'arrondi sont supprimés sans que l'arrondi devienne moins précis.
FR7929908A 1978-12-06 1979-12-05 Circuit logique de correction par arrondi pour multiplicateur utilisant l'algorithme de booth modifie Expired FR2443720B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/966,870 US4229800A (en) 1978-12-06 1978-12-06 Round off correction logic for modified Booth's algorithm

Publications (2)

Publication Number Publication Date
FR2443720A1 true FR2443720A1 (fr) 1980-07-04
FR2443720B1 FR2443720B1 (fr) 1986-03-21

Family

ID=25511970

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7929908A Expired FR2443720B1 (fr) 1978-12-06 1979-12-05 Circuit logique de correction par arrondi pour multiplicateur utilisant l'algorithme de booth modifie

Country Status (8)

Country Link
US (1) US4229800A (fr)
JP (1) JPS588009B2 (fr)
CA (1) CA1119728A (fr)
DE (1) DE2946846A1 (fr)
FR (1) FR2443720B1 (fr)
GB (1) GB2039393B (fr)
IT (1) IT1192787B (fr)
NL (1) NL7908032A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0103722A2 (fr) * 1982-09-16 1984-03-28 Kabushiki Kaisha Toshiba Circuit de multiplication
EP0255696A2 (fr) * 1986-08-04 1988-02-10 Anton Steinecker Maschinenfabrik GmbH Procédé et matériau filtrant pour la filtration à précouche de boissons
EP0297989A2 (fr) * 1987-06-30 1989-01-04 Digital Equipment Corporation Dispositif et méthode pour accélérer la procédure de multiplication entière ou à virgule flottante

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4405992A (en) * 1981-04-23 1983-09-20 Data General Corporation Arithmetic unit for use in data processing systems
DE3144015A1 (de) * 1981-11-05 1983-05-26 Ulrich Prof. Dr. 7500 Karlsruhe Kulisch "schaltungsanordnung und verfahren zur bildung von skalarprodukten und summen von gleitkommazahlen mit maximaler genauigkeit"
US4547862A (en) * 1982-01-11 1985-10-15 Trw Inc. Monolithic fast fourier transform circuit
US4507676A (en) * 1982-10-28 1985-03-26 Rca Corporation Digital matrixing system
DE3309717A1 (de) * 1983-03-18 1984-09-20 Robert Bosch Gmbh, 7000 Stuttgart Multiplizierschaltung
JPS61165128A (ja) * 1984-12-14 1986-07-25 Fujitsu Ltd 多入力加減算装置
US4727506A (en) * 1985-03-25 1988-02-23 Rca Corporation Digital scaling circuitry with truncation offset compensation
JPS6285333A (ja) * 1985-10-11 1987-04-18 Oki Electric Ind Co Ltd 浮動小数点乗算器丸め処理方式
JPS62120535A (ja) * 1985-11-20 1987-06-01 Oki Electric Ind Co Ltd 並列乗算器
US4887232A (en) * 1987-05-15 1989-12-12 Digital Equipment Corporation Apparatus and method for performing a shift operation in a multiplier array circuit
US5463575A (en) * 1994-06-24 1995-10-31 Rockwell International Corporation Reduced quantization noise from single-precision multiplier
US5729485A (en) * 1995-09-11 1998-03-17 Digital Equipment Corporation Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array
US5726927A (en) * 1995-09-11 1998-03-10 Digital Equipment Corporation Multiply pipe round adder
JPH10133856A (ja) * 1996-10-31 1998-05-22 Nec Corp 丸め機能付き乗算方法及び乗算器
JP3417286B2 (ja) 1998-02-23 2003-06-16 株式会社デンソー 乗算器
US6684236B1 (en) * 2000-02-15 2004-01-27 Conexant Systems, Inc. System of and method for efficiently performing computations through extended booth encoding of the operands thereto
US6898614B2 (en) * 2001-03-29 2005-05-24 Koninklijke Philips Electronics N.V. Round-off algorithm without bias for 2's complement data
US9450601B1 (en) 2015-04-02 2016-09-20 Microsoft Technology Licensing, Llc Continuous rounding of differing bit lengths
EP3471271A1 (fr) * 2017-10-16 2019-04-17 Acoustical Beauty Convolutions améliorées de signaux numériques utilisant une optimisation des exigences de bits d'un signal numérique cible

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947670A (en) * 1974-11-22 1976-03-30 General Electric Company Signed multiplication logic
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3290493A (en) * 1965-04-01 1966-12-06 North American Aviation Inc Truncated parallel multiplication
US3878985A (en) * 1973-11-30 1975-04-22 Advanced Micro Devices Inc Serial-parallel multiplier using booth{3 s algorithm with combined carry-borrow feature
US3885141A (en) * 1974-02-06 1975-05-20 Bell Telephone Labor Inc Modular pipeline multiplier to generate a rounded product

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947670A (en) * 1974-11-22 1976-03-30 General Electric Company Signed multiplication logic
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0103722A2 (fr) * 1982-09-16 1984-03-28 Kabushiki Kaisha Toshiba Circuit de multiplication
EP0103722A3 (fr) * 1982-09-16 1986-08-27 Kabushiki Kaisha Toshiba Circuit de multiplication
EP0255696A2 (fr) * 1986-08-04 1988-02-10 Anton Steinecker Maschinenfabrik GmbH Procédé et matériau filtrant pour la filtration à précouche de boissons
EP0255696A3 (fr) * 1986-08-04 1988-10-05 Anton Steinecker Maschinenfabrik GmbH Procédé et matériau filtrant pour la filtration à précouche de boissons
EP0297989A2 (fr) * 1987-06-30 1989-01-04 Digital Equipment Corporation Dispositif et méthode pour accélérer la procédure de multiplication entière ou à virgule flottante
EP0297989A3 (fr) * 1987-06-30 1989-12-27 Digital Equipment Corporation Dispositif et méthode pour accélérer la procédure de multiplication entière ou à virgule flottante

Also Published As

Publication number Publication date
IT1192787B (it) 1988-05-04
GB2039393B (en) 1983-04-13
CA1119728A (fr) 1982-03-09
US4229800A (en) 1980-10-21
DE2946846A1 (de) 1980-06-19
GB2039393A (en) 1980-08-06
IT7969339A0 (it) 1979-12-05
JPS588009B2 (ja) 1983-02-14
NL7908032A (nl) 1980-06-10
FR2443720B1 (fr) 1986-03-21
JPS5582354A (en) 1980-06-21

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