IT7969339A0 - Binari utilizzanti l algoritmo di circuito logico correttore arrotonbooth modificato datore per moltiplicatori digitali - Google Patents

Binari utilizzanti l algoritmo di circuito logico correttore arrotonbooth modificato datore per moltiplicatori digitali

Info

Publication number
IT7969339A0
IT7969339A0 IT7969339A IT6933979A IT7969339A0 IT 7969339 A0 IT7969339 A0 IT 7969339A0 IT 7969339 A IT7969339 A IT 7969339A IT 6933979 A IT6933979 A IT 6933979A IT 7969339 A0 IT7969339 A0 IT 7969339A0
Authority
IT
Italy
Prior art keywords
arrotonbooth
binaries
logic circuit
digital multipliers
corrector device
Prior art date
Application number
IT7969339A
Other languages
English (en)
Other versions
IT1192787B (it
Inventor
Gregorian Roubik
Reddy Kadiri
Original Assignee
American Micro Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Micro Syst filed Critical American Micro Syst
Publication of IT7969339A0 publication Critical patent/IT7969339A0/it
Application granted granted Critical
Publication of IT1192787B publication Critical patent/IT1192787B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
IT69339/79A 1978-12-06 1979-12-05 Circuito logico correttore arroton datore per loltiplicatori digitali binari utilizzanti l algoritmo di booth modificato IT1192787B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/966,870 US4229800A (en) 1978-12-06 1978-12-06 Round off correction logic for modified Booth's algorithm

Publications (2)

Publication Number Publication Date
IT7969339A0 true IT7969339A0 (it) 1979-12-05
IT1192787B IT1192787B (it) 1988-05-04

Family

ID=25511970

Family Applications (1)

Application Number Title Priority Date Filing Date
IT69339/79A IT1192787B (it) 1978-12-06 1979-12-05 Circuito logico correttore arroton datore per loltiplicatori digitali binari utilizzanti l algoritmo di booth modificato

Country Status (8)

Country Link
US (1) US4229800A (it)
JP (1) JPS588009B2 (it)
CA (1) CA1119728A (it)
DE (1) DE2946846A1 (it)
FR (1) FR2443720B1 (it)
GB (1) GB2039393B (it)
IT (1) IT1192787B (it)
NL (1) NL7908032A (it)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4405992A (en) * 1981-04-23 1983-09-20 Data General Corporation Arithmetic unit for use in data processing systems
DE3144015A1 (de) * 1981-11-05 1983-05-26 Ulrich Prof. Dr. 7500 Karlsruhe Kulisch "schaltungsanordnung und verfahren zur bildung von skalarprodukten und summen von gleitkommazahlen mit maximaler genauigkeit"
US4547862A (en) * 1982-01-11 1985-10-15 Trw Inc. Monolithic fast fourier transform circuit
JPS5949640A (ja) * 1982-09-16 1984-03-22 Toshiba Corp 乗算回路
US4507676A (en) * 1982-10-28 1985-03-26 Rca Corporation Digital matrixing system
DE3309717A1 (de) * 1983-03-18 1984-09-20 Robert Bosch Gmbh, 7000 Stuttgart Multiplizierschaltung
JPS61165128A (ja) * 1984-12-14 1986-07-25 Fujitsu Ltd 多入力加減算装置
US4727506A (en) * 1985-03-25 1988-02-23 Rca Corporation Digital scaling circuitry with truncation offset compensation
JPS6285333A (ja) * 1985-10-11 1987-04-18 Oki Electric Ind Co Ltd 浮動小数点乗算器丸め処理方式
JPS62120535A (ja) * 1985-11-20 1987-06-01 Oki Electric Ind Co Ltd 並列乗算器
DE3626378A1 (de) * 1986-08-04 1988-02-11 Steinecker Maschf Anton Verfahren und filtermaterial zur anschwemmfiltration von getraenken
US4887232A (en) * 1987-05-15 1989-12-12 Digital Equipment Corporation Apparatus and method for performing a shift operation in a multiplier array circuit
US4862405A (en) * 1987-06-30 1989-08-29 Digital Equipment Corporation Apparatus and method for expediting subtraction procedures in a carry/save adder multiplication unit
US5463575A (en) * 1994-06-24 1995-10-31 Rockwell International Corporation Reduced quantization noise from single-precision multiplier
US5729485A (en) * 1995-09-11 1998-03-17 Digital Equipment Corporation Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array
US5726927A (en) * 1995-09-11 1998-03-10 Digital Equipment Corporation Multiply pipe round adder
JPH10133856A (ja) * 1996-10-31 1998-05-22 Nec Corp 丸め機能付き乗算方法及び乗算器
JP3417286B2 (ja) 1998-02-23 2003-06-16 株式会社デンソー 乗算器
US6684236B1 (en) * 2000-02-15 2004-01-27 Conexant Systems, Inc. System of and method for efficiently performing computations through extended booth encoding of the operands thereto
US6898614B2 (en) * 2001-03-29 2005-05-24 Koninklijke Philips Electronics N.V. Round-off algorithm without bias for 2's complement data
US9450601B1 (en) 2015-04-02 2016-09-20 Microsoft Technology Licensing, Llc Continuous rounding of differing bit lengths
EP3471271A1 (en) * 2017-10-16 2019-04-17 Acoustical Beauty Improved convolutions of digital signals using a bit requirement optimization of a target digital signal

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3290493A (en) * 1965-04-01 1966-12-06 North American Aviation Inc Truncated parallel multiplication
US3878985A (en) * 1973-11-30 1975-04-22 Advanced Micro Devices Inc Serial-parallel multiplier using booth{3 s algorithm with combined carry-borrow feature
US3885141A (en) * 1974-02-06 1975-05-20 Bell Telephone Labor Inc Modular pipeline multiplier to generate a rounded product
US3947670A (en) * 1974-11-22 1976-03-30 General Electric Company Signed multiplication logic
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier

Also Published As

Publication number Publication date
DE2946846A1 (de) 1980-06-19
GB2039393B (en) 1983-04-13
GB2039393A (en) 1980-08-06
FR2443720B1 (fr) 1986-03-21
JPS588009B2 (ja) 1983-02-14
CA1119728A (en) 1982-03-09
US4229800A (en) 1980-10-21
FR2443720A1 (fr) 1980-07-04
NL7908032A (nl) 1980-06-10
IT1192787B (it) 1988-05-04
JPS5582354A (en) 1980-06-21

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