FR2382805A1 - Circuit logique realise suivant la technique des circuits integres mos - Google Patents

Circuit logique realise suivant la technique des circuits integres mos

Info

Publication number
FR2382805A1
FR2382805A1 FR7820821A FR7820821A FR2382805A1 FR 2382805 A1 FR2382805 A1 FR 2382805A1 FR 7820821 A FR7820821 A FR 7820821A FR 7820821 A FR7820821 A FR 7820821A FR 2382805 A1 FR2382805 A1 FR 2382805A1
Authority
FR
France
Prior art keywords
mos integrated
integrated circuits
technique
logic circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7820821A
Other languages
English (en)
Other versions
FR2382805B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2382805A1 publication Critical patent/FR2382805A1/fr
Application granted granted Critical
Publication of FR2382805B1 publication Critical patent/FR2382805B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/16—Circuits for carrying over pulses between successive decades
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/56—Reversible counters

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un circuit logique réalisé suivant la technique des circuits intégrés MOS. Ce circuit, destiné à effectuer les opérations sur des chiffres binaires, comporte des portes logiques pour produire et transmettre des signaux de report entre les différents étages du circuit, lesdites portes de transmission des signaux de report étant réalisées sous la forme de portes de transfert. Application notamment aux circuits intégrés MOS constituant des additionneurs complets, des comparateurs et des compteurs binaires synchrones.
FR787820821A 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos Expired FR2382805B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19762647982 DE2647982A1 (de) 1976-10-22 1976-10-22 Logische schaltungsanordnung in integrierter mos-schaltkreistechnik

Publications (2)

Publication Number Publication Date
FR2382805A1 true FR2382805A1 (fr) 1978-09-29
FR2382805B1 FR2382805B1 (fr) 1989-02-24

Family

ID=5991178

Family Applications (5)

Application Number Title Priority Date Filing Date
FR7731285A Pending FR2382802A1 (fr) 1976-10-22 1977-10-18 Circuit logique realise suivant la technique des circuits integres mos
FR787820821A Expired FR2382805B1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos
FR7820819A Granted FR2382803A1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos
FR7820822A Granted FR2382806A1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos
FR7820820A Granted FR2382804A1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos

Family Applications Before (1)

Application Number Title Priority Date Filing Date
FR7731285A Pending FR2382802A1 (fr) 1976-10-22 1977-10-18 Circuit logique realise suivant la technique des circuits integres mos

Family Applications After (3)

Application Number Title Priority Date Filing Date
FR7820819A Granted FR2382803A1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos
FR7820822A Granted FR2382806A1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos
FR7820820A Granted FR2382804A1 (fr) 1976-10-22 1978-07-12 Circuit logique realise suivant la technique des circuits integres mos

Country Status (5)

Country Link
US (2) US4323982A (fr)
JP (3) JPS5353236A (fr)
DE (2) DE2647982A1 (fr)
FR (5) FR2382802A1 (fr)
GB (3) GB1595229A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2573316A1 (fr) * 1984-11-22 1986-05-23 Bensch Kurt Cordage de raquette, notamment de raquette de tennis

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3035631A1 (de) * 1980-09-20 1982-05-06 Deutsche Itt Industries Gmbh, 7800 Freiburg Binaerer mos-paralleladdierer
DE3036065A1 (de) * 1980-09-25 1982-05-06 Deutsche Itt Industries Gmbh, 7800 Freiburg Binaere mos-parallel-komparatoren
FR2505065A1 (fr) * 1981-04-29 1982-11-05 Labo Cent Telecommunicat Cellule d'additionneur binaire a propagation rapide de la retenue et additionneur utilisant de telles cellules
US4439835A (en) * 1981-07-14 1984-03-27 Rockwell International Corporation Apparatus for and method of generation of ripple carry signals in conjunction with logical adding circuitry
US4471455A (en) * 1982-02-04 1984-09-11 Dshkhunian Valery Carry-forming unit
EP0098692A3 (fr) * 1982-07-01 1986-04-16 Hewlett-Packard Company Dispositif d'addition d'un premier et d'un second opérandes binaires
US4523292A (en) * 1982-09-30 1985-06-11 Rca Corporation Complementary FET ripple carry binary adder circuit
US4572506A (en) * 1983-06-03 1986-02-25 Commodore Business Machines Raster line comparator circuit for video game
US4584660A (en) * 1983-06-22 1986-04-22 Harris Corporation Reduction of series propagation delay and impedance
DE3323607A1 (de) * 1983-06-30 1985-01-03 Siemens AG, 1000 Berlin und 8000 München Digitales rechenwerk
JPS61211735A (ja) * 1985-03-18 1986-09-19 Nec Corp 比較回路
FR2583182B1 (fr) * 1985-06-11 1987-08-07 Efcis Additionneur a propagation de retenue avec precharge
JPS6270935A (ja) * 1985-09-24 1987-04-01 Sharp Corp デイジタル加算器
JPH07120261B2 (ja) * 1986-03-20 1995-12-20 株式会社東芝 デジタル比較回路
US4755696A (en) * 1987-06-25 1988-07-05 Delco Electronics Corporation CMOS binary threshold comparator
US4797650A (en) * 1987-06-25 1989-01-10 Delco Electronics Corporation CMOS binary equals comparator with carry in and out
JPH03175530A (ja) * 1989-12-04 1991-07-30 Nec Corp 論理回路
US5282234A (en) * 1990-05-18 1994-01-25 Fuji Photo Film Co., Ltd. Bi-directional shift register useful as scanning registers for active matrix displays and solid state image pick-up devices
JPH07200257A (ja) * 1993-12-28 1995-08-04 Nec Corp Ｎｍｏｓパストランジスタ回路と加算器
US6292093B1 (en) * 2000-02-22 2001-09-18 Hewlett Packard Company Multi-bit comparator
US8118748B2 (en) * 2005-04-28 2012-02-21 Medtronic, Inc. Implantable capacitive pressure sensor system and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3151252A (en) * 1959-12-28 1964-09-29 Ibm Bidirectional decade counter

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2823476A (en) 1952-04-23 1958-02-18 Bendix Aviat Corp Illuminated devices
US3183369A (en) * 1961-08-16 1965-05-11 Westinghouse Electric Corp Reversible counter operative to count either binary or binary coded decimal number system
US3588475A (en) * 1969-03-21 1971-06-28 Us Navy Forward-backward digital counter circuit
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
GB1468342A (en) * 1973-01-28 1977-03-23 Hawker Siddeley Dynamics Ld Adder or priority-determining circuits for computers
US3843876A (en) * 1973-09-20 1974-10-22 Motorola Inc Electronic digital adder having a high speed carry propagation line
DE2425602A1 (de) * 1974-05-27 1975-12-11 Siemens Ag Vergleicherschaltung fuer zwei nstellige binaerworte, insbesondere dualzahlen
US3943378A (en) 1974-08-01 1976-03-09 Motorola, Inc. CMOS synchronous binary counter
JPS5227348A (en) * 1975-08-27 1977-03-01 Hitachi Ltd Counter
JPS5841533B2 (ja) * 1975-10-31 1983-09-13 日本電気株式会社 ゼンカゲンサンカイロ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3151252A (en) * 1959-12-28 1964-09-29 Ibm Bidirectional decade counter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SIEMENS RESEARCH AND DEVELOPMENT REPORTS, vol. 5, no. 6, juin 1976, pages 324-326, Springer Verlag, Berlin, DE; D. EICHRODT: "Rewarding-application of transmission gates in MOS-LSI circuits" *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2573316A1 (fr) * 1984-11-22 1986-05-23 Bensch Kurt Cordage de raquette, notamment de raquette de tennis

Also Published As

Publication number Publication date
JPS5353236A (en) 1978-05-15
JPS6114533B2 (fr) 1986-04-19
GB1595229A (en) 1981-08-12
FR2382804A1 (fr) 1978-09-29
DE2660843C2 (de) 1984-05-30
FR2382804B1 (fr) 1984-04-20
JPS6134296B2 (fr) 1986-08-07
FR2382806B1 (fr) 1985-01-18
FR2382805B1 (fr) 1989-02-24
JPS631779B2 (fr) 1988-01-14
FR2382802A1 (fr) 1978-09-29
JPS60247329A (ja) 1985-12-07
GB1595228A (en) 1981-08-12
JPS60243739A (ja) 1985-12-03
DE2647982A1 (de) 1978-04-27
FR2382803B1 (fr) 1982-10-01
FR2382806A1 (fr) 1978-09-29
US4433372A (en) 1984-02-21
US4323982A (en) 1982-04-06
GB1595230A (en) 1981-08-12
FR2382803A1 (fr) 1978-09-29

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Legal Events

Date Code Title Description
ST Notification of lapse
AR Application made for restoration
BR Restoration of rights
ST Notification of lapse