GB1468342A - Adder or priority-determining circuits for computers - Google Patents

Abstract

1468342 Adder and priority circuits HAWKER SIDDELEY DYNAMICS Ltd 5 March 1974 [28 Jan 1973] 44763/72 Heading G4A In a multistage binary parallel adder or priority resolving network each stage includes a complementary metal oxide semi-conductor (CMOS) transmission gate to propagate a signal rapidly to the succeeding stage. Adder.-A three stage complementing adder is shown, Fig. 1. CMOS gate 108 transmits the stage carry input to the carry output when the bit inputs to the stage (x, y) differ and CMOS gate 107 transmits an internally generated carry by the NAND of the bit inputs when these inputs are the same. Further CMOS gates 113, 114 generate SUM from the true and inverse carry inputs to the stage, formed by inverters 14, 15, in accordance with whether the stage bit inputs are the same or different, the equivalence, non- equivalence, and NAND outputs 104-106 being generated by CMOS logic 103 (not described). The Specification states that the carry propagating CMOS gates may be provided to transmit "block carry" signals between blocks in a block carry adder. Priority circuit.-Respective flip-flops produce Q=1 outputs when their request inputs are set. A CMOS gate 108, Fig. 3, in each stage propagates a logic "1" input 109 to the next stage unless Q = 1 in the stage whereupon logic "0" is propagated by CMOS gate 107. Whenever logic "0" is propagated, logic "0" is propagated to all succeeding stages. Each stage output is the AND combination of the propagated input to the stage and the stage Q output so that only the highest priority set request input results in a logic "1" output.