FR2215654B3 - - Google Patents
Info
- Publication number
- FR2215654B3 FR2215654B3 FR7402479A FR7402479A FR2215654B3 FR 2215654 B3 FR2215654 B3 FR 2215654B3 FR 7402479 A FR7402479 A FR 7402479A FR 7402479 A FR7402479 A FR 7402479A FR 2215654 B3 FR2215654 B3 FR 2215654B3
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4476372A GB1468342A (en) | 1973-01-28 | 1973-01-28 | Adder or priority-determining circuits for computers |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2215654A1 FR2215654A1 (en) | 1974-08-23 |
FR2215654B3 true FR2215654B3 (en) | 1976-11-19 |
Family
ID=10434644
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7402479A Expired FR2215654B3 (en) | 1973-01-28 | 1974-01-25 |
Country Status (4)
Country | Link |
---|---|
DE (1) | DE2404145A1 (en) |
FR (1) | FR2215654B3 (en) |
GB (1) | GB1468342A (en) |
NL (1) | NL7401039A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2647982A1 (en) * | 1976-10-22 | 1978-04-27 | Siemens Ag | LOGICAL CIRCUIT ARRANGEMENT IN INTEGRATED MOS CIRCUIT TECHNOLOGY |
US4254471A (en) * | 1978-04-25 | 1981-03-03 | International Computers Limited | Binary adder circuit |
DE3035631A1 (en) * | 1980-09-20 | 1982-05-06 | Deutsche Itt Industries Gmbh, 7800 Freiburg | BINARY MOS PARALLEL ADDER |
-
1973
- 1973-01-28 GB GB4476372A patent/GB1468342A/en not_active Expired
-
1974
- 1974-01-25 FR FR7402479A patent/FR2215654B3/fr not_active Expired
- 1974-01-25 NL NL7401039A patent/NL7401039A/xx unknown
- 1974-01-26 DE DE19742404145 patent/DE2404145A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
FR2215654A1 (en) | 1974-08-23 |
GB1468342A (en) | 1977-03-23 |
DE2404145A1 (en) | 1974-09-05 |
NL7401039A (en) | 1974-07-30 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |