FR2344093A1 - Systeme de gestion coherente d'une hierarchie de memoires - Google Patents

Systeme de gestion coherente d'une hierarchie de memoires

Info

Publication number
FR2344093A1
FR2344093A1 FR7606877A FR7606877A FR2344093A1 FR 2344093 A1 FR2344093 A1 FR 2344093A1 FR 7606877 A FR7606877 A FR 7606877A FR 7606877 A FR7606877 A FR 7606877A FR 2344093 A1 FR2344093 A1 FR 2344093A1
Authority
FR
France
Prior art keywords
level
operating system
data transfer
coherent data
set operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7606877A
Other languages
English (en)
French (fr)
Other versions
FR2344093B1 (enExample
Inventor
Alice Maria Recoque
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INFORMATIQUE CIE INTERNATIONALE
Original Assignee
INFORMATIQUE CIE INTERNATIONALE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INFORMATIQUE CIE INTERNATIONALE filed Critical INFORMATIQUE CIE INTERNATIONALE
Priority to FR7606877A priority Critical patent/FR2344093A1/fr
Priority to DE19772710502 priority patent/DE2710502A1/de
Publication of FR2344093A1 publication Critical patent/FR2344093A1/fr
Application granted granted Critical
Publication of FR2344093B1 publication Critical patent/FR2344093B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
FR7606877A 1976-03-10 1976-03-10 Systeme de gestion coherente d'une hierarchie de memoires Granted FR2344093A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR7606877A FR2344093A1 (fr) 1976-03-10 1976-03-10 Systeme de gestion coherente d'une hierarchie de memoires
DE19772710502 DE2710502A1 (de) 1976-03-10 1977-03-10 Anordnung zur kohaerenten leitung einer speicherhierarchie

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7606877A FR2344093A1 (fr) 1976-03-10 1976-03-10 Systeme de gestion coherente d'une hierarchie de memoires

Publications (2)

Publication Number Publication Date
FR2344093A1 true FR2344093A1 (fr) 1977-10-07
FR2344093B1 FR2344093B1 (enExample) 1978-12-08

Family

ID=9170232

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7606877A Granted FR2344093A1 (fr) 1976-03-10 1976-03-10 Systeme de gestion coherente d'une hierarchie de memoires

Country Status (2)

Country Link
DE (1) DE2710502A1 (enExample)
FR (1) FR2344093A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0325419A3 (en) * 1988-01-20 1991-01-02 Advanced Micro Devices, Inc. Method and apparatus for caching interlock variables in an integrated cache memory
EP0325422A3 (en) * 1988-01-20 1991-01-09 Advanced Micro Devices, Inc. Integrated cache unit
EP0325421A3 (en) * 1988-01-20 1991-01-16 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PUBLICATION US: "IBM TECHNICAL DISCLOSURE BULLETIN" VOLUME 15, NO. 9, FEVRIER 1973, PAGES 2813 A 2816, ARTICLE: "DETECTING DISCREPANT SEGMENTS IN A PAGING ENVIRONMENT" KRUSKAL ) *
PUBLICATION US: "IBM TECHNICAL DISCLOSURE BULLETIN", VOLUME 16, NO. 6, NOVEMBRE 1973, PAGES 1847 ET 1848, ARTICLE: "MULTIPROCESSOR INTERFACE" BOEHNER E.A. *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0325419A3 (en) * 1988-01-20 1991-01-02 Advanced Micro Devices, Inc. Method and apparatus for caching interlock variables in an integrated cache memory
EP0325422A3 (en) * 1988-01-20 1991-01-09 Advanced Micro Devices, Inc. Integrated cache unit
EP0325421A3 (en) * 1988-01-20 1991-01-16 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations
US5627992A (en) * 1988-01-20 1997-05-06 Advanced Micro Devices Organization of an integrated cache unit for flexible usage in supporting microprocessor operations

Also Published As

Publication number Publication date
DE2710502A1 (de) 1977-09-22
FR2344093B1 (enExample) 1978-12-08

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