FR2305023A1 - FET with strongly doped gate - has channel of opposite conduction type to gate and is manufactured by engraving and doping process (NL230476) - Google Patents

FET with strongly doped gate - has channel of opposite conduction type to gate and is manufactured by engraving and doping process (NL230476)

Info

Publication number
FR2305023A1
FR2305023A1 FR7508943A FR7508943A FR2305023A1 FR 2305023 A1 FR2305023 A1 FR 2305023A1 FR 7508943 A FR7508943 A FR 7508943A FR 7508943 A FR7508943 A FR 7508943A FR 2305023 A1 FR2305023 A1 FR 2305023A1
Authority
FR
France
Prior art keywords
gate
fet
engraving
channel
manufactured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7508943A
Other languages
French (fr)
Other versions
FR2305023B1 (en
Inventor
Jacques Gremillet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7508943A priority Critical patent/FR2305023A1/en
Priority to DE19762611804 priority patent/DE2611804A1/en
Priority to NL7602896A priority patent/NL7602896A/en
Priority to JP3116976A priority patent/JPS51120181A/en
Publication of FR2305023A1 publication Critical patent/FR2305023A1/en
Application granted granted Critical
Publication of FR2305023B1 publication Critical patent/FR2305023B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The source-drain channel of the FET consists of an active SC layer applied on the surface of the substrate the FET has further a series of resistive contacts in a specified interdigital configurations forming the source and drain contacts. The method of manufacture involves first application of a dielectric on the whole surface of the active layer and engraving this dielectric layer in accordance with the configuration, unti l the active layer is bared. This is folled by application of a strongly doped SC material, which fills the engraved zones finally, ametal is applied which forms resistive contacts on the second layer.
FR7508943A 1975-03-21 1975-03-21 FET with strongly doped gate - has channel of opposite conduction type to gate and is manufactured by engraving and doping process (NL230476) Granted FR2305023A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR7508943A FR2305023A1 (en) 1975-03-21 1975-03-21 FET with strongly doped gate - has channel of opposite conduction type to gate and is manufactured by engraving and doping process (NL230476)
DE19762611804 DE2611804A1 (en) 1975-03-21 1976-03-19 METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR
NL7602896A NL7602896A (en) 1975-03-21 1976-03-19 PROCEDURE FOR MANUFACTURING A FIELD EFFECT TRANSISTOR AND FIELD EFFECT TRANSISTOR MANUFACTURED ACCORDING TO THIS PROCESS.
JP3116976A JPS51120181A (en) 1975-03-21 1976-03-22 Method of producing fet transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7508943A FR2305023A1 (en) 1975-03-21 1975-03-21 FET with strongly doped gate - has channel of opposite conduction type to gate and is manufactured by engraving and doping process (NL230476)

Publications (2)

Publication Number Publication Date
FR2305023A1 true FR2305023A1 (en) 1976-10-15
FR2305023B1 FR2305023B1 (en) 1978-06-23

Family

ID=9152916

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7508943A Granted FR2305023A1 (en) 1975-03-21 1975-03-21 FET with strongly doped gate - has channel of opposite conduction type to gate and is manufactured by engraving and doping process (NL230476)

Country Status (4)

Country Link
JP (1) JPS51120181A (en)
DE (1) DE2611804A1 (en)
FR (1) FR2305023A1 (en)
NL (1) NL7602896A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1573742A (en) * 1967-07-28 1969-07-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1573742A (en) * 1967-07-28 1969-07-04

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
REVUE US "IEEE TRANSACTIONS ON ELECTRON DEVICES", VOLUME ED17, NO 8, AOUT 1970, "SILICON CONTACT FOR AREA REDUCTION OF INTEGRATED CIRCUITS", H.C. LIN ET D.S. ALEXANDER, PAGE 636. *

Also Published As

Publication number Publication date
FR2305023B1 (en) 1978-06-23
JPS51120181A (en) 1976-10-21
NL7602896A (en) 1976-09-23
DE2611804A1 (en) 1976-09-30

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