FR2269175A1 - Capacitive semiconductor memory circuit - with silicon oxide layer on doped silicon substrate covered by insulating layer - Google Patents

Capacitive semiconductor memory circuit - with silicon oxide layer on doped silicon substrate covered by insulating layer

Info

Publication number
FR2269175A1
FR2269175A1 FR7512802A FR7512802A FR2269175A1 FR 2269175 A1 FR2269175 A1 FR 2269175A1 FR 7512802 A FR7512802 A FR 7512802A FR 7512802 A FR7512802 A FR 7512802A FR 2269175 A1 FR2269175 A1 FR 2269175A1
Authority
FR
France
Prior art keywords
layer
silicon oxide
semiconductor memory
memory circuit
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7512802A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2269175A1 publication Critical patent/FR2269175A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92Capacitors with potential-jump barrier or surface barrier
    • H01L29/94Metal-insulator-semiconductors, e.g. MOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
FR7512802A 1974-04-26 1975-04-24 Capacitive semiconductor memory circuit - with silicon oxide layer on doped silicon substrate covered by insulating layer Withdrawn FR2269175A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742420370 DE2420370A1 (de) 1974-04-26 1974-04-26 Speicherschaltung mit mnos-elementen

Publications (1)

Publication Number Publication Date
FR2269175A1 true FR2269175A1 (en) 1975-11-21

Family

ID=5914101

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7512802A Withdrawn FR2269175A1 (en) 1974-04-26 1975-04-24 Capacitive semiconductor memory circuit - with silicon oxide layer on doped silicon substrate covered by insulating layer

Country Status (6)

Country Link
JP (1) JPS50155180A (fr)
BE (1) BE828444A (fr)
DE (1) DE2420370A1 (fr)
FR (1) FR2269175A1 (fr)
IT (1) IT1037412B (fr)
NL (1) NL7504970A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5938655B2 (ja) * 1979-05-14 1984-09-18 日本放送協会 半導体デイスクメモリ装置
GB2072417B (en) * 1980-03-19 1983-12-14 Plessey Co Ltd Semiconductor memory element

Also Published As

Publication number Publication date
NL7504970A (nl) 1975-10-28
DE2420370A1 (de) 1975-11-06
BE828444A (fr) 1975-08-18
JPS50155180A (fr) 1975-12-15
IT1037412B (it) 1979-11-10

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Legal Events

Date Code Title Description
ST Notification of lapse