FR2239736A1 - Memory circuit with individual transistor storage cells - is connected with multiple lead to form storage line - Google Patents
Memory circuit with individual transistor storage cells - is connected with multiple lead to form storage lineInfo
- Publication number
- FR2239736A1 FR2239736A1 FR7414565A FR7414565A FR2239736A1 FR 2239736 A1 FR2239736 A1 FR 2239736A1 FR 7414565 A FR7414565 A FR 7414565A FR 7414565 A FR7414565 A FR 7414565A FR 2239736 A1 FR2239736 A1 FR 2239736A1
- Authority
- FR
- France
- Prior art keywords
- multiple lead
- memory circuit
- storage
- individual transistor
- storage cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US38548473A | 1973-08-03 | 1973-08-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2239736A1 true FR2239736A1 (en) | 1975-02-28 |
Family
ID=23521563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7414565A Withdrawn FR2239736A1 (en) | 1973-08-03 | 1974-04-26 | Memory circuit with individual transistor storage cells - is connected with multiple lead to form storage line |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS5040246A (enrdf_load_stackoverflow) |
DE (1) | DE2422136A1 (enrdf_load_stackoverflow) |
FR (1) | FR2239736A1 (enrdf_load_stackoverflow) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2340599A1 (fr) * | 1975-12-29 | 1977-09-02 | Mostek Corp | Memoire a acces aleatoire, dynamique |
FR2376494A1 (en) * | 1976-12-29 | 1978-07-28 | Mostek Corp | Random access dynamic memory - has pushpull amplifier for rapid action in triggering digit line potentials and uses transistors as input resistors |
FR2468973A1 (fr) * | 1979-11-01 | 1981-05-08 | Texas Instruments Inc | Circuit de detection differentielle pour une matrice de memoire a sortie monopolaire |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51128236A (en) * | 1975-04-30 | 1976-11-09 | Nec Corp | A memory circuit |
DE2634089C3 (de) * | 1975-08-11 | 1988-09-08 | Nippon Telegraph And Telephone Corp., Tokio/Tokyo | Schaltungsanordnung zum Erfassen schwacher Signale |
DE2646245A1 (de) * | 1975-10-28 | 1977-05-05 | Motorola Inc | Speicherschaltung |
JPS5922316B2 (ja) * | 1976-02-24 | 1984-05-25 | 株式会社東芝 | ダイナミツクメモリ装置 |
US4028557A (en) * | 1976-05-21 | 1977-06-07 | Bell Telephone Laboratories, Incorporated | Dynamic sense-refresh detector amplifier |
JPS53134337A (en) * | 1977-03-25 | 1978-11-22 | Hitachi Ltd | Sense circuit |
DE2801255C2 (de) * | 1978-01-12 | 1984-06-28 | Siemens AG, 1000 Berlin und 8000 München | Bewerterschaltung für symmetrisch strukturierte Halbleiterspeicher mit Ein-Transistor-Speicherelementen |
US4162416A (en) * | 1978-01-16 | 1979-07-24 | Bell Telephone Laboratories, Incorporated | Dynamic sense-refresh detector amplifier |
US4247791A (en) * | 1978-04-03 | 1981-01-27 | Rockwell International Corporation | CMOS Memory sense amplifier |
LU87431A1 (de) * | 1988-06-08 | 1989-06-14 | Siemens Ag | Breitbandsignal-koppeleinrichtung |
LU87566A1 (de) * | 1989-03-22 | 1990-01-08 | Siemens Ag | Breitbandsignal-koppeleinrichtung |
FR2650452B1 (fr) * | 1989-07-27 | 1991-11-15 | Sgs Thomson Microelectronics | Point de croisement pour matrice de commutation |
-
1974
- 1974-04-09 JP JP49039552A patent/JPS5040246A/ja active Pending
- 1974-04-26 FR FR7414565A patent/FR2239736A1/fr not_active Withdrawn
- 1974-05-08 DE DE19742422136 patent/DE2422136A1/de active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2340599A1 (fr) * | 1975-12-29 | 1977-09-02 | Mostek Corp | Memoire a acces aleatoire, dynamique |
FR2376494A1 (en) * | 1976-12-29 | 1978-07-28 | Mostek Corp | Random access dynamic memory - has pushpull amplifier for rapid action in triggering digit line potentials and uses transistors as input resistors |
FR2468973A1 (fr) * | 1979-11-01 | 1981-05-08 | Texas Instruments Inc | Circuit de detection differentielle pour une matrice de memoire a sortie monopolaire |
Also Published As
Publication number | Publication date |
---|---|
DE2422136A1 (de) | 1975-02-20 |
JPS5040246A (enrdf_load_stackoverflow) | 1975-04-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2239736A1 (en) | Memory circuit with individual transistor storage cells - is connected with multiple lead to form storage line | |
CA988220A (en) | Monolithic memory utilizing defective storage cells | |
CA960775A (en) | Full capacity monolithic memory utilizing defective storage cells | |
CA941965A (en) | Integrated circuit read only memory bit organized in coincident select structure | |
FR2149396B1 (enrdf_load_stackoverflow) | ||
SE7508428L (sv) | Ordorganiserat minne med konstant accesstid. | |
CA925170A (en) | Pulse power data storage cell | |
JPS57111893A (en) | Relieving system of defective memory | |
JPS5785255A (en) | Memory storage for integrated circuit | |
ES395249A1 (es) | Un sistema de memoria de acceso al azar. | |
JPS5314525A (en) | Memory circuit | |
CA932460A (en) | Monolithic associative memory cell | |
CA983167A (en) | Memory cell circuit | |
CA934876A (en) | Distributed logic memory cell for parallel cellular-logic processor | |
JPS5641593A (en) | Semiconductor memory unit | |
AU460048B2 (en) | Memory storage cell with single single selection line and single input/output line | |
JPS5715286A (en) | Memory device | |
JPS54153538A (en) | Read write access system to reloadable memory | |
CA864134A (en) | Memory employing transistor storage cells | |
JPS6453398A (en) | Non-volatile semiconductor memory device | |
AU414953B2 (en) | Memory employing transistor storage cells | |
JPS6482392A (en) | Semiconductor memory device | |
JPS5641592A (en) | Semiconductor memory unit | |
SU395900A1 (ru) | Динамическая ячейка памяти на мдп-транзисторах | |
AU4235668A (en) | Memory employing transistor storage cells |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |