FI880867A - Housing for an optical device and a method of manufacturing the optical device - Google Patents

Housing for an optical device and a method of manufacturing the optical device Download PDF

Info

Publication number
FI880867A
FI880867A FI880867A FI880867A FI880867A FI 880867 A FI880867 A FI 880867A FI 880867 A FI880867 A FI 880867A FI 880867 A FI880867 A FI 880867A FI 880867 A FI880867 A FI 880867A
Authority
FI
Finland
Prior art keywords
optical device
housing
connection flange
optical
recess
Prior art date
Application number
FI880867A
Other languages
Finnish (fi)
Swedish (sv)
Other versions
FI880867A0 (en
FI91574C (en
FI91574B (en
Inventor
Hideaki Nishizawa
Original Assignee
Sumitomo Electric Industries
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58218964A external-priority patent/JPS60110180A/en
Priority claimed from JP58223020A external-priority patent/JPS60113978A/en
Priority claimed from JP58232341A external-priority patent/JPS60124885A/en
Priority claimed from FI844473A external-priority patent/FI82999C/en
Application filed by Sumitomo Electric Industries filed Critical Sumitomo Electric Industries
Publication of FI880867A0 publication Critical patent/FI880867A0/en
Publication of FI880867A publication Critical patent/FI880867A/en
Application granted granted Critical
Publication of FI91574B publication Critical patent/FI91574B/en
Publication of FI91574C publication Critical patent/FI91574C/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Light Receiving Elements (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

The invention concerns a housing for an optical arrangement and a method for production of the optical arrangment. In the housing according to the invention, an essentially smooth surface is produced on connection flange 23 and the upper surface on a sapphire substrate 23 has a recess with sloping sides and the electrically conducting paste edges are arranged on the recess's sloping slides in which the edges of the paste are prevented from rising higher on the ends than in the other parts after firing. In the method according to the invention the optical chip set is connected on connection flange 23 so that electrode 65 and solder layer 66, each of which has a light introduction pole 24 are mounted in succession in the layer on the anchored side of the optical chip set, which is then anchored to connection flange 23 by means of solder layer 66. <IMAGE>
FI880867A 1983-11-21 1988-02-24 Housing for an optical device and a method of manufacturing the optical device FI91574C (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP21896483 1983-11-21
JP58218964A JPS60110180A (en) 1983-11-21 1983-11-21 Package for photoelement
JP58223020A JPS60113978A (en) 1983-11-25 1983-11-25 Optical element
JP22302083 1983-11-25
JP23234183 1983-12-08
JP58232341A JPS60124885A (en) 1983-12-08 1983-12-08 Light-receiving diode and manufacture thereof
FI844473 1984-11-14
FI844473A FI82999C (en) 1983-11-21 1984-11-14 OPTICAL ANGLE FARING FOR FOUNDATION.

Publications (4)

Publication Number Publication Date
FI880867A0 FI880867A0 (en) 1988-02-24
FI880867A true FI880867A (en) 1988-02-24
FI91574B FI91574B (en) 1994-03-31
FI91574C FI91574C (en) 1994-07-11

Family

ID=27444091

Family Applications (1)

Application Number Title Priority Date Filing Date
FI880867A FI91574C (en) 1983-11-21 1988-02-24 Housing for an optical device and a method of manufacturing the optical device

Country Status (1)

Country Link
FI (1) FI91574C (en)

Also Published As

Publication number Publication date
FI880867A0 (en) 1988-02-24
FI91574C (en) 1994-07-11
FI91574B (en) 1994-03-31

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Legal Events

Date Code Title Description
BB Publication of examined application
MM Patent lapsed
MM Patent lapsed

Owner name: SUMITOMO ELECTRIC INDUSTRIES, LTD.