FI105727B - Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin - Google Patents

Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin Download PDF

Info

Publication number
FI105727B
FI105727B FI972091A FI972091A FI105727B FI 105727 B FI105727 B FI 105727B FI 972091 A FI972091 A FI 972091A FI 972091 A FI972091 A FI 972091A FI 105727 B FI105727 B FI 105727B
Authority
FI
Finland
Prior art keywords
asic
processor
read
signal
signals
Prior art date
Application number
FI972091A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI972091A0 (fi
FI972091A (fi
Inventor
Olli Piirainen
Aki Happonen
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Publication of FI972091A0 publication Critical patent/FI972091A0/fi
Priority to FI972091A priority Critical patent/FI105727B/fi
Priority to CN98805140A priority patent/CN1256769A/zh
Priority to EP98921512A priority patent/EP0988603B1/en
Priority to JP54884098A priority patent/JP2001526810A/ja
Priority to PCT/FI1998/000402 priority patent/WO1998052123A2/en
Priority to AU74338/98A priority patent/AU736765B2/en
Priority to AT98921512T priority patent/ATE231256T1/de
Priority to US09/423,134 priority patent/US6654844B1/en
Priority to DE69810769T priority patent/DE69810769T2/de
Publication of FI972091A publication Critical patent/FI972091A/fi
Priority to NO995556A priority patent/NO995556D0/no
Application granted granted Critical
Publication of FI105727B publication Critical patent/FI105727B/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Multi Processors (AREA)
  • Electrotherapy Devices (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Small-Scale Networks (AREA)
  • Hardware Redundancy (AREA)
FI972091A 1997-05-15 1997-05-15 Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin FI105727B (fi)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FI972091A FI105727B (fi) 1997-05-15 1997-05-15 Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin
PCT/FI1998/000402 WO1998052123A2 (en) 1997-05-15 1998-05-12 Method and arrangement for connecting processor to asic
EP98921512A EP0988603B1 (en) 1997-05-15 1998-05-12 Method and arrangement for connecting processor to asic
JP54884098A JP2001526810A (ja) 1997-05-15 1998-05-12 プロセッサをａｓｉｃに接続する方法及び構成体
CN98805140A CN1256769A (zh) 1997-05-15 1998-05-12 将处理器连接到asic的方法和装置
AU74338/98A AU736765B2 (en) 1997-05-15 1998-05-12 Method and arrangement for connecting processor to ASIC
AT98921512T ATE231256T1 (de) 1997-05-15 1998-05-12 Verfahren und vorrichtung zur verbindung eines prozessors mit einer anwendungsspezifischen integrierten schaltung (asic)
US09/423,134 US6654844B1 (en) 1997-05-15 1998-05-12 Method and arrangement for connecting processor to ASIC
DE69810769T DE69810769T2 (de) 1997-05-15 1998-05-12 Verfahren und vorrichtung zur verbindung eines prozessors mit einer anwendungsspezifischen integrierten schaltung (asic)
NO995556A NO995556D0 (no) 1997-05-15 1999-11-12 Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI972091A FI105727B (fi) 1997-05-15 1997-05-15 Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin
FI972091 1997-05-15

Publications (3)

Publication Number Publication Date
FI972091A0 FI972091A0 (fi) 1997-05-15
FI972091A FI972091A (fi) 1998-11-16
FI105727B true FI105727B (fi) 2000-09-29

Family

ID=8548861

Family Applications (1)

Application Number Title Priority Date Filing Date
FI972091A FI105727B (fi) 1997-05-15 1997-05-15 Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin

Country Status (10)

Country Link
US (1) US6654844B1 (zh)
EP (1) EP0988603B1 (zh)
JP (1) JP2001526810A (zh)
CN (1) CN1256769A (zh)
AT (1) ATE231256T1 (zh)
AU (1) AU736765B2 (zh)
DE (1) DE69810769T2 (zh)
FI (1) FI105727B (zh)
NO (1) NO995556D0 (zh)
WO (1) WO1998052123A2 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999066392A1 (en) 1998-06-17 1999-12-23 Nokia Networks Oy An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface
US6789153B1 (en) * 2001-02-20 2004-09-07 Lsi Logic Corporation Bridge for coupling digital signal processor to on-chip bus as slave

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0340901A3 (en) 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Access system for dual port memory
GB2217064A (en) 1988-03-23 1989-10-18 Benchmark Technologies Interfacing asynchronous processors
US5335338A (en) 1991-05-31 1994-08-02 Micro Solutions, Inc. General purpose parallel port interface
US5255375A (en) * 1992-01-10 1993-10-19 Digital Equipment Corporation High performance interface between an asynchronous bus and one or more processors or the like
US5339395A (en) * 1992-09-17 1994-08-16 Delco Electronics Corporation Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
US5325491A (en) * 1993-04-13 1994-06-28 International Business Machines Corporation Method and apparatus for extending a computer bus
US5428623A (en) * 1993-07-01 1995-06-27 Tandem Computers Incorporated Scannable interface to nonscannable microprocessor
US5758107A (en) * 1994-02-14 1998-05-26 Motorola Inc. System for offloading external bus by coupling peripheral device to data processor through interface logic that emulate the characteristics of the external bus
US5680594A (en) 1995-05-24 1997-10-21 Eastman Kodak Company Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies
US5987590A (en) * 1996-04-02 1999-11-16 Texas Instruments Incorporated PC circuits, systems and methods

Also Published As

Publication number Publication date
CN1256769A (zh) 2000-06-14
WO1998052123A3 (en) 1999-02-04
JP2001526810A (ja) 2001-12-18
AU736765B2 (en) 2001-08-02
NO995556L (no) 1999-11-12
AU7433898A (en) 1998-12-08
DE69810769D1 (de) 2003-02-20
FI972091A0 (fi) 1997-05-15
EP0988603A2 (en) 2000-03-29
ATE231256T1 (de) 2003-02-15
EP0988603B1 (en) 2003-01-15
DE69810769T2 (de) 2003-09-25
WO1998052123A2 (en) 1998-11-19
FI972091A (fi) 1998-11-16
NO995556D0 (no) 1999-11-12
US6654844B1 (en) 2003-11-25

Similar Documents

Publication Publication Date Title
KR100337052B1 (ko) 동기화된 독출 포인터 및 기록 포인터를 갖는 2 중 포트 ｆｉｆｏ
KR100694440B1 (ko) 반도체기억장치
US7154327B2 (en) Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system
USRE46754E1 (en) Integrated circuit for clock generation for memory devices
US7586337B2 (en) Circuit for switching between two clock signals independently of the frequency of the clock signals
KR100498473B1 (ko) 제어신호 발생회로 및 상기 제어신호 발생회로를 구비하는데이터 전송회로
US7461186B2 (en) Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements
FI105727B (fi) Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin
US6377071B1 (en) Composite flag generation for DDR FIFOs
US6906558B2 (en) Data latch circuit and method for improving operating speed in a data latch circuit
Wasif et al. Energy efficient synchronous-asynchronous circuit-switched NoC
US5793672A (en) Low power register memory element circuits
US6643793B1 (en) Apparatus for transferring and holding data based on a selected clock rate
US20040223374A1 (en) Synchronous up/down address generator for burst mode read
KR20130069350A (ko) 듀얼 포트 메모리 및 그 방법
KR100381024B1 (ko) 마이크로프로세서 개발 시스템의 기능을 효율적으로 지원하기위한 회로
US7894278B2 (en) Semiconductor memory device and method for operating the same
US20200312383A1 (en) Semiconductor device
JP3917736B2 (ja) 集積回路
US20060203564A1 (en) Memory device having off-chip driver enable circuit and method for reducing delays during read operations
US20040160845A1 (en) Method and apparatus to reduce access time in synchronous FIFOS with zero latency overhead
KR100233843B1 (ko) 영상 데이터 저장 장치
CN116400882A (zh) 一种深度可拓展的先进先出存储装置
KR0120220Y1 (ko) 시분할 메모리의 억세스 제어회로
JP2004158166A (ja) 集積回路装置、データを供給するための方法およびメモリアレイにデータを書込むための方法