ES8501902A1 - Una instalacion para procesar las interrupciones de comprobacion de maquina - Google Patents

Una instalacion para procesar las interrupciones de comprobacion de maquina

Info

Publication number
ES8501902A1
ES8501902A1 ES528305A ES528305A ES8501902A1 ES 8501902 A1 ES8501902 A1 ES 8501902A1 ES 528305 A ES528305 A ES 528305A ES 528305 A ES528305 A ES 528305A ES 8501902 A1 ES8501902 A1 ES 8501902A1
Authority
ES
Spain
Prior art keywords
machine check
machine
generates
facility
mcu2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES528305A
Other languages
English (en)
Other versions
ES528305A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8501902A1 publication Critical patent/ES8501902A1/es
Publication of ES528305A0 publication Critical patent/ES528305A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Hardware Redundancy (AREA)
  • Computer And Data Communications (AREA)

Abstract

INSTALACION PARA PROCESAR LAS INTERRUPCIONES DE COMPROBACION DE MAQUINA.COMPRENDE UNA UNIDAD CENTRAL DE PROCESO (CPU1) QUE CONSTA DE: UNA PARTE (11) GENERADORA DE SEN/AL QUE GENERA UN CODIGO MODIFICADO DE INTERRUPCION DE COMPR-BACION DE MAQUINA; UNA PARTE (4) DETECTORA DE FALLOS QUE GENERA UNA SEN/AL DE INTERRUPCION DE COMPROBACION DE MAQUINA CUANDO SE DETECTA UN FALLO EN LA (CPU1); Y UNA PARTE CENTRAL: UNA UNIDAD DE CONTROL DE MEMORIA (MCU2) QUE CONSTA DE UNA PARTE (5) DETECTORA DE FALLOS QUE GENERA UNA SEN/AL DE INTERRUPCION DE COMPROBACION DE MAQUINA CUANDO SE DETECTA UN FALLO EN LA (MCU2); Y UNA UNIDAD DE ALMACENAMIENTO PRINCIPAL (MSU3) QUE CONSTA DE UNA PARTE DE CONTROL (20) QUE INCLUYE UN REGISTRO (19) PARA ALMACENAR UN CODIGO DE INTERRUPCION DE COMPROBACION DE MAQUINA Y UNA RUTINA DE PROCESO DE COMPROBACION DE MAQUINA.
ES528305A 1982-12-23 1983-12-22 Una instalacion para procesar las interrupciones de comprobacion de maquina Granted ES528305A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57228855A JPS59116858A (ja) 1982-12-23 1982-12-23 マシンチエツク割込み処理方式

Publications (2)

Publication Number Publication Date
ES8501902A1 true ES8501902A1 (es) 1984-12-01
ES528305A0 ES528305A0 (es) 1984-12-01

Family

ID=16882929

Family Applications (1)

Application Number Title Priority Date Filing Date
ES528305A Granted ES528305A0 (es) 1982-12-23 1983-12-22 Una instalacion para procesar las interrupciones de comprobacion de maquina

Country Status (9)

Country Link
US (1) US4587654A (es)
EP (1) EP0112672B1 (es)
JP (1) JPS59116858A (es)
KR (1) KR890001796B1 (es)
AU (1) AU544915B2 (es)
BR (1) BR8307085A (es)
CA (1) CA1204876A (es)
DE (1) DE3380369D1 (es)
ES (1) ES528305A0 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916697A (en) * 1988-06-24 1990-04-10 International Business Machines Corporation Apparatus for partitioned clock stopping in response to classified processor errors

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3229251A (en) * 1962-03-26 1966-01-11 Ibm Computer error stop system
US3555517A (en) * 1968-10-30 1971-01-12 Ibm Early error detection system for data processing machine
US3707714A (en) * 1971-01-08 1972-12-26 Honeywell Inc Multiple error detector
JPS5519000B2 (es) * 1973-07-11 1980-05-22
JPS50117336A (es) * 1973-11-30 1975-09-13
IT1046598B (it) * 1974-05-16 1980-07-31 Honeywell Inf Systems Interfaccia di connessione di apparecchiature periferiche a un calcolatore provvista di meccanismi di segnalazione e di distinzione tradiversi tipi di errore
JPS51146143A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Wedging process mode when logic device generates error action
US4044337A (en) * 1975-12-23 1977-08-23 International Business Machines Corporation Instruction retry mechanism for a data processing system
JPS6032217B2 (ja) * 1979-04-02 1985-07-26 日産自動車株式会社 制御用コンピュ−タのフェィルセ−フ装置
DE3036926C2 (de) * 1980-09-30 1984-07-26 Siemens AG, 1000 Berlin und 8000 München Verfahren und Anordnung zur Steuerung des Arbeitsablaufes in Datenverarbeitungsanlagen mit Mikroprogrammsteuerung
JPS57159353A (en) * 1981-03-28 1982-10-01 Fujitsu Ltd Failure processing system

Also Published As

Publication number Publication date
US4587654A (en) 1986-05-06
JPS59116858A (ja) 1984-07-05
JPS6322339B2 (es) 1988-05-11
CA1204876A (en) 1986-05-20
EP0112672B1 (en) 1989-08-09
KR890001796B1 (ko) 1989-05-22
EP0112672A3 (en) 1987-05-13
EP0112672A2 (en) 1984-07-04
AU544915B2 (en) 1985-06-20
ES528305A0 (es) 1984-12-01
DE3380369D1 (en) 1989-09-14
AU2146683A (en) 1984-06-28
KR840007188A (ko) 1984-12-05
BR8307085A (pt) 1984-07-31

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001