JPS6421564A - Test system for multiprocessor system - Google Patents

Test system for multiprocessor system

Info

Publication number
JPS6421564A
JPS6421564A JP62177670A JP17767087A JPS6421564A JP S6421564 A JPS6421564 A JP S6421564A JP 62177670 A JP62177670 A JP 62177670A JP 17767087 A JP17767087 A JP 17767087A JP S6421564 A JPS6421564 A JP S6421564A
Authority
JP
Japan
Prior art keywords
processor
processors
storage device
main storage
access area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62177670A
Other languages
Japanese (ja)
Inventor
Hisatoshi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62177670A priority Critical patent/JPS6421564A/en
Publication of JPS6421564A publication Critical patent/JPS6421564A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To test a defective processor without exerting influence upon the normal operation of a processor by restarting a system after distinguishing an access area in a main storage device for a processor from an access area in the main storage device for other processors. CONSTITUTION:When a fault is generated in a processor 20, the operation of the system is temporarily stopped and respective set values of the 2nd and 3rd registers 80, 90 for the processor 20 are set up differently from respective set values of the 2nd registers 81-8n and the 3rd registers 91-9n for other processors 21-2n. Thereby, the system is restarted after distinguishing the access area in the main storage device 4 for the processor 20 from the access area in the main storage device 4 for the processors 21-2n. Consequently, the defective processor 20 can be tested without disturbing the processors 21-2n in normal operation.
JP62177670A 1987-07-15 1987-07-15 Test system for multiprocessor system Pending JPS6421564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62177670A JPS6421564A (en) 1987-07-15 1987-07-15 Test system for multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62177670A JPS6421564A (en) 1987-07-15 1987-07-15 Test system for multiprocessor system

Publications (1)

Publication Number Publication Date
JPS6421564A true JPS6421564A (en) 1989-01-24

Family

ID=16035055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62177670A Pending JPS6421564A (en) 1987-07-15 1987-07-15 Test system for multiprocessor system

Country Status (1)

Country Link
JP (1) JPS6421564A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327550A (en) * 1990-11-27 1994-07-05 Cray Research, Inc. Disabled memory sections for degraded operation of a vector supercomputer
GB2407414A (en) * 2003-10-22 2005-04-27 Hewlett Packard Development Co Fault-tolerant multi-core microprocesing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327550A (en) * 1990-11-27 1994-07-05 Cray Research, Inc. Disabled memory sections for degraded operation of a vector supercomputer
GB2407414A (en) * 2003-10-22 2005-04-27 Hewlett Packard Development Co Fault-tolerant multi-core microprocesing
GB2407414B (en) * 2003-10-22 2006-10-04 Hewlett Packard Development Co Fault-tolerant multi-core microprocessing
US7206966B2 (en) 2003-10-22 2007-04-17 Hewlett-Packard Development Company, L.P. Fault-tolerant multi-core microprocessing

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