JPS57105049A - Fault processing method of data processing device - Google Patents

Fault processing method of data processing device

Info

Publication number
JPS57105049A
JPS57105049A JP55182339A JP18233980A JPS57105049A JP S57105049 A JPS57105049 A JP S57105049A JP 55182339 A JP55182339 A JP 55182339A JP 18233980 A JP18233980 A JP 18233980A JP S57105049 A JPS57105049 A JP S57105049A
Authority
JP
Japan
Prior art keywords
fault
processor
memory
processors
analyzing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182339A
Other languages
Japanese (ja)
Inventor
Nobuhiro Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55182339A priority Critical patent/JPS57105049A/en
Publication of JPS57105049A publication Critical patent/JPS57105049A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To minimize a down time of a system by the first and second processors, also to easily analyze the cause of an accident, and to quickly restart an operation of the system, by providing a fault detecting circuit, and the first and second processors. CONSTITUTION:A fault detecting circuit 1, the first processor 21 for executing a regular processing operation, and the second processor 22 for analyzing an abnormal operation are provided on a data processing system. This circuit 1 and both the processors 21, 22 are connected to a memory 3 and an interruption controlling circuit 4 through a system bus line BL1, respectively. When a fault has been detected by the detecting ciruit 1, its own storage contents are stored in a prescribed area of the memory 3 by the processor 21, and after that, immediately or after a constant interval of time has passed, the operation is restarted. Also, the contents of the memory 3, which are required for analyzing a fault are transferred to an area of its own memory by the processor 22, and also the operation of the system is restarted to its normal state quickly by analyzing the fault.
JP55182339A 1980-12-23 1980-12-23 Fault processing method of data processing device Pending JPS57105049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182339A JPS57105049A (en) 1980-12-23 1980-12-23 Fault processing method of data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182339A JPS57105049A (en) 1980-12-23 1980-12-23 Fault processing method of data processing device

Publications (1)

Publication Number Publication Date
JPS57105049A true JPS57105049A (en) 1982-06-30

Family

ID=16116573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182339A Pending JPS57105049A (en) 1980-12-23 1980-12-23 Fault processing method of data processing device

Country Status (1)

Country Link
JP (1) JPS57105049A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0285937A (en) * 1988-09-22 1990-03-27 Nec Corp Error detecting system
JPH0722103A (en) * 1993-06-30 1995-01-24 Yamaichi Electron Co Ltd Coil type contact piece and connector using it
CN108021407A (en) * 2017-12-06 2018-05-11 锐捷网络股份有限公司 Method for processing business and device based on the network equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0285937A (en) * 1988-09-22 1990-03-27 Nec Corp Error detecting system
JPH0722103A (en) * 1993-06-30 1995-01-24 Yamaichi Electron Co Ltd Coil type contact piece and connector using it
CN108021407A (en) * 2017-12-06 2018-05-11 锐捷网络股份有限公司 Method for processing business and device based on the network equipment
CN108021407B (en) * 2017-12-06 2021-01-15 锐捷网络股份有限公司 Service processing method and device based on network equipment

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