JPS57143643A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS57143643A
JPS57143643A JP2935081A JP2935081A JPS57143643A JP S57143643 A JPS57143643 A JP S57143643A JP 2935081 A JP2935081 A JP 2935081A JP 2935081 A JP2935081 A JP 2935081A JP S57143643 A JPS57143643 A JP S57143643A
Authority
JP
Japan
Prior art keywords
interruption
information
restored
request exists
saved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2935081A
Other languages
Japanese (ja)
Inventor
Akira Sakauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2935081A priority Critical patent/JPS57143643A/en
Publication of JPS57143643A publication Critical patent/JPS57143643A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To make the processing high-speed, by detecting that an interrupt request exists and that restores interrupt inhibition designating information permits interruption, when a return instruction for information saved because of the interruption is executed. CONSTITUTION:When an execution of return instruction is started, previously saved program execution state PSW information is read from a stack. When an interruption inhibition mode is designated in read information, it is restored by a CPU to set a new interruption inhibiting mode. If this information permits an interruption after it is tested and restored, it is tested whether an interruption request exists or not. If the interruption request exists, the control is transferred to an interruption processing program. Thus, CPU information is not restored and saved for the reinterruption after the return from the interruption, and the processing is performed in a high speed.
JP2935081A 1981-03-03 1981-03-03 Data processing device Pending JPS57143643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2935081A JPS57143643A (en) 1981-03-03 1981-03-03 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2935081A JPS57143643A (en) 1981-03-03 1981-03-03 Data processing device

Publications (1)

Publication Number Publication Date
JPS57143643A true JPS57143643A (en) 1982-09-04

Family

ID=12273763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2935081A Pending JPS57143643A (en) 1981-03-03 1981-03-03 Data processing device

Country Status (1)

Country Link
JP (1) JPS57143643A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265134A (en) * 1985-09-13 1987-03-24 Fujitsu Ltd Interruption processing system
JPS62286128A (en) * 1986-05-16 1987-12-12 インテル・コ−ポレ−シヨン Stack frame cash and control mechanism used therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140230A (en) * 1974-04-26 1975-11-10
JPS54153542A (en) * 1978-05-24 1979-12-03 Nec Corp Data processor of microprogram control type

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140230A (en) * 1974-04-26 1975-11-10
JPS54153542A (en) * 1978-05-24 1979-12-03 Nec Corp Data processor of microprogram control type

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265134A (en) * 1985-09-13 1987-03-24 Fujitsu Ltd Interruption processing system
JPS62286128A (en) * 1986-05-16 1987-12-12 インテル・コ−ポレ−シヨン Stack frame cash and control mechanism used therefor

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