ES8501545A1 - Una unidad de control de requrimiento de acceso en un sistema de procesado de datos. - Google Patents
Una unidad de control de requrimiento de acceso en un sistema de procesado de datos.Info
- Publication number
- ES8501545A1 ES8501545A1 ES523396A ES523396A ES8501545A1 ES 8501545 A1 ES8501545 A1 ES 8501545A1 ES 523396 A ES523396 A ES 523396A ES 523396 A ES523396 A ES 523396A ES 8501545 A1 ES8501545 A1 ES 8501545A1
- Authority
- ES
- Spain
- Prior art keywords
- determination circuit
- request
- access
- priority determination
- priority
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
- Complex Calculations (AREA)
Abstract
UNIDAD DE CONTROL DE REQUERIMIENTO DE ACCESO EN UN SISTEMA DE PROCESADO DE DATOS, EN PARTICULAR, APARATO PARA DETERMINAR UNA PRIORIDAD ENTRE UNA PLURALIDAD DE REQUERIMIENTOS DE ACCESO EN EL APARATO DE CONTROL DE MEMORIA.CONSTA DE UN CIRCUITO DE SELECCION DE REQUERIMIENTO DE ACCESO, CONECTADO CON LA PLURALIDAD DE APARATOS DE REQUERIMIENTO DE ACCESO; DE UN CIRCUITO DE CONTROL DE TUBERIA, CONECTADO CON EL CIRCUITO DE SELECCION DE REQUERIMIENTO DE ACCESO Y CON EL APARATO DE MEMORIA; Y DE UN CIRCUITO DE CONTROL DE PRIORIDAD CONECTADO CON EL CIRCUITO DE CONTROL DE TUBERIA.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57104736A JPS58222361A (ja) | 1982-06-18 | 1982-06-18 | デ−タ処理システムにおけるアクセス要求の優先順位決定制御方式 |
JP57108775A JPS58225463A (ja) | 1982-06-24 | 1982-06-24 | アクセス処理方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
ES523396A0 ES523396A0 (es) | 1984-12-01 |
ES8501545A1 true ES8501545A1 (es) | 1984-12-01 |
Family
ID=26445142
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES523396A Expired ES8501545A1 (es) | 1982-06-18 | 1983-06-17 | Una unidad de control de requrimiento de acceso en un sistema de procesado de datos. |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0097499B1 (es) |
KR (1) | KR860000904B1 (es) |
AU (1) | AU540649B2 (es) |
BR (1) | BR8303232A (es) |
CA (1) | CA1193024A (es) |
DE (1) | DE3380457D1 (es) |
ES (1) | ES8501545A1 (es) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4788640A (en) * | 1986-01-17 | 1988-11-29 | Intel Corporation | Priority logic system |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1077339A (en) * | 1965-04-05 | 1967-07-26 | Ibm | Control device for a data processor |
US4152764A (en) * | 1977-03-16 | 1979-05-01 | International Business Machines Corporation | Floating-priority storage control for processors in a multi-processor system |
US4345309A (en) * | 1980-01-28 | 1982-08-17 | Digital Equipment Corporation | Relating to cached multiprocessor system with pipeline timing |
JPS57164338A (en) * | 1981-03-31 | 1982-10-08 | Fujitsu Ltd | Selection circuit for priority |
-
1983
- 1983-06-16 KR KR1019830002695A patent/KR860000904B1/ko not_active IP Right Cessation
- 1983-06-17 EP EP83303505A patent/EP0097499B1/en not_active Expired
- 1983-06-17 DE DE8383303505T patent/DE3380457D1/de not_active Expired
- 1983-06-17 BR BR8303232A patent/BR8303232A/pt not_active IP Right Cessation
- 1983-06-17 ES ES523396A patent/ES8501545A1/es not_active Expired
- 1983-06-17 CA CA000430645A patent/CA1193024A/en not_active Expired
- 1983-06-17 AU AU15883/83A patent/AU540649B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
AU540649B2 (en) | 1984-11-29 |
KR860000904B1 (ko) | 1986-07-16 |
KR840005230A (ko) | 1984-11-05 |
EP0097499B1 (en) | 1989-08-23 |
AU1588383A (en) | 1983-12-22 |
ES523396A0 (es) | 1984-12-01 |
DE3380457D1 (en) | 1989-09-28 |
CA1193024A (en) | 1985-09-03 |
EP0097499A2 (en) | 1984-01-04 |
EP0097499A3 (en) | 1985-07-31 |
BR8303232A (pt) | 1984-01-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19971001 |