ES487814A1 - Una disposicion mejorada de inscripcion de canal a memoria - Google Patents

Una disposicion mejorada de inscripcion de canal a memoria

Info

Publication number
ES487814A1
ES487814A1 ES487814A ES487814A ES487814A1 ES 487814 A1 ES487814 A1 ES 487814A1 ES 487814 A ES487814 A ES 487814A ES 487814 A ES487814 A ES 487814A ES 487814 A1 ES487814 A1 ES 487814A1
Authority
ES
Spain
Prior art keywords
data processing
processing system
store
channel
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES487814A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES487814A1 publication Critical patent/ES487814A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

Una disposición mejorada de inscripción de canal a memoria para inscribir a través de límites de palabra doble, en un sistema de tratamiento de datos que incluye una unidad de tratamiento, al menos un canal conectado a dicha unidad de tratamiento, una primera memoria de ocultación de alta velocidad y de baja capacidad, una segunda memoria principal de velocidad más baja y alta capacidad, y un registro de entrada-salida conectado entre dicha memoria principal, dicha memoria de ocultación y dicha unidad de tratamiento, en la que se almacenan datos en dicha memoria de ocultación en la forma de páginas de memoria de ocultación, cada una de las cuales comprenden una pluralidad de palabras dobles, comprendiendo cada palabra doble varias baterías de bitios de datos; comprendiendo dicha disposición de inscripción de canal a memoria: una memoria intermedia de intercambio destinada a recibir datos de dicho registro de entrada-salida y que tiene una capacidad de almacenamiento de al menos una pagina de memoria de ocultación; un subconjuntos de circuitos lógicos y de corrección de error conectado entre dicho registro de entrada- salid y dicha memoria principal, estando destinado dicho subconjunto a recibir datos de dicha memoria intermedia de intercambio; medios que responden a una solicitud de inscripción parcial de canal para determinar si la página de datos direccionada por la solicitud de inscripción de canal está (acierto) o no está (fallo) en dicha memoria de ocultación; medios que responden a un acierto para intercalar o "fundir" los datos de dicha inscripción parcial de canal con la página de memoria de ocultación direccionada en dicho registro de entrada-salida, intercalándose individualmente una pluralidad de baterías de bitios y para transferir dichos datos intercalados a dicha memoria principal a través de dicho subconjunto; y medios que responden a un fallo para intercalar los datos de dicha inscripción parcial de canal con los datos direccionados desde dicha memoria principal en dicho subconjunto de circuito lógicos y de corrección de error, y para retornar dichos datos intercalados a dicha memoria principal
ES487814A 1979-01-26 1980-01-18 Una disposicion mejorada de inscripcion de canal a memoria Expired ES487814A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/006,980 US4298929A (en) 1979-01-26 1979-01-26 Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability

Publications (1)

Publication Number Publication Date
ES487814A1 true ES487814A1 (es) 1980-09-16

Family

ID=21723570

Family Applications (1)

Application Number Title Priority Date Filing Date
ES487814A Expired ES487814A1 (es) 1979-01-26 1980-01-18 Una disposicion mejorada de inscripcion de canal a memoria

Country Status (9)

Country Link
US (1) US4298929A (es)
EP (1) EP0013737B1 (es)
JP (1) JPS5821353B2 (es)
AU (1) AU530891B2 (es)
BR (1) BR8000314A (es)
CA (1) CA1124888A (es)
DE (1) DE2964509D1 (es)
ES (1) ES487814A1 (es)
IT (1) IT1165402B (es)

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Also Published As

Publication number Publication date
EP0013737B1 (de) 1983-01-12
IT7928240A0 (it) 1979-12-20
JPS55101182A (en) 1980-08-01
CA1124888A (en) 1982-06-01
DE2964509D1 (en) 1983-02-17
AU5386379A (en) 1980-07-31
AU530891B2 (en) 1983-08-04
US4298929A (en) 1981-11-03
BR8000314A (pt) 1980-10-07
IT1165402B (it) 1987-04-22
EP0013737A1 (de) 1980-08-06
JPS5821353B2 (ja) 1983-04-28

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970203