ES8503868A1 - Una instalacion de control de almacenamiento intermedio en un procesador de datos - Google Patents

Una instalacion de control de almacenamiento intermedio en un procesador de datos

Info

Publication number
ES8503868A1
ES8503868A1 ES532492A ES532492A ES8503868A1 ES 8503868 A1 ES8503868 A1 ES 8503868A1 ES 532492 A ES532492 A ES 532492A ES 532492 A ES532492 A ES 532492A ES 8503868 A1 ES8503868 A1 ES 8503868A1
Authority
ES
Spain
Prior art keywords
buffer
control system
storage control
partition
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES532492A
Other languages
English (en)
Other versions
ES532492A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8503868A1 publication Critical patent/ES8503868A1/es
Publication of ES532492A0 publication Critical patent/ES532492A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

SISTEMA DE CONTROL DE ALMACENAMIENTO INTERMEDIO UTILIZADO EN UN TRATADOR ESCALONADO DE DATOS.COMPRENDE UN SISTEMA DE MEMORIA QUE TIENE UNA ESTRUCTURA JERARQUICA DE DOS NIVELES COMPUESTA DE UN ALMACENAMIENTO PRINCIPAL Y UNO INTERMEDIO. EL ALMACENAMIENTO INTERMEDIO TIENE UNA PARTE DE ETIQUETAS Y UNA PARTE DE DATOS DE ACCESO INDEPENDIENTE, ESTANDO COMPUESTA CADA UNA DE LAS PARTES DE UNA PLURALIDAD DE ESPACIOS Y LA PARTE DE DATOS ESTA CONSTITUIDA POR CADA ESPECIO PUDIENDOSE SELECCIONAR UNO DE ENTRE UNA PLURALIDAD DE PASOS DE DIRECCION Y SELECCIONAR UNA DIRECCION PARA UN ACCESO A LECTURA Y UNA DIRECCION PARA UN ACCESO A ESCRITURA O INSCRIPCION PARA CADA ESPACIO, CON LO QUE SE EFECTUA SIMULTANEAMENTE UNA OPERACION DE LECTURA Y OTRA DE ESCRITURA EN EL MISMO CICLO DE MAQUINA Y EJECUTANDOSE DE NUEVO EL ACCESO A LECTURA SOLO CUANDO LOS ACCESOS A LECTURA Y ESCRITURA SE EFECTUAN PARA EL MISMO ESPACIO.
ES532492A 1983-05-16 1984-05-14 Una instalacion de control de almacenamiento intermedio en un procesador de datos Granted ES532492A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58085351A JPS59213084A (ja) 1983-05-16 1983-05-16 バッファ記憶装置のアクセス制御方式

Publications (2)

Publication Number Publication Date
ES8503868A1 true ES8503868A1 (es) 1985-03-01
ES532492A0 ES532492A0 (es) 1985-03-01

Family

ID=13856259

Family Applications (1)

Application Number Title Priority Date Filing Date
ES532492A Granted ES532492A0 (es) 1983-05-16 1984-05-14 Una instalacion de control de almacenamiento intermedio en un procesador de datos

Country Status (9)

Country Link
US (1) US5097414A (es)
EP (1) EP0125855B1 (es)
JP (1) JPS59213084A (es)
KR (1) KR890003688B1 (es)
AU (1) AU551435B2 (es)
BR (1) BR8402299A (es)
CA (1) CA1218753A (es)
DE (1) DE3485487D1 (es)
ES (1) ES532492A0 (es)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0224691B1 (en) * 1985-12-02 1993-02-10 International Business Machines Corporation A multiple read/write access memory system
JPS63257853A (ja) * 1987-04-03 1988-10-25 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン キヤツシユ・メモリ・システム
JPH0727492B2 (ja) * 1988-01-21 1995-03-29 三菱電機株式会社 緩衝記憶装置
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
US5214777A (en) * 1989-03-27 1993-05-25 Ncr Corporation High speed read/modify/write memory system and method
JPH077356B2 (ja) * 1989-05-19 1995-01-30 株式会社東芝 パイプライン方式のマイクロプロセッサ
JPH0740247B2 (ja) * 1989-06-20 1995-05-01 松下電器産業株式会社 キャッシュメモリ装置
US5442769A (en) * 1990-03-13 1995-08-15 At&T Corp. Processor having general registers with subdivisions addressable in instructions by register number and subdivision type
JP2636485B2 (ja) * 1990-09-21 1997-07-30 日本電気株式会社 キャッシュ記憶装置
JPH04145552A (ja) * 1990-10-05 1992-05-19 Nec Corp キャッシュ記憶装置
JPH04199242A (ja) * 1990-11-26 1992-07-20 Nec Corp キャッシュ記憶装置
JPH04199243A (ja) * 1990-11-26 1992-07-20 Nec Corp キャッシュ記憶装置
WO1993004431A1 (fr) * 1991-08-15 1993-03-04 Fujitsu Limited Systeme de commande de memoire tampon
JPH05143449A (ja) * 1991-11-22 1993-06-11 Fujitsu Ltd 主記憶データ書込制御方法
JP2868141B2 (ja) 1992-03-16 1999-03-10 株式会社日立製作所 ディスクアレイ装置
US5678040A (en) * 1993-10-29 1997-10-14 Motorola, Inc. Method for managing a hierarchical design transaction
US5860149A (en) * 1995-06-07 1999-01-12 Emulex Corporation Memory buffer system using a single pointer to reference multiple associated data
US5915265A (en) * 1995-12-22 1999-06-22 Intel Corporation Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system
JPH09237162A (ja) * 1996-02-23 1997-09-09 Hewlett Packard Co <Hp> 走査型データ記憶システム、及びその針摩耗管理方法、媒体摩耗管理方法、並びに残存寿命表示装置
US5924115A (en) * 1996-03-29 1999-07-13 Interval Research Corporation Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration
US6029237A (en) * 1997-10-08 2000-02-22 Dell Usa, L.P. Method for simulating the presence of a diskette drive in a NetPC computer that contains only a hard disk drive
JP2014006807A (ja) * 2012-06-26 2014-01-16 Fujitsu Ltd 演算処理装置、キャッシュメモリ制御装置及びキャッシュメモリの制御方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations
US4293910A (en) * 1979-07-02 1981-10-06 International Business Machines Corporation Reconfigurable key-in-storage means for protecting interleaved main storage
JPS5619575A (en) * 1979-07-25 1981-02-24 Fujitsu Ltd Data processing system having hierarchy memory
JPS5694567A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Busy control system for buffer memory
US4407015A (en) * 1980-11-26 1983-09-27 Burroughs Corporation Multiple event driven micro-sequencer
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
CA1187198A (en) * 1981-06-15 1985-05-14 Takashi Chiba System for controlling access to channel buffers
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache

Also Published As

Publication number Publication date
EP0125855A3 (en) 1988-05-25
DE3485487D1 (de) 1992-03-12
CA1218753A (en) 1987-03-03
JPS6215896B2 (es) 1987-04-09
BR8402299A (pt) 1984-12-26
JPS59213084A (ja) 1984-12-01
US5097414A (en) 1992-03-17
AU551435B2 (en) 1986-05-01
KR840008849A (ko) 1984-12-19
EP0125855A2 (en) 1984-11-21
KR890003688B1 (en) 1989-09-30
EP0125855B1 (en) 1992-01-29
ES532492A0 (es) 1985-03-01
AU2788784A (en) 1984-11-22

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