JPS5694567A - Busy control system for buffer memory - Google Patents

Busy control system for buffer memory

Info

Publication number
JPS5694567A
JPS5694567A JP17299579A JP17299579A JPS5694567A JP S5694567 A JPS5694567 A JP S5694567A JP 17299579 A JP17299579 A JP 17299579A JP 17299579 A JP17299579 A JP 17299579A JP S5694567 A JPS5694567 A JP S5694567A
Authority
JP
Japan
Prior art keywords
buffer memory
address
bank
access
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17299579A
Other languages
Japanese (ja)
Inventor
Akira Hattori
Terutaka Tateishi
Takeshi Shimamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17299579A priority Critical patent/JPS5694567A/en
Publication of JPS5694567A publication Critical patent/JPS5694567A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To efficiently operate a buffer memory, by constituting the buffer memory with the bank possible for readout/write-in independently in a set associative system and providing the busy control operation circuit by a set address and bank number.
CONSTITUTION: The buffer memory is constituted with a plurality of banks independently possible for readout/write-in, in a set associative system, and the address is detected with the tag pickup register TG to the access request, and the banks are used when the presence of block including the address in the buffer is clear. Further, the first access state is stored in a set competition register SCFR. In the next access, the address is once set to the register REQAR and it is chekced with the busy control operating circuit consisting of the set competition detecting logic circuit SCLG and bank usage detection circuit BBS. Further, the access inhibition signal is obtained with the logical sum of the set competition and bank usage to increase the processing efficiency of access request.
COPYRIGHT: (C)1981,JPO&Japio
JP17299579A 1979-12-28 1979-12-28 Busy control system for buffer memory Pending JPS5694567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17299579A JPS5694567A (en) 1979-12-28 1979-12-28 Busy control system for buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17299579A JPS5694567A (en) 1979-12-28 1979-12-28 Busy control system for buffer memory

Publications (1)

Publication Number Publication Date
JPS5694567A true JPS5694567A (en) 1981-07-31

Family

ID=15952223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17299579A Pending JPS5694567A (en) 1979-12-28 1979-12-28 Busy control system for buffer memory

Country Status (1)

Country Link
JP (1) JPS5694567A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59213084A (en) * 1983-05-16 1984-12-01 Fujitsu Ltd Buffer store control system
JPH04130940A (en) * 1990-09-21 1992-05-01 Nec Corp Cache memory device
JPH04145552A (en) * 1990-10-05 1992-05-19 Nec Corp Cache storage device
JPH04199243A (en) * 1990-11-26 1992-07-20 Nec Corp Cache storage device
JPH04199242A (en) * 1990-11-26 1992-07-20 Nec Corp Cache storage device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59213084A (en) * 1983-05-16 1984-12-01 Fujitsu Ltd Buffer store control system
JPS6215896B2 (en) * 1983-05-16 1987-04-09 Fujitsu Ltd
JPH04130940A (en) * 1990-09-21 1992-05-01 Nec Corp Cache memory device
JPH04145552A (en) * 1990-10-05 1992-05-19 Nec Corp Cache storage device
JPH04199243A (en) * 1990-11-26 1992-07-20 Nec Corp Cache storage device
JPH04199242A (en) * 1990-11-26 1992-07-20 Nec Corp Cache storage device

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