ES450127A1 - Timing arrangement in a computer - Google Patents

Timing arrangement in a computer

Info

Publication number
ES450127A1
ES450127A1 ES450127A ES450127A ES450127A1 ES 450127 A1 ES450127 A1 ES 450127A1 ES 450127 A ES450127 A ES 450127A ES 450127 A ES450127 A ES 450127A ES 450127 A1 ES450127 A1 ES 450127A1
Authority
ES
Spain
Prior art keywords
frequency
real
synchronization signals
measurement circuits
integer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES450127A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of ES450127A1 publication Critical patent/ES450127A1/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/223Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14Time supervision arrangements, e.g. real time clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Bus Control (AREA)

Abstract

A time regulation arrangement for computers, intended to determine the synchronization of the microprogram, as well as to determine the times for operations performed in real time, for example interruption of the clock in the program, characterized in that it includes a common clock oscillator to of generating synchronization signals for the computer control unit as well as for the real-time measurement circuits, a frequency divider being arranged to divide the frequency of the clock oscillator in such a way that it adapts to the duration of the period between the operations performed in real time, and the frequency of the clock oscillator being an integer multiple of the frequency of the impulses of the steps to the time measurement circuits, and because the division ratio of said frequency divider is adjustable from as possible by dividing by an integer of the oscillator frequency of re loj, keep the synchronization signals constant for the real-time measurement circuits by changing the frequency of the synchronization signals for the computer control unit, depending on the working conditions, thereby the number of duty cycles per step pulse interval always results in an integer. (Machine-translation by Google Translate, not legally binding)
ES450127A 1975-07-25 1976-07-24 Timing arrangement in a computer Expired ES450127A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE7508478A SE387451B (en) 1975-07-25 1975-07-25 COMPUTER TIMING DEVICE

Publications (1)

Publication Number Publication Date
ES450127A1 true ES450127A1 (en) 1977-08-01

Family

ID=20325204

Family Applications (1)

Application Number Title Priority Date Filing Date
ES450127A Expired ES450127A1 (en) 1975-07-25 1976-07-24 Timing arrangement in a computer

Country Status (12)

Country Link
AU (1) AU496975B2 (en)
BR (1) BR7604772A (en)
CA (1) CA1075821A (en)
ES (1) ES450127A1 (en)
FR (1) FR2319156A1 (en)
GB (1) GB1531603A (en)
HU (1) HU174135B (en)
IT (1) IT1062469B (en)
MX (1) MX143013A (en)
NL (1) NL187938C (en)
SE (1) SE387451B (en)
YU (1) YU37407B (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678463A (en) * 1970-04-27 1972-07-18 Bell Telephone Labor Inc Controlled pause in data processing appartus
US3714635A (en) * 1972-01-31 1973-01-30 Ibm Standard adapter method and apparatus

Also Published As

Publication number Publication date
NL7607781A (en) 1977-01-27
AU1557176A (en) 1978-01-12
FR2319156A1 (en) 1977-02-18
GB1531603A (en) 1978-11-08
BR7604772A (en) 1977-08-02
MX143013A (en) 1981-02-10
YU178376A (en) 1983-04-27
HU174135B (en) 1979-11-28
IT1062469B (en) 1984-10-10
SE387451B (en) 1976-09-06
YU37407B (en) 1984-08-31
CA1075821A (en) 1980-04-15
NL187938B (en) 1991-09-16
NL187938C (en) 1992-02-17
AU496975B2 (en) 1978-11-16
FR2319156B1 (en) 1980-04-18

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