ES440887A1 - Unidad de control de acceso para controlar un dispositivo dememoria. - Google Patents
Unidad de control de acceso para controlar un dispositivo dememoria.Info
- Publication number
- ES440887A1 ES440887A1 ES440887A ES440887A ES440887A1 ES 440887 A1 ES440887 A1 ES 440887A1 ES 440887 A ES440887 A ES 440887A ES 440887 A ES440887 A ES 440887A ES 440887 A1 ES440887 A1 ES 440887A1
- Authority
- ES
- Spain
- Prior art keywords
- cycle
- memory
- address
- coincidence
- memory unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
- G06F9/267—Microinstruction selection based on results of processing by instruction selection on output of storage
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP49105367A JPS605978B2 (ja) | 1974-09-12 | 1974-09-12 | 記憶装置のアクセス制御方式 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES440887A1 true ES440887A1 (es) | 1977-06-16 |
Family
ID=14405732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES440887A Expired ES440887A1 (es) | 1974-09-12 | 1975-09-11 | Unidad de control de acceso para controlar un dispositivo dememoria. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4027291A (es) |
JP (1) | JPS605978B2 (es) |
CA (1) | CA1033073A (es) |
DE (1) | DE2539211C2 (es) |
ES (1) | ES440887A1 (es) |
FR (1) | FR2284926A1 (es) |
GB (1) | GB1493448A (es) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4099231A (en) * | 1975-10-01 | 1978-07-04 | Digital Equipment Corporation | Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle |
JPS52124825A (en) * | 1976-04-12 | 1977-10-20 | Mitsubishi Electric Corp | High performance memory circuit |
GB1590835A (en) * | 1976-11-12 | 1981-06-10 | Rolls Royce | Data processing methods and systems |
JPS5465554U (es) * | 1977-10-18 | 1979-05-09 | ||
US4204252A (en) * | 1978-03-03 | 1980-05-20 | Digital Equipment Corporation | Writeable control store for use in a data processing system |
JPS5522298A (en) * | 1978-07-31 | 1980-02-16 | Ibm | Data processing system |
US4236205A (en) * | 1978-10-23 | 1980-11-25 | International Business Machines Corporation | Access-time reduction control circuit and process for digital storage devices |
US4279015A (en) * | 1979-06-13 | 1981-07-14 | Ford Motor Company | Binary output processing in a digital computer using a time-sorted stack |
US4283761A (en) * | 1979-06-13 | 1981-08-11 | Ford Motor Company | Binary input/output processing in a digital computer using assigned times for input and output data |
US4336602A (en) * | 1979-09-24 | 1982-06-22 | Control Data Corporation | Network for generating modified microcode addresses |
US4393444A (en) * | 1980-11-06 | 1983-07-12 | Rca Corporation | Memory addressing circuit for converting sequential input data to interleaved output data sequence using multiple memories |
US4541045A (en) * | 1981-09-21 | 1985-09-10 | Racal-Milgo, Inc. | Microprocessor architecture employing efficient operand and instruction addressing |
US4551798A (en) * | 1982-11-03 | 1985-11-05 | Burroughs Corporation | Multiple control stores in a pipelined microcontroller for handling nester subroutines |
US4586127A (en) * | 1982-11-03 | 1986-04-29 | Burroughs Corp. | Multiple control stores for a pipelined microcontroller |
US4546431A (en) * | 1982-11-03 | 1985-10-08 | Burroughs Corporation | Multiple control stores in a pipelined microcontroller for handling jump and return subroutines |
JPS603036A (ja) * | 1983-06-20 | 1985-01-09 | Hitachi Ltd | 処理履歴情報の取得・参照方式 |
JPS62164133A (ja) * | 1986-01-16 | 1987-07-20 | Toshiba Corp | マイクロプログラム制御装置 |
US4914582A (en) * | 1986-06-27 | 1990-04-03 | Hewlett-Packard Company | Cache tag lookaside |
JPS6356754A (ja) * | 1986-08-28 | 1988-03-11 | Toshiba Corp | 入出力チヤネル |
US5155826A (en) * | 1988-12-05 | 1992-10-13 | Fadem Richard J | Memory paging method and apparatus |
CA2030404A1 (en) * | 1989-11-27 | 1991-05-28 | Robert W. Horst | Microinstruction sequencer |
US11550577B2 (en) * | 2019-05-15 | 2023-01-10 | Western Digital Technologies, Inc. | Memory circuit for halting a program counter while fetching an instruction sequence from memory |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3629842A (en) * | 1970-04-30 | 1971-12-21 | Bell Telephone Labor Inc | Multiple memory-accessing system |
BE789583A (fr) * | 1971-10-01 | 1973-02-01 | Sanders Associates Inc | Appareil de controle de programme pour machine de traitement del'information |
US3866180A (en) * | 1973-04-02 | 1975-02-11 | Amdahl Corp | Having an instruction pipeline for concurrently processing a plurality of instructions |
JPS5034134A (es) * | 1973-07-27 | 1975-04-02 | ||
US3990051A (en) * | 1975-03-26 | 1976-11-02 | Honeywell Information Systems, Inc. | Memory steering in a data processing system |
-
1974
- 1974-09-12 JP JP49105367A patent/JPS605978B2/ja not_active Expired
-
1975
- 1975-09-03 DE DE2539211A patent/DE2539211C2/de not_active Expired
- 1975-09-05 US US05/610,642 patent/US4027291A/en not_active Expired - Lifetime
- 1975-09-09 FR FR7527591A patent/FR2284926A1/fr active Granted
- 1975-09-11 ES ES440887A patent/ES440887A1/es not_active Expired
- 1975-09-12 CA CA235321A patent/CA1033073A/en not_active Expired
- 1975-09-12 GB GB37682/75A patent/GB1493448A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2284926A1 (fr) | 1976-04-09 |
FR2284926B1 (es) | 1979-02-02 |
DE2539211C2 (de) | 1983-10-13 |
CA1033073A (en) | 1978-06-13 |
JPS605978B2 (ja) | 1985-02-15 |
JPS5132143A (en) | 1976-03-18 |
GB1493448A (en) | 1977-11-30 |
DE2539211A1 (de) | 1976-03-25 |
US4027291A (en) | 1977-05-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19970217 |