ES2100159T3 - Circuito de sincronismo. - Google Patents

Circuito de sincronismo.

Info

Publication number
ES2100159T3
ES2100159T3 ES90203446T ES90203446T ES2100159T3 ES 2100159 T3 ES2100159 T3 ES 2100159T3 ES 90203446 T ES90203446 T ES 90203446T ES 90203446 T ES90203446 T ES 90203446T ES 2100159 T3 ES2100159 T3 ES 2100159T3
Authority
ES
Spain
Prior art keywords
signal
digital input
input signal
clock signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90203446T
Other languages
English (en)
Inventor
Patrick Ampe
De Pol Daniel Frans Jozefi Van
Leon Cloetens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell NV
Original Assignee
Alcatel Bell NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Bell NV filed Critical Alcatel Bell NV
Application granted granted Critical
Publication of ES2100159T3 publication Critical patent/ES2100159T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Selective Calling Equipment (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Synchronizing For Television (AREA)

Abstract

UN CIRCUITO DE SINCRONIZACION PARA SINCRONIZAR UNA SEÑAL DE ENTRADA DIGITAL (DIN) CON UNA SEÑAL DE RELOJ (CK1) INCLUYE UN CIRCUITO DE DETECCION (DC) QUE COMPRUEBA SI UNA MUESTRA PRESENTE (SA) DE UNA SEÑAL DE RELOJ (CK3) QUE SE ESTA SINCRONIZANDO CON LA SEÑAL DE ENTRADA DIGITAL, ES IGUAL A LA MUESTRA ANTERIOR (SB), AMBAS MUESTRAS SE HAN TOMADO A UN INTERVALO IGUAL AL PERIODO (T) DE LA SEÑAL DE RELOJ SINCRONIZADA CON LA SEÑAL DE SALIDA. CUANDO LAS MUESTRAS DIFIEREN, EL CIRCUITO DE DETECCION GENERA UNA SEÑAL DE AJUSTE DE FASE (CLR), QUE ACTIVA UN CIRCUITO DE AJUSTE DE FASE (PAC) PARA ASEGURAR UNA VUELTA AL SINCRONISMO DESFASANDO LA SEÑAL (ES) QUE CONTROLA EL MUESTREO DE LA SEÑAL DE ENTRADA DIGITAL.
ES90203446T 1990-12-18 1990-12-18 Circuito de sincronismo. Expired - Lifetime ES2100159T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP90203446A EP0491090B1 (en) 1990-12-18 1990-12-18 Synchronizing circuit

Publications (1)

Publication Number Publication Date
ES2100159T3 true ES2100159T3 (es) 1997-06-16

Family

ID=8205209

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90203446T Expired - Lifetime ES2100159T3 (es) 1990-12-18 1990-12-18 Circuito de sincronismo.

Country Status (9)

Country Link
US (1) US5272391A (es)
EP (1) EP0491090B1 (es)
JP (1) JPH04341013A (es)
KR (1) KR0165683B1 (es)
AT (1) ATE150240T1 (es)
AU (1) AU646702B2 (es)
CA (1) CA2057831C (es)
DE (1) DE69030192T2 (es)
ES (1) ES2100159T3 (es)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2711869B1 (fr) * 1993-10-21 1995-12-01 Alcatel Nv Dispositif de synchronisation pour réseau de communication optique.
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
DE4442506A1 (de) * 1994-11-30 1996-06-05 Sel Alcatel Ag Synchronisierungsüberachung in einem Netzwerk
JP2773669B2 (ja) * 1995-03-01 1998-07-09 日本電気株式会社 ディジタルｐｌｌ回路
US5793233A (en) * 1996-05-30 1998-08-11 Sun Microsystems, Inc. Apparatus and method for generating a phase detection signal that coordinates the phases of separate clock signals
US6269135B1 (en) * 1998-01-14 2001-07-31 Tropian, Inc. Digital phase discriminations based on frequency sampling
US6985547B2 (en) 1999-09-27 2006-01-10 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations System and method of digital system performance enhancement
US7027545B2 (en) * 2001-05-09 2006-04-11 Tropian, Inc. Data sampler for digital frequency/phase determination
DE10122702C2 (de) * 2001-05-10 2003-08-21 Infineon Technologies Ag Verfahren und Vorrichtung zum Erzeugen eines zweiten Signals mit einem auf einem zweiten Takt basierenden Takt aus einem ersten Signal mit einem ersten Takt
US7003064B2 (en) * 2002-01-07 2006-02-21 International Business Machines Corporation Method and apparatus for periodic phase alignment
DE10255685B3 (de) * 2002-11-28 2004-07-29 Infineon Technologies Ag Taktsynchronisationsschaltung
US7120814B2 (en) * 2003-06-30 2006-10-10 Raytheon Company System and method for aligning signals in multiple clock systems
JP4927033B2 (ja) * 2008-05-30 2012-05-09 Ｎｔｔエレクトロニクス株式会社 クロック再生用信号生成方法及びクロック再生回路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4039960A (en) * 1976-06-29 1977-08-02 International Telephone And Telegraph Corporation Automatic phasing circuit to transfer digital data from an external interface circuit to an internal interface circuit
EP0054322B1 (en) * 1980-12-12 1985-07-03 Philips Electronics Uk Limited Phase sensitive detector
US4873703A (en) * 1985-09-27 1989-10-10 Hewlett-Packard Company Synchronizing system
US4706033A (en) * 1986-05-20 1987-11-10 Northern Telecom Limited Data recovery and clock circuit for use in data test equipment
CA1301260C (en) * 1988-01-21 1992-05-19 Norio Yoshida Synchronizer for establishing synchronization between data and clock signals
EP0364451A1 (en) * 1988-03-26 1990-04-25 BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap Synchronizing circuit
JP2512786B2 (ja) * 1988-07-18 1996-07-03 富士通株式会社 位相整合回路
JP2536929B2 (ja) * 1989-07-21 1996-09-25 富士通株式会社 位相整合回路

Also Published As

Publication number Publication date
DE69030192T2 (de) 1997-07-24
JPH04341013A (ja) 1992-11-27
KR920013932A (ko) 1992-07-30
US5272391A (en) 1993-12-21
AU646702B2 (en) 1994-03-03
KR0165683B1 (ko) 1999-03-20
AU8826591A (en) 1992-06-25
CA2057831C (en) 1998-12-15
EP0491090B1 (en) 1997-03-12
CA2057831A1 (en) 1992-06-19
EP0491090A1 (en) 1992-06-24
ATE150240T1 (de) 1997-03-15
DE69030192D1 (de) 1997-04-17

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